[people/ms/u-boot.git] / include / configs / zipitz2.h

/*
 * Aeronix Zipit Z2 configuration file
 *
 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Board Configuration Options
 */
#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
#define	CONFIG_ZIPITZ2		1	/* Zipit Z2 board */
#define	CONFIG_SYS_TEXT_BASE	0x0

#undef	CONFIG_BOARD_LATE_INIT
#undef	CONFIG_SKIP_LOWLEVEL_INIT
#define	CONFIG_PREBOOT

/*
 * Environment settings
 */
#define	CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_ADDR			0x40000
#define CONFIG_ENV_SIZE			0x20000

/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF

#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
#define	CONFIG_ARCH_CPU_INIT

#define	CONFIG_BOOTCOMMAND						\
	"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
	"then "								\
		"source 0xa0000000; "					\
	"else "								\
		"bootm 0x60000; "					\
	"fi; "
#define	CONFIG_BOOTARGS							\
	"console=tty0 console=ttyS2,115200 fbcon=rotate:3"
#define	CONFIG_TIMESTAMP
#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
#define	CONFIG_CMDLINE_TAG
#define	CONFIG_SETUP_MEMORY_TAGS
#define	CONFIG_SYS_TEXT_BASE		0x0
#define	CONFIG_LZMA			/* LZMA compression support */

/*
 * Serial Console Configuration
 * STUART - the lower serial port on Colibri board
 */
#define	CONFIG_PXA_SERIAL
#define	CONFIG_STUART			1
#define CONFIG_CONS_INDEX		2
#define	CONFIG_BAUDRATE			115200

/*
 * Bootloader Components Configuration
 */
#define	CONFIG_CMD_ENV
#define	CONFIG_CMD_MMC
#define	CONFIG_CMD_SPI

/*
 * MMC Card Configuration
 */
#ifdef	CONFIG_CMD_MMC
#define	CONFIG_MMC
#define	CONFIG_GENERIC_MMC
#define	CONFIG_PXA_MMC_GENERIC
#define	CONFIG_SYS_MMC_BASE		0xF0000000
#define	CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define	CONFIG_DOS_PARTITION
#endif

/*
 * SPI and LCD
 */
#ifdef	CONFIG_CMD_SPI
#define	CONFIG_SOFT_SPI
#define	CONFIG_LCD
#define	CONFIG_PXA_LCD
#define	CONFIG_LMS283GF05
#define	CONFIG_VIDEO_LOGO
#define	CONFIG_CMD_BMP
#define	CONFIG_SPLASH_SCREEN
#define	CONFIG_SPLASH_SCREEN_ALIGN
#define	CONFIG_VIDEO_BMP_GZIP
#define	CONFIG_VIDEO_BMP_RLE8
#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)

#define	SPI_DELAY	udelay(10)
#define	SPI_SDA(val)	zipitz2_spi_sda(val)
#define	SPI_SCL(val)	zipitz2_spi_scl(val)
#define	SPI_READ	zipitz2_spi_read()
#ifndef	__ASSEMBLY__
void zipitz2_spi_sda(int);
void zipitz2_spi_scl(int);
unsigned char zipitz2_spi_read(void);
#endif
#endif

/*
 * KGDB
 */
#ifdef	CONFIG_CMD_KGDB
#define	CONFIG_KGDB_BAUDRATE		230400		/* speed to run kgdb serial port */
#endif

/*
 * HUSH Shell Configuration
 */
#define	CONFIG_SYS_HUSH_PARSER		1

#define	CONFIG_SYS_LONGHELP				/* undef to save memory	*/
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define	CONFIG_SYS_DEVICE_NULLDEV	1

/*
 * Clock Configuration
 */
#define CONFIG_SYS_CPUSPEED		0x190		/* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */

/*
 * SRAM Map
 */
#define	PHYS_SRAM			0x5c000000	/* SRAM Bank #1 */
#define	PHYS_SRAM_SIZE			0x00040000	/* 256k */

/*
 * DRAM Map
 */
#define	CONFIG_NR_DRAM_BANKS		1		/* We have 1 bank of DRAM */
#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
#define	PHYS_SDRAM_1_SIZE		0x02000000	/* 32 MB */

#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
#define	CONFIG_SYS_DRAM_SIZE		0x02000000	/* 32 MB DRAM */

#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */

#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)

/*
 * NOR FLASH
 */
#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
#define PHYS_FLASH_SIZE			0x00800000	/* 8 MB */
#define PHYS_FLASH_SECT_SIZE		0x00010000	/* 64 KB sectors */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER		1
#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT

#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
#define CONFIG_SYS_FLASH_WRITE_TOUT	240000
#define CONFIG_SYS_FLASH_LOCK_TOUT	240000
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
#define CONFIG_SYS_FLASH_PROTECTION

/*
 * GPIO settings
 */
#define CONFIG_SYS_GAFR0_L_VAL	0x02000140
#define CONFIG_SYS_GAFR0_U_VAL	0x59188000
#define CONFIG_SYS_GAFR1_L_VAL	0x63900002
#define CONFIG_SYS_GAFR1_U_VAL	0xaaa03950
#define CONFIG_SYS_GAFR2_L_VAL	0x0aaaaaaa
#define CONFIG_SYS_GAFR2_U_VAL	0x29000308
#define CONFIG_SYS_GAFR3_L_VAL	0x54000000
#define CONFIG_SYS_GAFR3_U_VAL	0x000000d5
#define CONFIG_SYS_GPCR0_VAL	0x00000000
#define CONFIG_SYS_GPCR1_VAL	0x00000020
#define CONFIG_SYS_GPCR2_VAL	0x00000000
#define CONFIG_SYS_GPCR3_VAL	0x00000000
#define CONFIG_SYS_GPDR0_VAL	0xdafcee00
#define CONFIG_SYS_GPDR1_VAL	0xffa3aaab
#define CONFIG_SYS_GPDR2_VAL	0x8fe9ffff
#define CONFIG_SYS_GPDR3_VAL	0x001b1f8a
#define CONFIG_SYS_GPSR0_VAL	0x06080400
#define CONFIG_SYS_GPSR1_VAL	0x007f0000
#define CONFIG_SYS_GPSR2_VAL	0x032a0000
#define CONFIG_SYS_GPSR3_VAL	0x00000180

#define CONFIG_SYS_PSSR_VAL	0x30

/*
 * Clock settings
 */
#define CONFIG_SYS_CKEN		0x00511220
#define CONFIG_SYS_CCCR		0x00000190

/*
 * Memory settings
 */
#define CONFIG_SYS_MSC0_VAL	0x2ffc38f8
#define CONFIG_SYS_MSC1_VAL	0x0000ccd1
#define CONFIG_SYS_MSC2_VAL	0x0000b884
#define CONFIG_SYS_MDCNFG_VAL	0x08000ba9
#define CONFIG_SYS_MDREFR_VAL	0x2011a01e
#define CONFIG_SYS_MDMRS_VAL	0x00000000
#define CONFIG_SYS_FLYCNFG_VAL	0x00010001
#define CONFIG_SYS_SXCNFG_VAL	0x40044004

/*
 * PCMCIA and CF Interfaces
 */
#define CONFIG_SYS_MECR_VAL	0x00000001
#define CONFIG_SYS_MCMEM0_VAL	0x00014307
#define CONFIG_SYS_MCMEM1_VAL	0x00014307
#define CONFIG_SYS_MCATT0_VAL	0x0001c787
#define CONFIG_SYS_MCATT1_VAL	0x0001c787
#define CONFIG_SYS_MCIO0_VAL	0x0001430f
#define CONFIG_SYS_MCIO1_VAL	0x0001430f

#endif	/* __CONFIG_H */
Commit	Line	Data
bc3a4a53 MV	1	/*
	2	* Aeronix Zipit Z2 configuration file
	3	*
	4	* Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
bc3a4a53 MV	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Board Configuration Options
	14	*/
abc20aba	15	#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
bc3a4a53	16	#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
9b3d167f	17	#define CONFIG_SYS_TEXT_BASE 0x0
bc3a4a53	18
9660e442	19	#undef CONFIG_BOARD_LATE_INIT
bc3a4a53	20	#undef CONFIG_SKIP_LOWLEVEL_INIT
aac316a8	21	#define CONFIG_PREBOOT
bc3a4a53 MV	22
	23	/*
	24	* Environment settings
	25	*/
	26	#define CONFIG_ENV_OVERWRITE
	27	#define CONFIG_ENV_IS_IN_FLASH 1
	28	#define CONFIG_ENV_ADDR 0x40000
	29	#define CONFIG_ENV_SIZE 0x20000
	30
89959081 SG	31	/* we will never enable dcache, because we have to setup MMU first */
	32	#define CONFIG_SYS_DCACHE_OFF
	33
24e84c3d	34	#define CONFIG_SYS_MALLOC_LEN (128*1024)
24e84c3d	35	#define CONFIG_ARCH_CPU_INIT
bc3a4a53 MV	36
bc3a4a53 MV	37	#define CONFIG_BOOTCOMMAND \
81f731ca VK	38	"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
81f731ca VK	39	"then " \
bc3a4a53 MV	40	"source 0xa0000000; " \
	41	"else " \
	42	"bootm 0x60000; " \
	43	"fi; "
	44	#define CONFIG_BOOTARGS \
	45	"console=tty0 console=ttyS2,115200 fbcon=rotate:3"
	46	#define CONFIG_TIMESTAMP
	47	#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
	48	#define CONFIG_CMDLINE_TAG
	49	#define CONFIG_SETUP_MEMORY_TAGS
24e84c3d	50	#define CONFIG_SYS_TEXT_BASE 0x0
bc3a4a53 MV	51	#define CONFIG_LZMA /* LZMA compression support */
	52
	53	/*
	54	* Serial Console Configuration
	55	* STUART - the lower serial port on Colibri board
	56	*/
	57	#define CONFIG_PXA_SERIAL
	58	#define CONFIG_STUART 1
ce6971cd	59	#define CONFIG_CONS_INDEX 2
bc3a4a53	60	#define CONFIG_BAUDRATE 115200
bc3a4a53 MV	61
	62	/*
	63	* Bootloader Components Configuration
	64	*/
bc3a4a53	65	#define CONFIG_CMD_ENV
bc3a4a53 MV	66	#define CONFIG_CMD_MMC
	67	#define CONFIG_CMD_SPI
	68
	69	/*
	70	* MMC Card Configuration
	71	*/
	72	#ifdef CONFIG_CMD_MMC
	73	#define CONFIG_MMC
81f731ca VK	74	#define CONFIG_GENERIC_MMC
81f731ca VK	75	#define CONFIG_PXA_MMC_GENERIC
bc3a4a53 MV	76	#define CONFIG_SYS_MMC_BASE 0xF0000000
	77	#define CONFIG_CMD_FAT
	78	#define CONFIG_CMD_EXT2
	79	#define CONFIG_DOS_PARTITION
	80	#endif
	81
	82	/*
	83	* SPI and LCD
	84	*/
	85	#ifdef CONFIG_CMD_SPI
	86	#define CONFIG_SOFT_SPI
	87	#define CONFIG_LCD
0698095a	88	#define CONFIG_PXA_LCD
bc3a4a53 MV	89	#define CONFIG_LMS283GF05
	90	#define CONFIG_VIDEO_LOGO
	91	#define CONFIG_CMD_BMP
	92	#define CONFIG_SPLASH_SCREEN
	93	#define CONFIG_SPLASH_SCREEN_ALIGN
	94	#define CONFIG_VIDEO_BMP_GZIP
	95	#define CONFIG_VIDEO_BMP_RLE8
	96	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
bc3a4a53 MV	97
	98	#define SPI_DELAY udelay(10)
	99	#define SPI_SDA(val) zipitz2_spi_sda(val)
	100	#define SPI_SCL(val) zipitz2_spi_scl(val)
	101	#define SPI_READ zipitz2_spi_read()
	102	#ifndef __ASSEMBLY__
	103	void zipitz2_spi_sda(int);
	104	void zipitz2_spi_scl(int);
	105	unsigned char zipitz2_spi_read(void);
	106	#endif
	107	#endif
	108
	109	/*
	110	* KGDB
	111	*/
	112	#ifdef CONFIG_CMD_KGDB
	113	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
bc3a4a53 MV	114	#endif
	115
	116	/*
	117	* HUSH Shell Configuration
	118	*/
	119	#define CONFIG_SYS_HUSH_PARSER 1
bc3a4a53 MV	120
bc3a4a53 MV	121	#define CONFIG_SYS_LONGHELP /* undef to save memory */
bc3a4a53 MV	122	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	123	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	124	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	125	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	126	#define CONFIG_SYS_DEVICE_NULLDEV 1
	127
	128	/*
	129	* Clock Configuration
	130	*/
bc3a4a53 MV	131	#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
bc3a4a53 MV	132
76d4ae25 VK	133	/*
	134	* SRAM Map
	135	*/
	136	#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
	137	#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
	138
bc3a4a53 MV	139	/*
	140	* DRAM Map
	141	*/
	142	#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
	143	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	144	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
	145
	146	#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
	147	#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
	148
	149	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
	150	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	151
	152	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
	153
6ef6eb91	154	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
76d4ae25	155	#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
6ef6eb91	156
bc3a4a53 MV	157	/*
	158	* NOR FLASH
	159	*/
	160	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	161	#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
	162	#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
	163	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	164
	165	#define CONFIG_SYS_FLASH_CFI
	166	#define CONFIG_FLASH_CFI_DRIVER 1
	167	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	168
	169	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
	170	#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
	171
	172	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	173	#define CONFIG_SYS_MAX_FLASH_SECT 256
	174
	175	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	176
f90aea2a MV	177	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
	178	#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
	179	#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
	180	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
bc3a4a53 MV	181	#define CONFIG_SYS_FLASH_PROTECTION
	182
	183	/*
	184	* GPIO settings
	185	*/
	186	#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
	187	#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
	188	#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
	189	#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
	190	#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
	191	#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
	192	#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
	193	#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
	194	#define CONFIG_SYS_GPCR0_VAL 0x00000000
	195	#define CONFIG_SYS_GPCR1_VAL 0x00000020
	196	#define CONFIG_SYS_GPCR2_VAL 0x00000000
	197	#define CONFIG_SYS_GPCR3_VAL 0x00000000
	198	#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
	199	#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
24e84c3d	200	#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
bc3a4a53 MV	201	#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
	202	#define CONFIG_SYS_GPSR0_VAL 0x06080400
	203	#define CONFIG_SYS_GPSR1_VAL 0x007f0000
	204	#define CONFIG_SYS_GPSR2_VAL 0x032a0000
	205	#define CONFIG_SYS_GPSR3_VAL 0x00000180
	206
	207	#define CONFIG_SYS_PSSR_VAL 0x30
	208
	209	/*
	210	* Clock settings
	211	*/
	212	#define CONFIG_SYS_CKEN 0x00511220
	213	#define CONFIG_SYS_CCCR 0x00000190
	214
	215	/*
	216	* Memory settings
	217	*/
	218	#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
	219	#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
	220	#define CONFIG_SYS_MSC2_VAL 0x0000b884
	221	#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
	222	#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
	223	#define CONFIG_SYS_MDMRS_VAL 0x00000000
	224	#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
	225	#define CONFIG_SYS_SXCNFG_VAL 0x40044004
	226
	227	/*
	228	* PCMCIA and CF Interfaces
	229	*/
	230	#define CONFIG_SYS_MECR_VAL 0x00000001
	231	#define CONFIG_SYS_MCMEM0_VAL 0x00014307
	232	#define CONFIG_SYS_MCMEM1_VAL 0x00014307
	233	#define CONFIG_SYS_MCATT0_VAL 0x0001c787
	234	#define CONFIG_SYS_MCATT1_VAL 0x0001c787
	235	#define CONFIG_SYS_MCIO0_VAL 0x0001430f
	236	#define CONFIG_SYS_MCIO1_VAL 0x0001430f
	237
	238	#endif /* __CONFIG_H */