[thirdparty/u-boot.git] / include / configs / zmx25.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (c) 2011 Graf-Syteco, Matthias Weisser
 * <weisserm@arcor.de>
 *
 * Configuation settings for the zmx25 board
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

#define CONFIG_SYS_TIMER_RATE		32768
#define CONFIG_SYS_TIMER_COUNTER	\
	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)

#define CONFIG_MACH_TYPE	MACH_TYPE_ZMX25
/*
 * Environment settings
 */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"gs_fast_boot=setenv bootdelay 5\0" \
	"gs_slow_boot=setenv bootdelay 10\0" \
	"bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
		"fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
		"bootm 0x81000000; bootelf 0x81000000\0"

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Hardware drivers
 */

/*
 * Serial
 */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART2_BASE

/*
 * Ethernet
 */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR		0x00

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

/*
 * Additional command
 */

/*
 * USB
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT	1
#define CONFIG_MXC_USB_PORTSC	MXC_EHCI_MODE_SERIAL
#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
#define CONFIG_EHCI_IS_TDI
#endif /* CONFIG_CMD_USB */

/* SDRAM */
#define PHYS_SDRAM		0x80000000	/* start address of LPDDRRAM */
#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */

#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR	0x78020000	/* end of internal SRAM */

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		0xA0000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

/*
 * CFI FLASH driver setup
 */

#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE


/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(0x400000 - 0x8000)

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
39f0023e MW	2	/*
	3	* (c) 2011 Graf-Syteco, Matthias Weisser
	4	* <weisserm@arcor.de>
	5	*
	6	* Configuation settings for the zmx25 board
39f0023e MW	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
3dae5b51 RH	12	#include <asm/arch/imx-regs.h>
3dae5b51 RH	13
3dae5b51 RH	14	#define CONFIG_SYS_TIMER_RATE 32768
	15	#define CONFIG_SYS_TIMER_COUNTER \
	16	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
	17
94ba26f2	18	#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25
39f0023e MW	19	/*
	20	* Environment settings
	21	*/
	22	#define CONFIG_EXTRA_ENV_SETTINGS \
	23	"gs_fast_boot=setenv bootdelay 5\0" \
	24	"gs_slow_boot=setenv bootdelay 10\0" \
	25	"bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
	26	"fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
	27	"bootm 0x81000000; bootelf 0x81000000\0"
	28
	29	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	30	#define CONFIG_SETUP_MEMORY_TAGS
	31	#define CONFIG_INITRD_TAG
39f0023e	32
39f0023e MW	33	/*
	34	* Hardware drivers
	35	*/
	36
39f0023e MW	37	/*
	38	* Serial
	39	*/
	40	#define CONFIG_MXC_UART
40f6fffe	41	#define CONFIG_MXC_UART_BASE UART2_BASE
39f0023e MW	42
	43	/*
	44	* Ethernet
	45	*/
	46	#define CONFIG_FEC_MXC
	47	#define CONFIG_FEC_MXC_PHYADDR 0x00
39f0023e MW	48
	49	/*
	50	* BOOTP options
	51	*/
	52	#define CONFIG_BOOTP_BOOTFILESIZE
39f0023e MW	53
	54	/*
	55	* Command line configuration.
	56	*/
39f0023e	57
39f0023e MW	58	/*
	59	* Additional command
	60	*/
39f0023e	61
39f0023e MW	62	/*
	63	* USB
	64	*/
	65	#ifdef CONFIG_CMD_USB
39f0023e MW	66	#define CONFIG_USB_EHCI_MXC
39f0023e MW	67	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
9fa3d093 BT	68	#define CONFIG_MXC_USB_PORT 1
	69	#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
	70	#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY \| MXC_EHCI_IPPUE_DOWN)
39f0023e	71	#define CONFIG_EHCI_IS_TDI
39f0023e MW	72	#endif /* CONFIG_CMD_USB */
	73
	74	/* SDRAM */
39f0023e MW	75	#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */
	76	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	77
	78	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	79	#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */
	80
	81	/*
	82	* FLASH and environment organization
	83	*/
	84	#define CONFIG_SYS_FLASH_BASE 0xA0000000
	85	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	86	#define CONFIG_SYS_MAX_FLASH_SECT 256
	87
39f0023e MW	88	/*
	89	* CFI FLASH driver setup
	90	*/
39f0023e MW	91
	92	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
	93
39f0023e MW	94
	95	/*
	96	* Size of malloc() pool
	97	*/
	98	#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
39f0023e MW	99
39f0023e MW	100	#endif /* __CONFIG_H */