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0f2cbe3f | 1 | /* |
34e026f9 | 2 | * Copyright 2008-2014 Freescale Semiconductor, Inc. |
0f2cbe3f JY |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * Version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef _DDR_SPD_H_ | |
10 | #define _DDR_SPD_H_ | |
11 | ||
12 | /* | |
13 | * Format from "JEDEC Standard No. 21-C, | |
14 | * Appendix D: Rev 1.0: SPD's for DDR SDRAM | |
15 | */ | |
16 | typedef struct ddr1_spd_eeprom_s { | |
17 | unsigned char info_size; /* 0 # bytes written into serial memory */ | |
18 | unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ | |
19 | unsigned char mem_type; /* 2 Fundamental memory type */ | |
20 | unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ | |
21 | unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ | |
22 | unsigned char nrows; /* 5 Number of DIMM Banks */ | |
23 | unsigned char dataw_lsb; /* 6 Data Width of this assembly */ | |
24 | unsigned char dataw_msb; /* 7 ... Data Width continuation */ | |
25 | unsigned char voltage; /* 8 Voltage intf std of this assembly */ | |
26 | unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ | |
27 | unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ | |
28 | unsigned char config; /* 11 DIMM Configuration type */ | |
29 | unsigned char refresh; /* 12 Refresh Rate/Type */ | |
30 | unsigned char primw; /* 13 Primary SDRAM Width */ | |
31 | unsigned char ecw; /* 14 Error Checking SDRAM width */ | |
32 | unsigned char min_delay; /* 15 for Back to Back Random Address */ | |
33 | unsigned char burstl; /* 16 Burst Lengths Supported */ | |
34 | unsigned char nbanks; /* 17 # of Banks on SDRAM Device */ | |
35 | unsigned char cas_lat; /* 18 CAS# Latencies Supported */ | |
36 | unsigned char cs_lat; /* 19 CS# Latency */ | |
37 | unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ | |
38 | unsigned char mod_attr; /* 21 SDRAM Module Attributes */ | |
39 | unsigned char dev_attr; /* 22 SDRAM Device Attributes */ | |
40 | unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */ | |
41 | unsigned char clk_access2; /* 24 SDRAM Access from | |
93e14596 | 42 | Clk @ CL=X-0.5 (tAC) */ |
0f2cbe3f JY |
43 | unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */ |
44 | unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */ | |
45 | unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ | |
46 | unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ | |
47 | unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ | |
48 | unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ | |
49 | unsigned char bank_dens; /* 31 Density of each bank on module */ | |
50 | unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clk */ | |
51 | unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clk */ | |
52 | unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */ | |
53 | unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */ | |
54 | unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */ | |
55 | unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ | |
56 | unsigned char trfc; /* 42 Min Auto to Active period tRFC */ | |
57 | unsigned char tckmax; /* 43 Max device cycle time tCKmax */ | |
58 | unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ | |
59 | unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ | |
60 | unsigned char res_46; /* 46 Reserved */ | |
61 | unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */ | |
62 | unsigned char res_48_61[14]; /* 48-61 Reserved */ | |
63 | unsigned char spd_rev; /* 62 SPD Data Revision Code */ | |
64 | unsigned char cksum; /* 63 Checksum for bytes 0-62 */ | |
65 | unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */ | |
66 | unsigned char mloc; /* 72 Manufacturing Location */ | |
67 | unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ | |
68 | unsigned char rev[2]; /* 91 Revision Code */ | |
69 | unsigned char mdate[2]; /* 93 Manufacturing Date */ | |
70 | unsigned char sernum[4]; /* 95 Assembly Serial Number */ | |
71 | unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ | |
72 | ||
73 | } ddr1_spd_eeprom_t; | |
74 | ||
75 | /* | |
76 | * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM", | |
77 | * SPD Revision 1.2 | |
78 | */ | |
79 | typedef struct ddr2_spd_eeprom_s { | |
80 | unsigned char info_size; /* 0 # bytes written into serial memory */ | |
81 | unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ | |
82 | unsigned char mem_type; /* 2 Fundamental memory type */ | |
83 | unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ | |
84 | unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ | |
85 | unsigned char mod_ranks; /* 5 Number of DIMM Ranks */ | |
86 | unsigned char dataw; /* 6 Module Data Width */ | |
87 | unsigned char res_7; /* 7 Reserved */ | |
88 | unsigned char voltage; /* 8 Voltage intf std of this assembly */ | |
89 | unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ | |
90 | unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ | |
91 | unsigned char config; /* 11 DIMM Configuration type */ | |
92 | unsigned char refresh; /* 12 Refresh Rate/Type */ | |
93 | unsigned char primw; /* 13 Primary SDRAM Width */ | |
94 | unsigned char ecw; /* 14 Error Checking SDRAM width */ | |
95 | unsigned char res_15; /* 15 Reserved */ | |
96 | unsigned char burstl; /* 16 Burst Lengths Supported */ | |
97 | unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ | |
98 | unsigned char cas_lat; /* 18 CAS# Latencies Supported */ | |
99 | unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */ | |
100 | unsigned char dimm_type; /* 20 DIMM type information */ | |
101 | unsigned char mod_attr; /* 21 SDRAM Module Attributes */ | |
102 | unsigned char dev_attr; /* 22 SDRAM Device Attributes */ | |
103 | unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */ | |
104 | unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */ | |
105 | unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */ | |
106 | unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */ | |
107 | unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ | |
108 | unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ | |
109 | unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ | |
110 | unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ | |
111 | unsigned char rank_dens; /* 31 Density of each rank on module */ | |
112 | unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */ | |
113 | unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */ | |
114 | unsigned char data_setup; /* 34 Data Input Setup Time | |
93e14596 | 115 | Before Strobe (tDS) */ |
0f2cbe3f | 116 | unsigned char data_hold; /* 35 Data Input Hold Time |
93e14596 | 117 | After Strobe (tDH) */ |
0f2cbe3f JY |
118 | unsigned char twr; /* 36 Write Recovery time tWR */ |
119 | unsigned char twtr; /* 37 Int write to read delay tWTR */ | |
120 | unsigned char trtp; /* 38 Int read to precharge delay tRTP */ | |
121 | unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ | |
122 | unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ | |
123 | unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ | |
124 | unsigned char trfc; /* 42 Min Auto to Active period tRFC */ | |
125 | unsigned char tckmax; /* 43 Max device cycle time tCKmax */ | |
126 | unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ | |
127 | unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ | |
128 | unsigned char pll_relock; /* 46 PLL Relock time */ | |
0dd38a35 PJ |
129 | unsigned char t_casemax; /* 47 Tcasemax */ |
130 | unsigned char psi_ta_dram; /* 48 Thermal Resistance of DRAM Package from | |
93e14596 | 131 | Top (Case) to Ambient (Psi T-A DRAM) */ |
0f2cbe3f | 132 | unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient |
93e14596 | 133 | due to Activate-Precharge/Mode Bits |
0f2cbe3f JY |
134 | (DT0/Mode Bits) */ |
135 | unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient | |
93e14596 | 136 | due to Precharge/Quiet Standby |
0f2cbe3f JY |
137 | (DT2N/DT2Q) */ |
138 | unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient | |
93e14596 | 139 | due to Precharge Power-Down (DT2P) */ |
0f2cbe3f | 140 | unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient |
93e14596 | 141 | due to Active Standby (DT3N) */ |
0f2cbe3f | 142 | unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient |
93e14596 | 143 | due to Active Power-Down with |
0f2cbe3f JY |
144 | Fast PDN Exit (DT3Pfast) */ |
145 | unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient | |
93e14596 | 146 | due to Active Power-Down with Slow |
0f2cbe3f JY |
147 | PDN Exit (DT3Pslow) */ |
148 | unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient | |
93e14596 | 149 | due to Page Open Burst Read/DT4R4W |
0f2cbe3f JY |
150 | Mode Bit (DT4R/DT4R4W Mode Bit) */ |
151 | unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient | |
93e14596 | 152 | due to Burst Refresh (DT5B) */ |
0f2cbe3f | 153 | unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient |
93e14596 | 154 | due to Bank Interleave Reads with |
0f2cbe3f | 155 | Auto-Precharge (DT7) */ |
0dd38a35 | 156 | unsigned char psi_ta_pll; /* 58 Thermal Resistance of PLL Package form |
93e14596 | 157 | Top (Case) to Ambient (Psi T-A PLL) */ |
0dd38a35 | 158 | unsigned char psi_ta_reg; /* 59 Thermal Reisitance of Register Package |
93e14596 | 159 | from Top (Case) to Ambient |
0f2cbe3f JY |
160 | (Psi T-A Register) */ |
161 | unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient | |
93e14596 | 162 | due to PLL Active (DT PLL Active) */ |
0f2cbe3f | 163 | unsigned char dtregact; /* 61 Register Case Temperature Rise from |
93e14596 | 164 | Ambient due to Register Active/Mode Bit |
0f2cbe3f JY |
165 | (DT Register Active/Mode Bit) */ |
166 | unsigned char spd_rev; /* 62 SPD Data Revision Code */ | |
167 | unsigned char cksum; /* 63 Checksum for bytes 0-62 */ | |
168 | unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */ | |
169 | unsigned char mloc; /* 72 Manufacturing Location */ | |
170 | unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ | |
171 | unsigned char rev[2]; /* 91 Revision Code */ | |
172 | unsigned char mdate[2]; /* 93 Manufacturing Date */ | |
173 | unsigned char sernum[4]; /* 95 Assembly Serial Number */ | |
174 | unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ | |
175 | ||
176 | } ddr2_spd_eeprom_t; | |
177 | ||
178 | typedef struct ddr3_spd_eeprom_s { | |
179 | /* General Section: Bytes 0-59 */ | |
180 | unsigned char info_size_crc; /* 0 # bytes written into serial memory, | |
181 | CRC coverage */ | |
182 | unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */ | |
183 | unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */ | |
184 | unsigned char module_type; /* 3 Key Byte / Module Type */ | |
185 | unsigned char density_banks; /* 4 SDRAM Density and Banks */ | |
186 | unsigned char addressing; /* 5 SDRAM Addressing */ | |
c360ceac | 187 | unsigned char module_vdd; /* 6 Module nominal voltage, VDD */ |
0f2cbe3f JY |
188 | unsigned char organization; /* 7 Module Organization */ |
189 | unsigned char bus_width; /* 8 Module Memory Bus Width */ | |
190 | unsigned char ftb_div; /* 9 Fine Timebase (FTB) | |
191 | Dividend / Divisor */ | |
192 | unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ | |
193 | unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ | |
0dd38a35 | 194 | unsigned char tck_min; /* 12 SDRAM Minimum Cycle Time */ |
0f2cbe3f JY |
195 | unsigned char res_13; /* 13 Reserved */ |
196 | unsigned char caslat_lsb; /* 14 CAS Latencies Supported, | |
197 | Least Significant Byte */ | |
198 | unsigned char caslat_msb; /* 15 CAS Latencies Supported, | |
199 | Most Significant Byte */ | |
0dd38a35 PJ |
200 | unsigned char taa_min; /* 16 Min CAS Latency Time */ |
201 | unsigned char twr_min; /* 17 Min Write REcovery Time */ | |
202 | unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */ | |
203 | unsigned char trrd_min; /* 19 Min Row Active to | |
0f2cbe3f | 204 | Row Active Delay Time */ |
0dd38a35 PJ |
205 | unsigned char trp_min; /* 20 Min Row Precharge Delay Time */ |
206 | unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */ | |
207 | unsigned char tras_min_lsb; /* 22 Min Active to Precharge | |
0f2cbe3f | 208 | Delay Time */ |
0dd38a35 | 209 | unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh |
0f2cbe3f | 210 | Delay Time, LSB */ |
0dd38a35 PJ |
211 | unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */ |
212 | unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */ | |
213 | unsigned char twtr_min; /* 26 Min Internal Write to | |
0f2cbe3f | 214 | Read Command Delay Time */ |
0dd38a35 | 215 | unsigned char trtp_min; /* 27 Min Internal Read to Precharge |
0f2cbe3f | 216 | Command Delay Time */ |
0dd38a35 PJ |
217 | unsigned char tfaw_msb; /* 28 Upper Nibble for tFAW */ |
218 | unsigned char tfaw_min; /* 29 Min Four Activate Window | |
0f2cbe3f JY |
219 | Delay Time*/ |
220 | unsigned char opt_features; /* 30 SDRAM Optional Features */ | |
221 | unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ | |
c49290cd YS |
222 | unsigned char therm_sensor; /* 32 Module Thermal Sensor */ |
223 | unsigned char device_type; /* 33 SDRAM device type */ | |
0dd38a35 PJ |
224 | int8_t fine_tck_min; /* 34 Fine offset for tCKmin */ |
225 | int8_t fine_taa_min; /* 35 Fine offset for tAAmin */ | |
226 | int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */ | |
227 | int8_t fine_trp_min; /* 37 Fine offset for tRPmin */ | |
228 | int8_t fine_trc_min; /* 38 Fine offset for tRCmin */ | |
73b5396b | 229 | unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */ |
0f2cbe3f JY |
230 | |
231 | /* Module-Specific Section: Bytes 60-116 */ | |
232 | union { | |
233 | struct { | |
234 | /* 60 (Unbuffered) Module Nominal Height */ | |
235 | unsigned char mod_height; | |
236 | /* 61 (Unbuffered) Module Maximum Thickness */ | |
237 | unsigned char mod_thickness; | |
238 | /* 62 (Unbuffered) Reference Raw Card Used */ | |
239 | unsigned char ref_raw_card; | |
240 | /* 63 (Unbuffered) Address Mapping from | |
241 | Edge Connector to DRAM */ | |
242 | unsigned char addr_mapping; | |
243 | /* 64-116 (Unbuffered) Reserved */ | |
244 | unsigned char res_64_116[53]; | |
245 | } unbuffered; | |
246 | struct { | |
247 | /* 60 (Registered) Module Nominal Height */ | |
248 | unsigned char mod_height; | |
249 | /* 61 (Registered) Module Maximum Thickness */ | |
250 | unsigned char mod_thickness; | |
251 | /* 62 (Registered) Reference Raw Card Used */ | |
252 | unsigned char ref_raw_card; | |
9490ff48 YS |
253 | /* 63 DIMM Module Attributes */ |
254 | unsigned char modu_attr; | |
255 | /* 64 RDIMM Thermal Heat Spreader Solution */ | |
256 | unsigned char thermal; | |
257 | /* 65 Register Manufacturer ID Code, Least Significant Byte */ | |
258 | unsigned char reg_id_lo; | |
259 | /* 66 Register Manufacturer ID Code, Most Significant Byte */ | |
260 | unsigned char reg_id_hi; | |
261 | /* 67 Register Revision Number */ | |
262 | unsigned char reg_rev; | |
263 | /* 68 Register Type */ | |
264 | unsigned char reg_type; | |
265 | /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */ | |
266 | unsigned char rcw[8]; | |
0f2cbe3f JY |
267 | } registered; |
268 | unsigned char uc[57]; /* 60-116 Module-Specific Section */ | |
269 | } mod_section; | |
270 | ||
271 | /* Unique Module ID: Bytes 117-125 */ | |
272 | unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */ | |
273 | unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */ | |
274 | unsigned char mloc; /* 119 Mfg Location */ | |
275 | unsigned char mdate[2]; /* 120-121 Mfg Date */ | |
276 | unsigned char sernum[4]; /* 122-125 Module Serial Number */ | |
277 | ||
278 | /* CRC: Bytes 126-127 */ | |
279 | unsigned char crc[2]; /* 126-127 SPD CRC */ | |
280 | ||
281 | /* Other Manufacturer Fields and User Space: Bytes 128-255 */ | |
282 | unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */ | |
283 | unsigned char mrev[2]; /* 146-147 Module Revision Code */ | |
284 | ||
285 | unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */ | |
286 | unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */ | |
287 | ||
288 | unsigned char msd[26]; /* 150-175 Mfg's Specific Data */ | |
289 | unsigned char cust[80]; /* 176-255 Open for Customer Use */ | |
290 | ||
291 | } ddr3_spd_eeprom_t; | |
292 | ||
34e026f9 YS |
293 | /* From JEEC Standard No. 21-C release 23A */ |
294 | struct ddr4_spd_eeprom_s { | |
295 | /* General Section: Bytes 0-127 */ | |
296 | uint8_t info_size_crc; /* 0 # bytes */ | |
297 | uint8_t spd_rev; /* 1 Total # bytes of SPD */ | |
298 | uint8_t mem_type; /* 2 Key Byte / mem type */ | |
299 | uint8_t module_type; /* 3 Key Byte / Module Type */ | |
300 | uint8_t density_banks; /* 4 Density and Banks */ | |
301 | uint8_t addressing; /* 5 Addressing */ | |
302 | uint8_t package_type; /* 6 Package type */ | |
303 | uint8_t opt_feature; /* 7 Optional features */ | |
304 | uint8_t thermal_ref; /* 8 Thermal and refresh */ | |
305 | uint8_t oth_opt_features; /* 9 Other optional features */ | |
306 | uint8_t res_10; /* 10 Reserved */ | |
307 | uint8_t module_vdd; /* 11 Module nominal voltage */ | |
308 | uint8_t organization; /* 12 Module Organization */ | |
309 | uint8_t bus_width; /* 13 Module Memory Bus Width */ | |
310 | uint8_t therm_sensor; /* 14 Module Thermal Sensor */ | |
311 | uint8_t ext_type; /* 15 Extended module type */ | |
312 | uint8_t res_16; | |
313 | uint8_t timebases; /* 17 MTb and FTB */ | |
314 | uint8_t tck_min; /* 18 tCKAVGmin */ | |
315 | uint8_t tck_max; /* 19 TCKAVGmax */ | |
316 | uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */ | |
317 | uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */ | |
318 | uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */ | |
319 | uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */ | |
320 | uint8_t taa_min; /* 24 Min CAS Latency Time */ | |
321 | uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */ | |
322 | uint8_t trp_min; /* 26 Min Row Precharge Delay Time */ | |
323 | uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */ | |
324 | uint8_t tras_min_lsb; /* 28 tRASmin, lsb */ | |
325 | uint8_t trc_min_lsb; /* 29 tRCmin, lsb */ | |
326 | uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */ | |
327 | uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */ | |
328 | uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */ | |
329 | uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */ | |
330 | uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */ | |
331 | uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */ | |
332 | uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */ | |
333 | uint8_t tfaw_min; /* 37 tFAW, lsb */ | |
334 | uint8_t trrds_min; /* 38 tRRD_Smin, MTB */ | |
335 | uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */ | |
336 | uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */ | |
337 | uint8_t res_41[60-41]; /* 41 Rserved */ | |
338 | uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ | |
339 | uint8_t res_78[117-78]; /* 78~116, Reserved */ | |
340 | int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */ | |
341 | int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */ | |
342 | int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */ | |
343 | int8_t fine_trc_min; /* 120 Fine offset for tRCmin */ | |
344 | int8_t fine_trp_min; /* 121 Fine offset for tRPmin */ | |
345 | int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */ | |
346 | int8_t fine_taa_min; /* 123 Fine offset for tAAmin */ | |
347 | int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */ | |
348 | int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */ | |
349 | /* CRC: Bytes 126-127 */ | |
350 | uint8_t crc[2]; /* 126-127 SPD CRC */ | |
351 | ||
352 | /* Module-Specific Section: Bytes 128-255 */ | |
353 | union { | |
354 | struct { | |
355 | /* 128 (Unbuffered) Module Nominal Height */ | |
356 | uint8_t mod_height; | |
357 | /* 129 (Unbuffered) Module Maximum Thickness */ | |
358 | uint8_t mod_thickness; | |
359 | /* 130 (Unbuffered) Reference Raw Card Used */ | |
360 | uint8_t ref_raw_card; | |
361 | /* 131 (Unbuffered) Address Mapping from | |
362 | Edge Connector to DRAM */ | |
363 | uint8_t addr_mapping; | |
364 | /* 132~253 (Unbuffered) Reserved */ | |
365 | uint8_t res_132[254-132]; | |
366 | /* 254~255 CRC */ | |
367 | uint8_t crc[2]; | |
368 | } unbuffered; | |
369 | struct { | |
370 | /* 128 (Registered) Module Nominal Height */ | |
371 | uint8_t mod_height; | |
372 | /* 129 (Registered) Module Maximum Thickness */ | |
373 | uint8_t mod_thickness; | |
374 | /* 130 (Registered) Reference Raw Card Used */ | |
375 | uint8_t ref_raw_card; | |
376 | /* 131 DIMM Module Attributes */ | |
377 | uint8_t modu_attr; | |
378 | /* 132 RDIMM Thermal Heat Spreader Solution */ | |
379 | uint8_t thermal; | |
380 | /* 133 Register Manufacturer ID Code, LSB */ | |
381 | uint8_t reg_id_lo; | |
382 | /* 134 Register Manufacturer ID Code, MSB */ | |
383 | uint8_t reg_id_hi; | |
384 | /* 135 Register Revision Number */ | |
385 | uint8_t reg_rev; | |
386 | /* 136 Address mapping from register to DRAM */ | |
387 | uint8_t reg_map; | |
388 | /* 137~253 Reserved */ | |
389 | uint8_t res_137[254-137]; | |
390 | /* 254~255 CRC */ | |
391 | uint8_t crc[2]; | |
392 | } registered; | |
393 | struct { | |
394 | /* 128 (Loadreduced) Module Nominal Height */ | |
395 | uint8_t mod_height; | |
396 | /* 129 (Loadreduced) Module Maximum Thickness */ | |
397 | uint8_t mod_thickness; | |
398 | /* 130 (Loadreduced) Reference Raw Card Used */ | |
399 | uint8_t ref_raw_card; | |
400 | /* 131 DIMM Module Attributes */ | |
401 | uint8_t modu_attr; | |
402 | /* 132 RDIMM Thermal Heat Spreader Solution */ | |
403 | uint8_t thermal; | |
404 | /* 133 Register Manufacturer ID Code, LSB */ | |
405 | uint8_t reg_id_lo; | |
406 | /* 134 Register Manufacturer ID Code, MSB */ | |
407 | uint8_t reg_id_hi; | |
408 | /* 135 Register Revision Number */ | |
409 | uint8_t reg_rev; | |
410 | /* 136 Address mapping from register to DRAM */ | |
411 | uint8_t reg_map; | |
412 | /* 137 Register Output Drive Strength for CMD/Add*/ | |
413 | uint8_t reg_drv; | |
414 | /* 138 Register Output Drive Strength for CK */ | |
415 | uint8_t reg_drv_ck; | |
416 | /* 139 Data Buffer Revision Number */ | |
417 | uint8_t data_buf_rev; | |
418 | /* 140 DRAM VrefDQ for Package Rank 0 */ | |
419 | uint8_t vrefqe_r0; | |
420 | /* 141 DRAM VrefDQ for Package Rank 1 */ | |
421 | uint8_t vrefqe_r1; | |
422 | /* 142 DRAM VrefDQ for Package Rank 2 */ | |
423 | uint8_t vrefqe_r2; | |
424 | /* 143 DRAM VrefDQ for Package Rank 3 */ | |
425 | uint8_t vrefqe_r3; | |
426 | /* 144 Data Buffer VrefDQ for DRAM Interface */ | |
427 | uint8_t data_intf; | |
428 | /* | |
429 | * 145 Data Buffer MDQ Drive Strength and RTT | |
430 | * for data rate <= 1866 | |
431 | */ | |
432 | uint8_t data_drv_1866; | |
433 | /* | |
434 | * 146 Data Buffer MDQ Drive Strength and RTT | |
435 | * for 1866 < data rate <= 2400 | |
436 | */ | |
437 | uint8_t data_drv_2400; | |
438 | /* | |
439 | * 147 Data Buffer MDQ Drive Strength and RTT | |
440 | * for 2400 < data rate <= 3200 | |
441 | */ | |
442 | uint8_t data_drv_3200; | |
443 | /* 148 DRAM Drive Strength */ | |
444 | uint8_t dram_drv; | |
445 | /* | |
446 | * 149 DRAM ODT (RTT_WR, RTT_NOM) | |
447 | * for data rate <= 1866 | |
448 | */ | |
449 | uint8_t dram_odt_1866; | |
450 | /* | |
451 | * 150 DRAM ODT (RTT_WR, RTT_NOM) | |
452 | * for 1866 < data rate <= 2400 | |
453 | */ | |
454 | uint8_t dram_odt_2400; | |
455 | /* | |
456 | * 151 DRAM ODT (RTT_WR, RTT_NOM) | |
457 | * for 2400 < data rate <= 3200 | |
458 | */ | |
459 | uint8_t dram_odt_3200; | |
460 | /* | |
461 | * 152 DRAM ODT (RTT_PARK) | |
462 | * for data rate <= 1866 | |
463 | */ | |
464 | uint8_t dram_odt_park_1866; | |
465 | /* | |
466 | * 153 DRAM ODT (RTT_PARK) | |
467 | * for 1866 < data rate <= 2400 | |
468 | */ | |
469 | uint8_t dram_odt_park_2400; | |
470 | /* | |
471 | * 154 DRAM ODT (RTT_PARK) | |
472 | * for 2400 < data rate <= 3200 | |
473 | */ | |
474 | uint8_t dram_odt_park_3200; | |
475 | uint8_t res_155[254-155]; /* Reserved */ | |
476 | /* 254~255 CRC */ | |
477 | uint8_t crc[2]; | |
478 | } loadreduced; | |
479 | uint8_t uc[128]; /* 128-255 Module-Specific Section */ | |
480 | } mod_section; | |
481 | ||
482 | uint8_t res_256[320-256]; /* 256~319 Reserved */ | |
483 | ||
484 | /* Module supplier's data: Byte 320~383 */ | |
485 | uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */ | |
486 | uint8_t mmid_msb; /* 321 Module MfgID Code MSB */ | |
487 | uint8_t mloc; /* 322 Mfg Location */ | |
488 | uint8_t mdate[2]; /* 323~324 Mfg Date */ | |
489 | uint8_t sernum[4]; /* 325~328 Module Serial Number */ | |
490 | uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */ | |
491 | uint8_t mrev; /* 349 Module Revision Code */ | |
492 | uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */ | |
493 | uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */ | |
494 | uint8_t stepping; /* 352 DRAM stepping */ | |
495 | uint8_t msd[29]; /* 353~381 Mfg's Specific Data */ | |
496 | uint8_t res_382[2]; /* 382~383 Reserved */ | |
497 | ||
498 | uint8_t user[512-384]; /* 384~511 End User Programmable */ | |
499 | }; | |
500 | ||
0f2cbe3f JY |
501 | extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); |
502 | extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); | |
503 | extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); | |
504 | extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); | |
c360ceac | 505 | extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); |
34e026f9 | 506 | unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd); |
0f2cbe3f JY |
507 | |
508 | /* | |
509 | * Byte 2 Fundamental Memory Types. | |
510 | */ | |
511 | #define SPD_MEMTYPE_FPM (0x01) | |
512 | #define SPD_MEMTYPE_EDO (0x02) | |
513 | #define SPD_MEMTYPE_PIPE_NIBBLE (0x03) | |
514 | #define SPD_MEMTYPE_SDRAM (0x04) | |
515 | #define SPD_MEMTYPE_ROM (0x05) | |
516 | #define SPD_MEMTYPE_SGRAM (0x06) | |
517 | #define SPD_MEMTYPE_DDR (0x07) | |
518 | #define SPD_MEMTYPE_DDR2 (0x08) | |
519 | #define SPD_MEMTYPE_DDR2_FBDIMM (0x09) | |
520 | #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) | |
521 | #define SPD_MEMTYPE_DDR3 (0x0B) | |
34e026f9 | 522 | #define SPD_MEMTYPE_DDR4 (0x0C) |
0f2cbe3f | 523 | |
c7fd27cc KM |
524 | /* DIMM Type for DDR2 SPD (according to v1.3) */ |
525 | #define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) | |
526 | #define DDR2_SPD_DIMMTYPE_RDIMM (0x01) | |
527 | #define DDR2_SPD_DIMMTYPE_UDIMM (0x02) | |
528 | #define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04) | |
529 | #define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06) | |
530 | #define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07) | |
531 | #define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08) | |
532 | #define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10) | |
533 | #define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20) | |
534 | ||
535 | /* Byte 3 Key Byte / Module Type for DDR3 SPD */ | |
536 | #define DDR3_SPD_MODULETYPE_MASK (0x0f) | |
537 | #define DDR3_SPD_MODULETYPE_RDIMM (0x01) | |
538 | #define DDR3_SPD_MODULETYPE_UDIMM (0x02) | |
539 | #define DDR3_SPD_MODULETYPE_SO_DIMM (0x03) | |
540 | #define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) | |
541 | #define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) | |
542 | #define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) | |
2f3a71f2 IS |
543 | #define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07) |
544 | #define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08) | |
545 | #define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09) | |
546 | #define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A) | |
547 | #define DDR3_SPD_MODULETYPE_LRDIMM (0x0B) | |
548 | #define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C) | |
549 | #define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D) | |
c360ceac | 550 | |
34e026f9 YS |
551 | /* DIMM Type for DDR4 SPD */ |
552 | #define DDR4_SPD_MODULETYPE_MASK (0x0f) | |
553 | #define DDR4_SPD_MODULETYPE_EXT (0x00) | |
554 | #define DDR4_SPD_MODULETYPE_RDIMM (0x01) | |
555 | #define DDR4_SPD_MODULETYPE_UDIMM (0x02) | |
556 | #define DDR4_SPD_MODULETYPE_SO_DIMM (0x03) | |
557 | #define DDR4_SPD_MODULETYPE_LRDIMM (0x04) | |
558 | #define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05) | |
559 | #define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06) | |
560 | #define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08) | |
561 | #define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09) | |
562 | #define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C) | |
563 | #define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D) | |
564 | ||
0f2cbe3f | 565 | #endif /* _DDR_SPD_H_ */ |