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c74b2108 SK |
1 | /* |
2 | * DP83848 ethernet Physical layer | |
3 | * | |
4 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
5 | * | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
c74b2108 SK |
8 | */ |
9 | ||
10 | ||
11 | /* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ | |
12 | ||
13 | #define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ | |
14 | #define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ | |
15 | #define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ | |
16 | #define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ | |
17 | #define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ | |
18 | #define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ | |
19 | #define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ | |
20 | #define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ | |
21 | #define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ | |
22 | #define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ | |
23 | ||
24 | /*--Bit definitions: DP83848_CTL_REG */ | |
25 | #define DP83848_RESET (1 << 15) /* 1= S/W Reset */ | |
26 | #define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ | |
27 | #define DP83848_SPEED_SELECT (1 << 13) | |
28 | #define DP83848_AUTONEG (1 << 12) | |
29 | #define DP83848_POWER_DOWN (1 << 11) | |
30 | #define DP83848_ISOLATE (1 << 10) | |
31 | #define DP83848_RESTART_AUTONEG (1 << 9) | |
32 | #define DP83848_DUPLEX_MODE (1 << 8) | |
33 | #define DP83848_COLLISION_TEST (1 << 7) | |
34 | ||
35 | /*--Bit definitions: DP83848_STAT_REG */ | |
36 | #define DP83848_100BASE_T4 (1 << 15) | |
37 | #define DP83848_100BASE_TX_FD (1 << 14) | |
38 | #define DP83848_100BASE_TX_HD (1 << 13) | |
39 | #define DP83848_10BASE_T_FD (1 << 12) | |
40 | #define DP83848_10BASE_T_HD (1 << 11) | |
41 | #define DP83848_MF_PREAMB_SUPPR (1 << 6) | |
42 | #define DP83848_AUTONEG_COMP (1 << 5) | |
43 | #define DP83848_RMT_FAULT (1 << 4) | |
44 | #define DP83848_AUTONEG_ABILITY (1 << 3) | |
45 | #define DP83848_LINK_STATUS (1 << 2) | |
46 | #define DP83848_JABBER_DETECT (1 << 1) | |
47 | #define DP83848_EXTEND_CAPAB (1 << 0) | |
48 | ||
49 | /*--definitions: DP83848_PHYID1 */ | |
50 | #define DP83848_PHYID1_OUI 0x2000 | |
51 | #define DP83848_PHYID2_OUI 0x5c90 | |
52 | ||
53 | /*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ | |
54 | #define DP83848_NP (1 << 15) | |
55 | #define DP83848_ACK (1 << 14) | |
56 | #define DP83848_RF (1 << 13) | |
57 | #define DP83848_PAUSE (1 << 10) | |
58 | #define DP83848_T4 (1 << 9) | |
59 | #define DP83848_TX_FDX (1 << 8) | |
60 | #define DP83848_TX_HDX (1 << 7) | |
61 | #define DP83848_10_FDX (1 << 6) | |
62 | #define DP83848_10_HDX (1 << 5) | |
63 | #define DP83848_AN_IEEE_802_3 0x0001 | |
64 | ||
65 | /*--Bit definitions: DP83848_ANER */ | |
66 | #define DP83848_PDF (1 << 4) | |
67 | #define DP83848_LP_NP_ABLE (1 << 3) | |
68 | #define DP83848_NP_ABLE (1 << 2) | |
69 | #define DP83848_PAGE_RX (1 << 1) | |
70 | #define DP83848_LP_AN_ABLE (1 << 0) | |
71 | ||
72 | /*--Bit definitions: DP83848_PHY_STAT */ | |
73 | #define DP83848_RX_ERR_LATCH (1 << 13) | |
74 | #define DP83848_POLARITY_STAT (1 << 12) | |
75 | #define DP83848_FALSE_CAR_SENSE (1 << 11) | |
76 | #define DP83848_SIG_DETECT (1 << 10) | |
77 | #define DP83848_DESCRAM_LOCK (1 << 9) | |
78 | #define DP83848_PAGE_RCV (1 << 8) | |
79 | #define DP83848_PHY_RMT_FAULT (1 << 6) | |
80 | #define DP83848_JABBER (1 << 5) | |
81 | #define DP83848_AUTONEG_COMPLETE (1 << 4) | |
82 | #define DP83848_LOOPBACK_STAT (1 << 3) | |
83 | #define DP83848_DUPLEX (1 << 2) | |
84 | #define DP83848_SPEED (1 << 1) | |
85 | #define DP83848_LINK (1 << 0) |