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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Keith Packard | |
3 | * | |
4 | * Permission to use, copy, modify, distribute, and sell this software and its | |
5 | * documentation for any purpose is hereby granted without fee, provided that | |
6 | * the above copyright notice appear in all copies and that both that copyright | |
7 | * notice and this permission notice appear in supporting documentation, and | |
8 | * that the name of the copyright holders not be used in advertising or | |
9 | * publicity pertaining to distribution of the software without specific, | |
10 | * written prior permission. The copyright holders make no representations | |
11 | * about the suitability of this software for any purpose. It is provided "as | |
12 | * is" without express or implied warranty. | |
13 | * | |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | |
20 | * OF THIS SOFTWARE. | |
21 | */ | |
22 | ||
ab2c0672 DA |
23 | #ifndef _DRM_DP_HELPER_H_ |
24 | #define _DRM_DP_HELPER_H_ | |
a4fc5ed6 | 25 | |
1a644cd4 | 26 | #include <linux/delay.h> |
80664f75 | 27 | #include <linux/i2c.h> |
5d1b8b4a TZ |
28 | |
29 | #include <drm/display/drm_dp.h> | |
e5b92773 | 30 | #include <drm/drm_connector.h> |
9f0e7ff4 | 31 | |
7af655bc | 32 | struct drm_device; |
9e986666 | 33 | struct drm_dp_aux; |
072ed343 | 34 | struct drm_panel; |
7af655bc | 35 | |
0aec2881 | 36 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 | 37 | int lane_count); |
0aec2881 | 38 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
01916270 | 39 | int lane_count); |
0aec2881 | 40 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde | 41 | int lane); |
0aec2881 | 42 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde | 43 | int lane); |
c78b4a85 JN |
44 | u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], |
45 | int lane); | |
1ffdff13 | 46 | |
ba3078da JN |
47 | int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
48 | enum drm_dp_phy dp_phy, bool uhbr); | |
49 | int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
50 | enum drm_dp_phy dp_phy, bool uhbr); | |
51 | ||
9e986666 LP |
52 | void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, |
53 | const u8 dpcd[DP_RECEIVER_CAP_SIZE]); | |
9782f52a | 54 | void drm_dp_lttpr_link_train_clock_recovery_delay(void); |
0c4fada6 LP |
55 | void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, |
56 | const u8 dpcd[DP_RECEIVER_CAP_SIZE]); | |
57 | void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, | |
58 | const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); | |
1a644cd4 | 59 | |
0f4b5842 | 60 | int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); |
0192c25c JN |
61 | bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], |
62 | int lane_count); | |
63 | bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], | |
64 | int lane_count); | |
65 | bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); | |
66 | bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); | |
67 | bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); | |
0f4b5842 | 68 | |
3b5c662e SV |
69 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
70 | int drm_dp_bw_code_to_link_rate(u8 link_bw); | |
71 | ||
5b04aab6 JN |
72 | const char *drm_dp_phy_name(enum drm_dp_phy dp_phy); |
73 | ||
e2e4c4e1 GM |
74 | /** |
75 | * struct drm_dp_vsc_sdp - drm DP VSC SDP | |
76 | * | |
77 | * This structure represents a DP VSC SDP of drm | |
78 | * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and | |
79 | * [Table 2-117: VSC SDP Payload for DB16 through DB18] | |
80 | * | |
81 | * @sdp_type: secondary-data packet type | |
82 | * @revision: revision number | |
83 | * @length: number of valid data bytes | |
84 | * @pixelformat: pixel encoding format | |
85 | * @colorimetry: colorimetry format | |
86 | * @bpc: bit per color | |
87 | * @dynamic_range: dynamic range information | |
88 | * @content_type: CTA-861-G defines content types and expected processing by a sink device | |
89 | */ | |
90 | struct drm_dp_vsc_sdp { | |
91 | unsigned char sdp_type; | |
92 | unsigned char revision; | |
93 | unsigned char length; | |
94 | enum dp_pixelformat pixelformat; | |
95 | enum dp_colorimetry colorimetry; | |
96 | int bpc; | |
97 | enum dp_dynamic_range dynamic_range; | |
98 | enum dp_content_type content_type; | |
99 | }; | |
100 | ||
2e61504f | 101 | void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); |
2ba6221c | 102 | |
6608804b VS |
103 | int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); |
104 | ||
3b5c662e | 105 | static inline int |
0aec2881 | 106 | drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
3b5c662e SV |
107 | { |
108 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); | |
109 | } | |
397fe157 SV |
110 | |
111 | static inline u8 | |
0aec2881 | 112 | drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
397fe157 SV |
113 | { |
114 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; | |
115 | } | |
116 | ||
58704e6a JN |
117 | static inline bool |
118 | drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
119 | { | |
120 | return dpcd[DP_DPCD_REV] >= 0x11 && | |
121 | (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); | |
122 | } | |
123 | ||
8cda78b1 TR |
124 | static inline bool |
125 | drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
126 | { | |
127 | return dpcd[DP_DPCD_REV] >= 0x11 && | |
128 | (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); | |
129 | } | |
130 | ||
7cc53cf0 JN |
131 | static inline bool |
132 | drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
133 | { | |
134 | return dpcd[DP_DPCD_REV] >= 0x12 && | |
135 | dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; | |
136 | } | |
137 | ||
447a39f4 SB |
138 | static inline bool |
139 | drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
140 | { | |
141 | return dpcd[DP_DPCD_REV] >= 0x11 || | |
142 | dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; | |
143 | } | |
144 | ||
41d2f5fa MN |
145 | static inline bool |
146 | drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
147 | { | |
148 | return dpcd[DP_DPCD_REV] >= 0x14 && | |
149 | dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; | |
150 | } | |
151 | ||
152 | static inline u8 | |
153 | drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
154 | { | |
155 | return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : | |
156 | DP_TRAINING_PATTERN_MASK; | |
157 | } | |
158 | ||
c726ad01 ID |
159 | static inline bool |
160 | drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
161 | { | |
162 | return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; | |
163 | } | |
164 | ||
05756500 | 165 | /* DP/eDP DSC support */ |
0c2287c9 | 166 | u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); |
05756500 MN |
167 | u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], |
168 | bool is_edp); | |
169 | u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); | |
4d4101c8 MN |
170 | int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], |
171 | u8 dsc_bpc[3]); | |
05756500 MN |
172 | |
173 | static inline bool | |
174 | drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) | |
175 | { | |
176 | return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & | |
177 | DP_DSC_DECOMPRESSION_IS_SUPPORTED; | |
178 | } | |
179 | ||
180 | static inline u16 | |
181 | drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) | |
182 | { | |
183 | return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | | |
13525645 JN |
184 | ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & |
185 | DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); | |
05756500 MN |
186 | } |
187 | ||
188 | static inline u32 | |
189 | drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) | |
190 | { | |
191 | /* Max Slicewidth = Number of Pixels * 320 */ | |
192 | return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * | |
193 | DP_DSC_SLICE_WIDTH_MULTIPLIER; | |
194 | } | |
195 | ||
a389789c AN |
196 | /** |
197 | * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format | |
198 | * @dsc_dpcd : DSC-capability DPCDs of the sink | |
199 | * @output_format: output_format which is to be checked | |
200 | * | |
201 | * Returns true if the sink supports DSC with the given output_format, false otherwise. | |
202 | */ | |
203 | static inline bool | |
204 | drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) | |
205 | { | |
206 | return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; | |
207 | } | |
208 | ||
857d8283 AS |
209 | /* Forward Error Correction Support on DP 1.4 */ |
210 | static inline bool | |
211 | drm_dp_sink_supports_fec(const u8 fec_capable) | |
212 | { | |
213 | return fec_capable & DP_FEC_CAPABLE; | |
214 | } | |
215 | ||
99c830b8 TR |
216 | static inline bool |
217 | drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
218 | { | |
219 | return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; | |
220 | } | |
221 | ||
7624629d TR |
222 | static inline bool |
223 | drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
224 | { | |
225 | return dpcd[DP_EDP_CONFIGURATION_CAP] & | |
226 | DP_ALTERNATE_SCRAMBLER_RESET_CAP; | |
227 | } | |
228 | ||
24cfbec9 MN |
229 | /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ |
230 | static inline bool | |
231 | drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) | |
232 | { | |
233 | return dpcd[DP_DOWN_STREAM_PORT_COUNT] & | |
234 | DP_MSA_TIMING_PAR_IGNORED; | |
235 | } | |
236 | ||
867cf9cd LP |
237 | /** |
238 | * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support | |
239 | * @edp_dpcd: The DPCD to check | |
240 | * | |
241 | * Note that currently this function will return %false for panels which support various DPCD | |
242 | * backlight features but which require the brightness be set through PWM, and don't support setting | |
f58a4353 | 243 | * the brightness level via the DPCD. |
867cf9cd LP |
244 | * |
245 | * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false | |
246 | * otherwise | |
247 | */ | |
248 | static inline bool | |
249 | drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) | |
250 | { | |
f58a4353 | 251 | return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); |
867cf9cd LP |
252 | } |
253 | ||
d389989e ID |
254 | /** |
255 | * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR | |
256 | * @link_rate: link rate in 10kbits/s units | |
257 | * | |
258 | * Determine if the provided link rate is an UHBR rate. | |
259 | * | |
260 | * Returns: %True if @link_rate is an UHBR rate. | |
261 | */ | |
262 | static inline bool drm_dp_is_uhbr_rate(int link_rate) | |
263 | { | |
264 | return link_rate >= 1000000; | |
265 | } | |
266 | ||
c197db75 TR |
267 | /* |
268 | * DisplayPort AUX channel | |
269 | */ | |
270 | ||
271 | /** | |
272 | * struct drm_dp_aux_msg - DisplayPort AUX channel transaction | |
273 | * @address: address of the (first) register to access | |
274 | * @request: contains the type of transaction (see DP_AUX_* macros) | |
275 | * @reply: upon completion, contains the reply type of the transaction | |
276 | * @buffer: pointer to a transmission or reception buffer | |
277 | * @size: size of @buffer | |
278 | */ | |
279 | struct drm_dp_aux_msg { | |
280 | unsigned int address; | |
281 | u8 request; | |
282 | u8 reply; | |
283 | void *buffer; | |
284 | size_t size; | |
285 | }; | |
286 | ||
2c6d1fff | 287 | struct cec_adapter; |
ae85b0df | 288 | struct drm_connector; |
e2272bfb | 289 | struct drm_edid; |
2c6d1fff HV |
290 | |
291 | /** | |
292 | * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX | |
293 | * @lock: mutex protecting this struct | |
294 | * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. | |
ae85b0df | 295 | * @connector: the connector this CEC adapter is associated with |
2c6d1fff HV |
296 | * @unregister_work: unregister the CEC adapter |
297 | */ | |
298 | struct drm_dp_aux_cec { | |
299 | struct mutex lock; | |
300 | struct cec_adapter *adap; | |
ae85b0df | 301 | struct drm_connector *connector; |
2c6d1fff HV |
302 | struct delayed_work unregister_work; |
303 | }; | |
304 | ||
c197db75 TR |
305 | /** |
306 | * struct drm_dp_aux - DisplayPort AUX channel | |
88759686 TR |
307 | * |
308 | * An AUX channel can also be used to transport I2C messages to a sink. A | |
45d96999 LP |
309 | * typical application of that is to access an EDID that's present in the sink |
310 | * device. The @transfer() function can also be used to execute such | |
311 | * transactions. The drm_dp_aux_register() function registers an I2C adapter | |
312 | * that can be passed to drm_probe_ddc(). Upon removal, drivers should call | |
313 | * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long | |
314 | * transfers by default; if a partial response is received, the adapter will | |
315 | * drop down to the size given by the partial response for this transaction | |
316 | * only. | |
c197db75 TR |
317 | */ |
318 | struct drm_dp_aux { | |
14407d3a MR |
319 | /** |
320 | * @name: user-visible name of this AUX channel and the | |
321 | * I2C-over-AUX adapter. | |
322 | * | |
323 | * It's also used to specify the name of the I2C adapter. If set | |
324 | * to %NULL, dev_name() of @dev will be used. | |
325 | */ | |
9dc40560 | 326 | const char *name; |
14407d3a MR |
327 | |
328 | /** | |
329 | * @ddc: I2C adapter that can be used for I2C-over-AUX | |
330 | * communication | |
331 | */ | |
88759686 | 332 | struct i2c_adapter ddc; |
14407d3a MR |
333 | |
334 | /** | |
335 | * @dev: pointer to struct device that is the parent for this | |
336 | * AUX channel. | |
337 | */ | |
c197db75 | 338 | struct device *dev; |
14407d3a MR |
339 | |
340 | /** | |
341 | * @drm_dev: pointer to the &drm_device that owns this AUX channel. | |
342 | * Beware, this may be %NULL before drm_dp_aux_register() has been | |
343 | * called. | |
344 | * | |
345 | * It should be set to the &drm_device that will be using this AUX | |
346 | * channel as early as possible. For many graphics drivers this should | |
347 | * happen before drm_dp_aux_init(), however it's perfectly fine to set | |
348 | * this field later so long as it's assigned before calling | |
349 | * drm_dp_aux_register(). | |
350 | */ | |
6cba3fe4 | 351 | struct drm_device *drm_dev; |
14407d3a MR |
352 | |
353 | /** | |
354 | * @crtc: backpointer to the crtc that is currently using this | |
355 | * AUX channel | |
356 | */ | |
4bb310fd | 357 | struct drm_crtc *crtc; |
14407d3a MR |
358 | |
359 | /** | |
360 | * @hw_mutex: internal mutex used for locking transfers. | |
c48935ab MR |
361 | * |
362 | * Note that if the underlying hardware is shared among multiple | |
363 | * channels, the driver needs to do additional locking to | |
364 | * prevent concurrent access. | |
14407d3a | 365 | */ |
4f71d0cb | 366 | struct mutex hw_mutex; |
14407d3a MR |
367 | |
368 | /** | |
369 | * @crc_work: worker that captures CRCs for each frame | |
370 | */ | |
79c1da7c | 371 | struct work_struct crc_work; |
14407d3a MR |
372 | |
373 | /** | |
374 | * @crc_count: counter of captured frame CRCs | |
375 | */ | |
79c1da7c | 376 | u8 crc_count; |
14407d3a MR |
377 | |
378 | /** | |
379 | * @transfer: transfers a message representing a single AUX | |
380 | * transaction. | |
381 | * | |
382 | * This is a hardware-specific implementation of how | |
383 | * transactions are executed that the drivers must provide. | |
384 | * | |
385 | * A pointer to a &drm_dp_aux_msg structure describing the | |
386 | * transaction is passed into this function. Upon success, the | |
387 | * implementation should return the number of payload bytes that | |
388 | * were transferred, or a negative error-code on failure. | |
389 | * | |
390 | * Helpers will propagate these errors, with the exception of | |
391 | * the %-EBUSY error, which causes a transaction to be retried. | |
392 | * On a short, helpers will return %-EPROTO to make it simpler | |
393 | * to check for failure. | |
394 | * | |
395 | * The @transfer() function must only modify the reply field of | |
396 | * the &drm_dp_aux_msg structure. The retry logic and i2c | |
397 | * helpers assume this is the case. | |
bacbab58 MR |
398 | * |
399 | * Also note that this callback can be called no matter the | |
69ef4a19 DA |
400 | * state @dev is in and also no matter what state the panel is |
401 | * in. It's expected: | |
7d188c52 | 402 | * |
69ef4a19 DA |
403 | * - If the @dev providing the AUX bus is currently unpowered then |
404 | * it will power itself up for the transfer. | |
7d188c52 | 405 | * |
69ef4a19 DA |
406 | * - If we're on eDP (using a drm_panel) and the panel is not in a |
407 | * state where it can respond (it's not powered or it's in a | |
408 | * low power state) then this function may return an error, but | |
409 | * not crash. It's up to the caller of this code to make sure that | |
410 | * the panel is powered on if getting an error back is not OK. If a | |
411 | * drm_panel driver is initiating a DP AUX transfer it may power | |
412 | * itself up however it wants. All other code should ensure that | |
413 | * the pre_enable() bridge chain (which eventually calls the | |
414 | * drm_panel prepare function) has powered the panel. | |
14407d3a | 415 | */ |
c197db75 TR |
416 | ssize_t (*transfer)(struct drm_dp_aux *aux, |
417 | struct drm_dp_aux_msg *msg); | |
14407d3a | 418 | |
841d742f DA |
419 | /** |
420 | * @wait_hpd_asserted: wait for HPD to be asserted | |
421 | * | |
422 | * This is mainly useful for eDP panels drivers to wait for an eDP | |
423 | * panel to finish powering on. This is an optional function. | |
424 | * | |
425 | * This function will efficiently wait for the HPD signal to be | |
426 | * asserted. The `wait_us` parameter that is passed in says that we | |
427 | * know that the HPD signal is expected to be asserted within `wait_us` | |
428 | * microseconds. This function could wait for longer than `wait_us` if | |
429 | * the logic in the DP controller has a long debouncing time. The | |
430 | * important thing is that if this function returns success that the | |
431 | * DP controller is ready to send AUX transactions. | |
432 | * | |
433 | * This function returns 0 if HPD was asserted or -ETIMEDOUT if time | |
434 | * expired and HPD wasn't asserted. This function should not print | |
435 | * timeout errors to the log. | |
436 | * | |
437 | * The semantics of this function are designed to match the | |
438 | * readx_poll_timeout() function. That means a `wait_us` of 0 means | |
439 | * to wait forever. Like readx_poll_timeout(), this function may sleep. | |
440 | * | |
441 | * NOTE: this function specifically reports the state of the HPD pin | |
442 | * that's associated with the DP AUX channel. This is different from | |
443 | * the HPD concept in much of the rest of DRM which is more about | |
444 | * physical presence of a display. For eDP, for instance, a display is | |
445 | * assumed always present even if the HPD pin is deasserted. | |
446 | */ | |
447 | int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); | |
448 | ||
212ae891 SV |
449 | /** |
450 | * @i2c_nack_count: Counts I2C NACKs, used for DP validation. | |
451 | */ | |
452 | unsigned i2c_nack_count; | |
453 | /** | |
454 | * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. | |
455 | */ | |
456 | unsigned i2c_defer_count; | |
2c6d1fff HV |
457 | /** |
458 | * @cec: struct containing fields used for CEC-Tunneling-over-AUX. | |
459 | */ | |
460 | struct drm_dp_aux_cec cec; | |
562836a2 VS |
461 | /** |
462 | * @is_remote: Is this AUX CH actually using sideband messaging. | |
463 | */ | |
464 | bool is_remote; | |
c197db75 TR |
465 | }; |
466 | ||
d8bb92e7 | 467 | int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); |
c197db75 TR |
468 | ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, |
469 | void *buffer, size_t size); | |
470 | ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, | |
471 | void *buffer, size_t size); | |
472 | ||
473 | /** | |
474 | * drm_dp_dpcd_readb() - read a single byte from the DPCD | |
475 | * @aux: DisplayPort AUX channel | |
476 | * @offset: address of the register to read | |
477 | * @valuep: location where the value of the register will be stored | |
478 | * | |
479 | * Returns the number of bytes transferred (1) on success, or a negative | |
480 | * error code on failure. | |
481 | */ | |
482 | static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, | |
483 | unsigned int offset, u8 *valuep) | |
484 | { | |
485 | return drm_dp_dpcd_read(aux, offset, valuep, 1); | |
486 | } | |
487 | ||
488 | /** | |
489 | * drm_dp_dpcd_writeb() - write a single byte to the DPCD | |
490 | * @aux: DisplayPort AUX channel | |
491 | * @offset: address of the register to write | |
492 | * @value: value to write to the register | |
493 | * | |
494 | * Returns the number of bytes transferred (1) on success, or a negative | |
495 | * error code on failure. | |
496 | */ | |
497 | static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, | |
498 | unsigned int offset, u8 value) | |
499 | { | |
500 | return drm_dp_dpcd_write(aux, offset, &value, 1); | |
501 | } | |
502 | ||
b9936121 LP |
503 | int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, |
504 | u8 dpcd[DP_RECEIVER_CAP_SIZE]); | |
505 | ||
8d4adc6a TR |
506 | int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, |
507 | u8 status[DP_LINK_STATUS_SIZE]); | |
508 | ||
9782f52a ID |
509 | int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, |
510 | enum drm_dp_phy dp_phy, | |
511 | u8 link_status[DP_LINK_STATUS_SIZE]); | |
512 | ||
e11f5bd8 JFZ |
513 | bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, |
514 | u8 real_edid_checksum); | |
515 | ||
3d3721cc LP |
516 | int drm_dp_read_downstream_info(struct drm_dp_aux *aux, |
517 | const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
518 | u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); | |
38784f6f VS |
519 | bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
520 | const u8 port_cap[4], u8 type); | |
521 | bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
522 | const u8 port_cap[4], | |
e2272bfb | 523 | const struct drm_edid *drm_edid); |
b770e843 VS |
524 | int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
525 | const u8 port_cap[4]); | |
6509ca05 VS |
526 | int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
527 | const u8 port_cap[4], | |
e2272bfb | 528 | const struct drm_edid *drm_edid); |
6509ca05 VS |
529 | int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
530 | const u8 port_cap[4], | |
e2272bfb | 531 | const struct drm_edid *drm_edid); |
7529d6af | 532 | int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
42f2562c | 533 | const u8 port_cap[4], |
e2272bfb | 534 | const struct drm_edid *drm_edid); |
2ef8d0f7 VS |
535 | bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
536 | const u8 port_cap[4]); | |
537 | bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
538 | const u8 port_cap[4]); | |
7af655bc VS |
539 | struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, |
540 | const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
541 | const u8 port_cap[4]); | |
266d783b | 542 | int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); |
42f2562c VS |
543 | void drm_dp_downstream_debug(struct seq_file *m, |
544 | const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
545 | const u8 port_cap[4], | |
e2272bfb | 546 | const struct drm_edid *drm_edid, |
42f2562c | 547 | struct drm_dp_aux *aux); |
e5b92773 OV |
548 | enum drm_mode_subconnector |
549 | drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
550 | const u8 port_cap[4]); | |
551 | void drm_dp_set_subconnector_property(struct drm_connector *connector, | |
552 | enum drm_connector_status status, | |
553 | const u8 *dpcd, | |
554 | const u8 port_cap[4]); | |
516c0f7c | 555 | |
693c3ec5 LP |
556 | struct drm_dp_desc; |
557 | bool drm_dp_read_sink_count_cap(struct drm_connector *connector, | |
558 | const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
559 | const struct drm_dp_desc *desc); | |
4778ff05 | 560 | int drm_dp_read_sink_count(struct drm_dp_aux *aux); |
516c0f7c | 561 | |
9782f52a | 562 | int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, |
657586e4 | 563 | const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
9782f52a ID |
564 | u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); |
565 | int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, | |
657586e4 | 566 | const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
9782f52a ID |
567 | enum drm_dp_phy dp_phy, |
568 | u8 caps[DP_LTTPR_PHY_CAP_SIZE]); | |
569 | int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); | |
570 | int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); | |
571 | int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); | |
572 | bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); | |
573 | bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); | |
574 | ||
c908b1c4 | 575 | void drm_dp_remote_aux_init(struct drm_dp_aux *aux); |
acd8f414 | 576 | void drm_dp_aux_init(struct drm_dp_aux *aux); |
4f71d0cb DA |
577 | int drm_dp_aux_register(struct drm_dp_aux *aux); |
578 | void drm_dp_aux_unregister(struct drm_dp_aux *aux); | |
88759686 | 579 | |
79c1da7c TV |
580 | int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); |
581 | int drm_dp_stop_crc(struct drm_dp_aux *aux); | |
582 | ||
118b90f3 JN |
583 | struct drm_dp_dpcd_ident { |
584 | u8 oui[3]; | |
585 | u8 device_id[6]; | |
586 | u8 hw_rev; | |
587 | u8 sw_major_rev; | |
588 | u8 sw_minor_rev; | |
589 | } __packed; | |
590 | ||
591 | /** | |
592 | * struct drm_dp_desc - DP branch/sink device descriptor | |
593 | * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). | |
76fa998a | 594 | * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. |
118b90f3 JN |
595 | */ |
596 | struct drm_dp_desc { | |
597 | struct drm_dp_dpcd_ident ident; | |
76fa998a | 598 | u32 quirks; |
118b90f3 JN |
599 | }; |
600 | ||
601 | int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, | |
602 | bool is_branch); | |
603 | ||
76fa998a JN |
604 | /** |
605 | * enum drm_dp_quirk - Display Port sink/branch device specific quirks | |
606 | * | |
607 | * Display Port sink and branch devices in the wild have a variety of bugs, try | |
608 | * to collect them here. The quirks are shared, but it's up to the drivers to | |
7c553f8b | 609 | * implement workarounds for them. |
76fa998a JN |
610 | */ |
611 | enum drm_dp_quirk { | |
612 | /** | |
53ca2edc | 613 | * @DP_DPCD_QUIRK_CONSTANT_N: |
76fa998a JN |
614 | * |
615 | * The device requires main link attributes Mvid and Nvid to be limited | |
53ca2edc | 616 | * to 16 bits. So will give a constant value (0x8000) for compatability. |
76fa998a | 617 | */ |
53ca2edc | 618 | DP_DPCD_QUIRK_CONSTANT_N, |
7c5c641a | 619 | /** |
ed17b555 | 620 | * @DP_DPCD_QUIRK_NO_PSR: |
7c5c641a JRS |
621 | * |
622 | * The device does not support PSR even if reports that it supports or | |
623 | * driver still need to implement proper handling for such device. | |
624 | */ | |
625 | DP_DPCD_QUIRK_NO_PSR, | |
7974033e VS |
626 | /** |
627 | * @DP_DPCD_QUIRK_NO_SINK_COUNT: | |
628 | * | |
629 | * The device does not set SINK_COUNT to a non-zero value. | |
693c3ec5 LP |
630 | * The driver should ignore SINK_COUNT during detection. Note that |
631 | * drm_dp_read_sink_count_cap() automatically checks for this quirk. | |
7974033e VS |
632 | */ |
633 | DP_DPCD_QUIRK_NO_SINK_COUNT, | |
5b03f9d8 ML |
634 | /** |
635 | * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: | |
636 | * | |
637 | * The device supports MST DSC despite not supporting Virtual DPCD. | |
638 | * The DSC caps can be read from the physical aux instead. | |
639 | */ | |
640 | DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, | |
639e0db2 MK |
641 | /** |
642 | * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: | |
643 | * | |
644 | * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite | |
645 | * the DP_MAX_LINK_RATE register reporting a lower max multiplier. | |
646 | */ | |
647 | DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, | |
a6315ec2 ID |
648 | /** |
649 | * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC: | |
650 | * | |
651 | * The device applies HBLANK expansion for some modes, but this | |
652 | * requires enabling DSC. | |
653 | */ | |
654 | DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, | |
76fa998a JN |
655 | }; |
656 | ||
657 | /** | |
658 | * drm_dp_has_quirk() - does the DP device have a specific quirk | |
fedbfcc6 | 659 | * @desc: Device descriptor filled by drm_dp_read_desc() |
76fa998a JN |
660 | * @quirk: Quirk to query for |
661 | * | |
662 | * Return true if DP device identified by @desc has @quirk. | |
663 | */ | |
664 | static inline bool | |
7c553f8b | 665 | drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) |
76fa998a | 666 | { |
7c553f8b | 667 | return desc->quirks & BIT(quirk); |
76fa998a JN |
668 | } |
669 | ||
867cf9cd LP |
670 | /** |
671 | * struct drm_edp_backlight_info - Probed eDP backlight info struct | |
672 | * @pwmgen_bit_count: The pwmgen bit count | |
673 | * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any | |
674 | * @max: The maximum backlight level that may be set | |
675 | * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? | |
676 | * @aux_enable: Does the panel support the AUX enable cap? | |
f58a4353 | 677 | * @aux_set: Does the panel support setting the brightness through AUX? |
867cf9cd LP |
678 | * |
679 | * This structure contains various data about an eDP backlight, which can be populated by using | |
680 | * drm_edp_backlight_init(). | |
681 | */ | |
682 | struct drm_edp_backlight_info { | |
683 | u8 pwmgen_bit_count; | |
684 | u8 pwm_freq_pre_divider; | |
685 | u16 max; | |
686 | ||
687 | bool lsb_reg_used : 1; | |
688 | bool aux_enable : 1; | |
f58a4353 | 689 | bool aux_set : 1; |
867cf9cd LP |
690 | }; |
691 | ||
692 | int | |
693 | drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, | |
694 | u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], | |
695 | u16 *current_level, u8 *current_mode); | |
696 | int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, | |
697 | u16 level); | |
698 | int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, | |
699 | u16 level); | |
700 | int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); | |
701 | ||
072ed343 DA |
702 | #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ |
703 | (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) | |
704 | ||
705 | int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); | |
706 | ||
707 | #else | |
708 | ||
709 | static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, | |
710 | struct drm_dp_aux *aux) | |
711 | { | |
712 | return 0; | |
713 | } | |
714 | ||
715 | #endif | |
716 | ||
2c6d1fff HV |
717 | #ifdef CONFIG_DRM_DP_CEC |
718 | void drm_dp_cec_irq(struct drm_dp_aux *aux); | |
ae85b0df DM |
719 | void drm_dp_cec_register_connector(struct drm_dp_aux *aux, |
720 | struct drm_connector *connector); | |
2c6d1fff | 721 | void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); |
113cdddc | 722 | void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address); |
2c6d1fff HV |
723 | void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); |
724 | void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); | |
725 | #else | |
726 | static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) | |
727 | { | |
728 | } | |
729 | ||
ae85b0df DM |
730 | static inline void |
731 | drm_dp_cec_register_connector(struct drm_dp_aux *aux, | |
732 | struct drm_connector *connector) | |
2c6d1fff HV |
733 | { |
734 | } | |
735 | ||
736 | static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) | |
737 | { | |
738 | } | |
739 | ||
113cdddc JN |
740 | static inline void drm_dp_cec_attach(struct drm_dp_aux *aux, |
741 | u16 source_physical_address) | |
742 | { | |
743 | } | |
744 | ||
2c6d1fff HV |
745 | static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, |
746 | const struct edid *edid) | |
747 | { | |
748 | } | |
749 | ||
750 | static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) | |
751 | { | |
752 | } | |
753 | ||
754 | #endif | |
755 | ||
4342f839 AM |
756 | /** |
757 | * struct drm_dp_phy_test_params - DP Phy Compliance parameters | |
758 | * @link_rate: Requested Link rate from DPCD 0x219 | |
759 | * @num_lanes: Number of lanes requested by sing through DPCD 0x220 | |
760 | * @phy_pattern: DP Phy test pattern from DPCD 0x248 | |
38a8b32f | 761 | * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B |
4342f839 AM |
762 | * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 |
763 | * @enhanced_frame_cap: flag for enhanced frame capability. | |
764 | */ | |
765 | struct drm_dp_phy_test_params { | |
766 | int link_rate; | |
767 | u8 num_lanes; | |
768 | u8 phy_pattern; | |
769 | u8 hbr2_reset[2]; | |
770 | u8 custom80[10]; | |
771 | bool enhanced_frame_cap; | |
772 | }; | |
773 | ||
774 | int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, | |
775 | struct drm_dp_phy_test_params *data); | |
776 | int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, | |
777 | struct drm_dp_phy_test_params *data, u8 dp_rev); | |
ce32a623 AN |
778 | int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
779 | const u8 port_cap[4]); | |
780 | int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); | |
781 | bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); | |
782 | int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, | |
68a8c645 | 783 | u8 frl_mode); |
ce32a623 | 784 | int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, |
68a8c645 | 785 | u8 frl_type); |
ce32a623 AN |
786 | int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); |
787 | int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); | |
788 | ||
789 | bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); | |
790 | int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); | |
3ce98018 SS |
791 | void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, |
792 | struct drm_connector *connector); | |
e2e16da3 AN |
793 | bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); |
794 | int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); | |
795 | int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); | |
796 | int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); | |
797 | int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); | |
798 | int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); | |
799 | int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); | |
07c9b863 AN |
800 | bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], |
801 | const u8 port_cap[4], u8 color_spc); | |
802 | int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); | |
ce32a623 | 803 | |
c1d6a22b ID |
804 | #define DRM_DP_BW_OVERHEAD_MST BIT(0) |
805 | #define DRM_DP_BW_OVERHEAD_UHBR BIT(1) | |
806 | #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2) | |
807 | #define DRM_DP_BW_OVERHEAD_FEC BIT(3) | |
808 | #define DRM_DP_BW_OVERHEAD_DSC BIT(4) | |
809 | ||
810 | int drm_dp_bw_overhead(int lane_count, int hactive, | |
811 | int dsc_slice_count, | |
812 | int bpp_x16, unsigned long flags); | |
813 | int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); | |
1e59ab50 | 814 | int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes); |
c1d6a22b | 815 | |
ab2c0672 | 816 | #endif /* _DRM_DP_HELPER_H_ */ |