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1 | /* |
2 | * Copyright 2003 Motorola,Inc. | |
3 | * Xianghua Xiao(x.xiao@motorola.com) | |
4 | */ | |
5 | ||
6 | #ifndef __E500_H__ | |
7 | #define __E500_H__ | |
8 | ||
9 | #ifndef __ASSEMBLY__ | |
10 | ||
11 | typedef struct | |
12 | { | |
13 | unsigned long freqProcessor; | |
14 | unsigned long freqSystemBus; | |
15 | } MPC85xx_SYS_INFO; | |
16 | ||
17 | #endif /* _ASMLANGUAGE */ | |
18 | ||
19 | /* Motorola E500 core provides 16 TLB1 entries; they can be used for | |
20 | * initial memory mapping like legacy BAT registers do. Usually we | |
21 | * use four MAS registers(MAS0-3) to operate on TLB1 entries. | |
22 | * | |
9aea9530 WD |
23 | * While there are 16 Entries with variable Page Sizes in TLB1, |
24 | * there are also 256 Entries with fixed 4K pages in TLB0. | |
25 | * | |
42d1f039 WD |
26 | * We also need LAWs(Local Access Window) to associate a range of |
27 | * the local 32-bit address space with a particular target interface | |
28 | * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM. | |
29 | * | |
30 | * We put TLB1/LAW code here because memory mapping is board-specific | |
31 | * instead of cpu-specific. | |
9aea9530 WD |
32 | * |
33 | * While these macros are all nominally for TLB1 by name, they can | |
34 | * also be used for TLB0 as well. | |
42d1f039 WD |
35 | */ |
36 | ||
9aea9530 WD |
37 | |
38 | /* | |
39 | * Convert addresses to Effective and Real Page Numbers. | |
40 | * Grab the high 20-bits and shift 'em down, dropping the "byte offset". | |
41 | */ | |
42 | #define E500_TLB_EPN(addr) (((addr) >> 12) & 0xfffff) | |
43 | #define E500_TLB_RPN(addr) (((addr) >> 12) & 0xfffff) | |
44 | ||
45 | ||
42d1f039 WD |
46 | /* MAS0 |
47 | * tlbsel(TLB Select):0,1 | |
48 | * esel(Entry Select): 0,1,2,...,15 for TLB1 | |
49 | * nv(Next victim):0,1 | |
50 | */ | |
51 | #define TLB1_MAS0(tlbsel,esel,nv) \ | |
52 | ((((tlbsel) << 28) & MAS0_TLBSEL) |\ | |
53 | (((esel) << 16) & MAS0_ESEL ) |\ | |
54 | (nv) ) | |
55 | ||
56 | ||
57 | /* MAS1 | |
58 | * v(TLB valid bit):0,1 | |
59 | * iprot(invalidate protect):0,1 | |
60 | * tid(translation identity):8bit to match process IDs | |
61 | * ts(translation space,comparing with MSR[IS,DS]): 0,1 | |
62 | * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M) | |
63 | */ | |
64 | #define TLB1_MAS1(v,iprot,tid,ts,tsize) \ | |
65 | ((((v) << 31) & MAS1_VALID) |\ | |
66 | (((iprot) << 30) & MAS1_IPROT) |\ | |
67 | (((tid) << 16) & MAS1_TID) |\ | |
68 | (((ts) << 12) & MAS1_TS) |\ | |
69 | (((tsize) << 8) & MAS1_TSIZE) ) | |
70 | ||
71 | ||
72 | /* MAS2 | |
73 | * epn(effective page number):20bits | |
74 | * sharen(Shared cache state):0,1 | |
75 | * x0,x1(implementation specific page attribute):0,1 | |
76 | * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded, | |
77 | * endianness):0,1 | |
78 | */ | |
79 | #define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \ | |
80 | ((((epn) << 12) & MAS2_EPN) |\ | |
81 | (((sharen) << 9) & MAS2_SHAREN) |\ | |
82 | (((x0) << 6) & MAS2_X0) |\ | |
83 | (((x1) << 5) & MAS2_X1) |\ | |
84 | (((w) << 4) & MAS2_W) |\ | |
85 | (((i) << 3) & MAS2_I) |\ | |
86 | (((m) << 2) & MAS2_M) |\ | |
87 | (((g) << 1) & MAS2_G) |\ | |
88 | (e) ) | |
89 | ||
90 | ||
91 | /* MAS3 | |
92 | * rpn(real page number):20bits | |
93 | * u0-u3(user bits, useful for page table management in OS):0,1 | |
94 | * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read, | |
95 | * write,execute permission). | |
96 | */ | |
97 | #define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \ | |
98 | ((((rpn) << 12) & MAS3_RPN) |\ | |
99 | (((u0) << 9) & MAS3_U0) |\ | |
100 | (((u1) << 8) & MAS3_U1) |\ | |
101 | (((u2) << 7) & MAS3_U2) |\ | |
102 | (((u3) << 6) & MAS3_U3) |\ | |
103 | (((ux) << 5) & MAS3_UX) |\ | |
104 | (((sx) << 4) & MAS3_SX) |\ | |
105 | (((uw) << 3) & MAS3_UW) |\ | |
106 | (((sw) << 2) & MAS3_SW) |\ | |
107 | (((ur) << 1) & MAS3_UR) |\ | |
108 | (sr) ) | |
109 | ||
110 | ||
111 | #define RESET_VECTOR 0xfffffffc | |
112 | #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache | |
113 | line aligned data. */ | |
114 | ||
115 | #endif /* __E500_H__ */ |