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Commit | Line | Data |
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b92e5a22 FB |
1 | /* |
2 | * Software MMU support | |
5fafdf24 | 3 | * |
efbf29b6 BS |
4 | * Generate inline load/store functions for one MMU mode and data |
5 | * size. | |
6 | * | |
82f11917 | 7 | * Generate a store function as well as signed and unsigned loads. |
efbf29b6 | 8 | * |
c773828a | 9 | * Not used directly but included from cpu_ldst.h. |
efbf29b6 | 10 | * |
b92e5a22 FB |
11 | * Copyright (c) 2003 Fabrice Bellard |
12 | * | |
13 | * This library is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU Lesser General Public | |
15 | * License as published by the Free Software Foundation; either | |
16 | * version 2 of the License, or (at your option) any later version. | |
17 | * | |
18 | * This library is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
21 | * Lesser General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 24 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
b92e5a22 | 25 | */ |
dcdaadb6 LV |
26 | |
27 | #if !defined(SOFTMMU_CODE_ACCESS) | |
0ab8ed18 | 28 | #include "trace-root.h" |
dcdaadb6 LV |
29 | #endif |
30 | ||
31 | #include "trace/mem.h" | |
32 | ||
b92e5a22 FB |
33 | #if DATA_SIZE == 8 |
34 | #define SUFFIX q | |
61382a50 | 35 | #define USUFFIX q |
b92e5a22 | 36 | #define DATA_TYPE uint64_t |
282dffc8 | 37 | #define SHIFT 3 |
b92e5a22 FB |
38 | #elif DATA_SIZE == 4 |
39 | #define SUFFIX l | |
61382a50 | 40 | #define USUFFIX l |
b92e5a22 | 41 | #define DATA_TYPE uint32_t |
282dffc8 | 42 | #define SHIFT 2 |
b92e5a22 FB |
43 | #elif DATA_SIZE == 2 |
44 | #define SUFFIX w | |
61382a50 | 45 | #define USUFFIX uw |
b92e5a22 FB |
46 | #define DATA_TYPE uint16_t |
47 | #define DATA_STYPE int16_t | |
282dffc8 | 48 | #define SHIFT 1 |
b92e5a22 FB |
49 | #elif DATA_SIZE == 1 |
50 | #define SUFFIX b | |
61382a50 | 51 | #define USUFFIX ub |
b92e5a22 FB |
52 | #define DATA_TYPE uint8_t |
53 | #define DATA_STYPE int8_t | |
282dffc8 | 54 | #define SHIFT 0 |
b92e5a22 FB |
55 | #else |
56 | #error unsupported data size | |
57 | #endif | |
58 | ||
b92e5a22 FB |
59 | #if DATA_SIZE == 8 |
60 | #define RES_TYPE uint64_t | |
61 | #else | |
c086b783 | 62 | #define RES_TYPE uint32_t |
b92e5a22 FB |
63 | #endif |
64 | ||
859d7612 | 65 | #ifdef SOFTMMU_CODE_ACCESS |
84b7b8e7 | 66 | #define ADDR_READ addr_code |
a6c9eac0 | 67 | #define MMUSUFFIX _cmmu |
282dffc8 PD |
68 | #define URETSUFFIX SUFFIX |
69 | #define SRETSUFFIX SUFFIX | |
84b7b8e7 FB |
70 | #else |
71 | #define ADDR_READ addr_read | |
a6c9eac0 | 72 | #define MMUSUFFIX _mmu |
282dffc8 PD |
73 | #define URETSUFFIX USUFFIX |
74 | #define SRETSUFFIX glue(s, SUFFIX) | |
84b7b8e7 | 75 | #endif |
b92e5a22 | 76 | |
e16c53fa FB |
77 | /* generic load/store macros */ |
78 | ||
e141ab52 | 79 | static inline RES_TYPE |
282dffc8 PD |
80 | glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, |
81 | target_ulong ptr, | |
82 | uintptr_t retaddr) | |
b92e5a22 | 83 | { |
4d7a0880 | 84 | int page_index; |
b92e5a22 | 85 | RES_TYPE res; |
c27004ec | 86 | target_ulong addr; |
6ebbf390 | 87 | int mmu_idx; |
282dffc8 | 88 | TCGMemOpIdx oi; |
61382a50 | 89 | |
dcdaadb6 LV |
90 | #if !defined(SOFTMMU_CODE_ACCESS) |
91 | trace_guest_mem_before_exec( | |
92 | ENV_GET_CPU(env), ptr, | |
93 | trace_mem_build_info(SHIFT, false, MO_TE, false)); | |
94 | #endif | |
95 | ||
c27004ec | 96 | addr = ptr; |
4d7a0880 | 97 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
6ebbf390 | 98 | mmu_idx = CPU_MMU_INDEX; |
551bd27f TS |
99 | if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ != |
100 | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { | |
282dffc8 PD |
101 | oi = make_memop_idx(SHIFT, mmu_idx); |
102 | res = glue(glue(helper_ret_ld, URETSUFFIX), MMUSUFFIX)(env, addr, | |
103 | oi, retaddr); | |
b92e5a22 | 104 | } else { |
23ddbf08 | 105 | uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend; |
35539232 | 106 | res = glue(glue(ld, USUFFIX), _p)((uint8_t *)hostaddr); |
b92e5a22 FB |
107 | } |
108 | return res; | |
109 | } | |
110 | ||
282dffc8 PD |
111 | static inline RES_TYPE |
112 | glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr) | |
113 | { | |
114 | return glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(env, ptr, 0); | |
115 | } | |
116 | ||
b92e5a22 | 117 | #if DATA_SIZE <= 2 |
e141ab52 | 118 | static inline int |
282dffc8 PD |
119 | glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, |
120 | target_ulong ptr, | |
121 | uintptr_t retaddr) | |
b92e5a22 | 122 | { |
4d7a0880 | 123 | int res, page_index; |
c27004ec | 124 | target_ulong addr; |
6ebbf390 | 125 | int mmu_idx; |
282dffc8 | 126 | TCGMemOpIdx oi; |
61382a50 | 127 | |
dcdaadb6 LV |
128 | #if !defined(SOFTMMU_CODE_ACCESS) |
129 | trace_guest_mem_before_exec( | |
130 | ENV_GET_CPU(env), ptr, | |
131 | trace_mem_build_info(SHIFT, true, MO_TE, false)); | |
132 | #endif | |
133 | ||
c27004ec | 134 | addr = ptr; |
4d7a0880 | 135 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
6ebbf390 | 136 | mmu_idx = CPU_MMU_INDEX; |
551bd27f TS |
137 | if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ != |
138 | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { | |
282dffc8 PD |
139 | oi = make_memop_idx(SHIFT, mmu_idx); |
140 | res = (DATA_STYPE)glue(glue(helper_ret_ld, SRETSUFFIX), | |
141 | MMUSUFFIX)(env, addr, oi, retaddr); | |
b92e5a22 | 142 | } else { |
23ddbf08 | 143 | uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend; |
35539232 | 144 | res = glue(glue(lds, SUFFIX), _p)((uint8_t *)hostaddr); |
b92e5a22 FB |
145 | } |
146 | return res; | |
147 | } | |
282dffc8 PD |
148 | |
149 | static inline int | |
150 | glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr) | |
151 | { | |
152 | return glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(env, ptr, 0); | |
153 | } | |
b92e5a22 FB |
154 | #endif |
155 | ||
859d7612 | 156 | #ifndef SOFTMMU_CODE_ACCESS |
84b7b8e7 | 157 | |
e16c53fa FB |
158 | /* generic store macro */ |
159 | ||
e141ab52 | 160 | static inline void |
282dffc8 PD |
161 | glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, |
162 | target_ulong ptr, | |
163 | RES_TYPE v, uintptr_t retaddr) | |
b92e5a22 | 164 | { |
4d7a0880 | 165 | int page_index; |
c27004ec | 166 | target_ulong addr; |
6ebbf390 | 167 | int mmu_idx; |
282dffc8 | 168 | TCGMemOpIdx oi; |
61382a50 | 169 | |
dcdaadb6 LV |
170 | #if !defined(SOFTMMU_CODE_ACCESS) |
171 | trace_guest_mem_before_exec( | |
172 | ENV_GET_CPU(env), ptr, | |
173 | trace_mem_build_info(SHIFT, false, MO_TE, true)); | |
174 | #endif | |
175 | ||
c27004ec | 176 | addr = ptr; |
4d7a0880 | 177 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
6ebbf390 | 178 | mmu_idx = CPU_MMU_INDEX; |
551bd27f TS |
179 | if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write != |
180 | (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { | |
282dffc8 PD |
181 | oi = make_memop_idx(SHIFT, mmu_idx); |
182 | glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, v, oi, | |
183 | retaddr); | |
b92e5a22 | 184 | } else { |
23ddbf08 | 185 | uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend; |
35539232 | 186 | glue(glue(st, SUFFIX), _p)((uint8_t *)hostaddr, v); |
b92e5a22 FB |
187 | } |
188 | } | |
189 | ||
282dffc8 PD |
190 | static inline void |
191 | glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr, | |
192 | RES_TYPE v) | |
193 | { | |
194 | glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(env, ptr, v, 0); | |
195 | } | |
196 | ||
859d7612 | 197 | #endif /* !SOFTMMU_CODE_ACCESS */ |
84b7b8e7 | 198 | |
b92e5a22 FB |
199 | #undef RES_TYPE |
200 | #undef DATA_TYPE | |
201 | #undef DATA_STYPE | |
202 | #undef SUFFIX | |
61382a50 | 203 | #undef USUFFIX |
b92e5a22 | 204 | #undef DATA_SIZE |
61382a50 | 205 | #undef MMUSUFFIX |
84b7b8e7 | 206 | #undef ADDR_READ |
282dffc8 PD |
207 | #undef URETSUFFIX |
208 | #undef SRETSUFFIX | |
209 | #undef SHIFT |