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4bb87d2b ML |
1 | /* |
2 | * Copyright (C) 2011 Andes Technology Corporation | |
3 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
4bb87d2b ML |
6 | */ |
7 | ||
8 | /* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */ | |
9 | #ifndef __FTAHBC020S_H | |
10 | #define __FTAHBC202S_H | |
11 | ||
12 | /* Registers Offsets */ | |
13 | ||
14 | /* | |
15 | * AHB Slave BSR, offset: n * 4, n=0~31 | |
16 | */ | |
17 | #ifndef __ASSEMBLY__ | |
18 | struct ftahbc02s { | |
19 | unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */ | |
20 | unsigned int pcr; /* 0x80 - Priority Ctrl Reg */ | |
21 | unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */ | |
22 | unsigned int cr; /* 0x88 - Ctrl Reg */ | |
23 | }; | |
24 | #endif /* __ASSEMBLY__ */ | |
25 | ||
26 | /* | |
27 | * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register | |
28 | */ | |
29 | #define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20) | |
30 | #define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16) | |
31 | /* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */ | |
32 | #define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */ | |
33 | ||
34 | /* | |
35 | * FTAHBC020S_PCR - Priority Control Register | |
36 | */ | |
37 | #define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */ | |
38 | ||
39 | /* | |
40 | * FTAHBC020S_CR - Interrupt Control Register | |
41 | */ | |
42 | #define FTAHBC020S_CR_INTSTS (1 << 24) | |
43 | #define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) | |
44 | #define FTAHBC020S_CR_INTSMASK (1 << 16) | |
45 | #define FTAHBC020S_CR_REMAP (1 << 0) | |
46 | ||
47 | #endif /* __FTAHBC020S_H */ |