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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
f8ef0d4f ML |
2 | /* |
3 | * Faraday FTSDC010 Secure Digital Memory Card Host Controller | |
4 | * | |
5 | * Copyright (C) 2011 Andes Technology Corporation | |
6 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> | |
f8ef0d4f ML |
7 | */ |
8 | ||
9 | #ifndef __FTSDC010_H | |
10 | #define __FTSDC010_H | |
11 | ||
12 | #ifndef __ASSEMBLY__ | |
f6c3b346 | 13 | |
f8ef0d4f ML |
14 | /* sd controller register */ |
15 | struct ftsdc010_mmc { | |
16 | unsigned int cmd; /* 0x00 - command reg */ | |
17 | unsigned int argu; /* 0x04 - argument reg */ | |
18 | unsigned int rsp0; /* 0x08 - response reg0 */ | |
19 | unsigned int rsp1; /* 0x0c - response reg1 */ | |
20 | unsigned int rsp2; /* 0x10 - response reg2 */ | |
21 | unsigned int rsp3; /* 0x14 - response reg3 */ | |
22 | unsigned int rsp_cmd; /* 0x18 - responded cmd reg */ | |
23 | unsigned int dcr; /* 0x1c - data control reg */ | |
24 | unsigned int dtr; /* 0x20 - data timer reg */ | |
25 | unsigned int dlr; /* 0x24 - data length reg */ | |
26 | unsigned int status; /* 0x28 - status reg */ | |
27 | unsigned int clr; /* 0x2c - clear reg */ | |
28 | unsigned int int_mask; /* 0x30 - intrrupt mask reg */ | |
29 | unsigned int pcr; /* 0x34 - power control reg */ | |
30 | unsigned int ccr; /* 0x38 - clock contorl reg */ | |
31 | unsigned int bwr; /* 0x3c - bus width reg */ | |
32 | unsigned int dwr; /* 0x40 - data window reg */ | |
33 | #ifndef CONFIG_FTSDC010_SDIO | |
34 | unsigned int feature; /* 0x44 - feature reg */ | |
35 | unsigned int rev; /* 0x48 - revision reg */ | |
36 | #else | |
37 | unsigned int mmc_intr_time; /* 0x44 - MMC int resp time reg */ | |
38 | unsigned int gpo; /* 0x48 - gerenal purpose output */ | |
39 | unsigned int reserved[8]; /* 0x50 - 0x68 reserved */ | |
40 | unsigned int sdio_ctrl1; /* 0x6c - SDIO control reg 1 */ | |
41 | unsigned int sdio_ctrl2; /* 0x70 - SDIO control reg 2 */ | |
42 | unsigned int sdio_status; /* 0x74 - SDIO status regi */ | |
43 | unsigned int reserved1[9]; /* 0x78 - 0x98 reserved */ | |
44 | unsigned int feature; /* 0x9c - feature reg */ | |
45 | unsigned int rev; /* 0xa0 - revision reg */ | |
46 | #endif /* CONFIG_FTSDC010_SDIO */ | |
47 | }; | |
48 | ||
49 | struct mmc_host { | |
50 | struct ftsdc010_mmc *reg; | |
51 | unsigned int version; /* SDHCI spec. version */ | |
52 | unsigned int clock; /* Current clock (MHz) */ | |
53 | unsigned int fifo_len; /* bytes */ | |
54 | unsigned int last_opcode; /* Last OP Code */ | |
55 | unsigned int card_type; /* Card type */ | |
56 | }; | |
57 | ||
58 | /* functions */ | |
59 | int ftsdc010_mmc_init(int dev_index); | |
60 | ||
61 | #endif /* __ASSEMBLY__ */ | |
62 | ||
63 | /* global defines */ | |
64 | #define FTSDC010_CMD_RETRY 0x100000 | |
65 | #define FTSDC010_PIO_RETRY 100 /* pio retry times */ | |
66 | #define FTSDC010_DELAY_UNIT 100 /* 100 us */ | |
67 | ||
68 | /* define from Linux kernel - include/linux/mmc/card.h */ | |
69 | #define MMC_TYPE_SDIO 2 /* SDIO card */ | |
70 | ||
71 | /* define for mmc layer */ | |
72 | #define MMC_DATA_BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ) | |
73 | ||
74 | /* this part is strange */ | |
75 | #define FTSDC010_SDIO_CTRL1_REG 0x0000006C | |
76 | #define FTSDC010_SDIO_CTRL2_REG 0x0000006C | |
77 | #define FTSDC010_SDIO_STATUS_REG 0x00000070 | |
78 | ||
79 | /* 0x00 - command register */ | |
80 | #define FTSDC010_CMD_IDX(x) (((x) & 0x3f) << 0) | |
81 | #define FTSDC010_CMD_NEED_RSP (1 << 6) | |
82 | #define FTSDC010_CMD_LONG_RSP (1 << 7) | |
83 | #define FTSDC010_CMD_APP_CMD (1 << 8) | |
84 | #define FTSDC010_CMD_CMD_EN (1 << 9) | |
85 | #define FTSDC010_CMD_SDC_RST (1 << 10) | |
86 | #define FTSDC010_CMD_MMC_INT_STOP (1 << 11) | |
87 | ||
88 | /* 0x18 - responded command register */ | |
89 | #define FTSDC010_RSP_CMD_IDX(x) (((x) >> 0) & 0x3f) | |
90 | #define FTSDC010_RSP_CMD_APP (1 << 6) | |
91 | ||
92 | /* 0x1c - data control register */ | |
93 | #define FTSDC010_DCR_BLK_SIZE(x) (((x) & 0xf) << 0) | |
94 | #define FTSDC010_DCR_DATA_WRITE (1 << 4) | |
95 | #define FTSDC010_DCR_DMA_EN (1 << 5) | |
96 | #define FTSDC010_DCR_DATA_EN (1 << 6) | |
97 | #ifdef CONFIG_FTSDC010_SDIO | |
98 | #define FTSDC010_DCR_FIFOTH (1 << 7) | |
99 | #define FTSDC010_DCR_DMA_TYPE(x) (((x) & 0x3) << 8) | |
100 | #define FTSDC010_DCR_FIFO_RST (1 << 10) | |
101 | #endif /* CONFIG_FTSDC010_SDIO */ | |
102 | ||
103 | #define FTSDC010_DCR_DMA_TYPE_1 0x0 /* Single r/w */ | |
104 | #define FTSDC010_DCR_DMA_TYPE_4 0x1 /* Burst 4 r/w */ | |
105 | #define FTSDC010_DCR_DMA_TYPE_8 0x2 /* Burst 8 r/w */ | |
106 | ||
107 | #define FTSDC010_DCR_BLK_BYTES(x) (ffs(x) - 1) /* 1B - 2048B */ | |
108 | ||
109 | /* CPRM related define */ | |
110 | #define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN 0x000008 | |
111 | #define FTSDC010_CPRM_DATA_SWAP_HL_EN 0x000010 | |
112 | ||
113 | /* 0x28 - status register */ | |
114 | #define FTSDC010_STATUS_RSP_CRC_FAIL (1 << 0) | |
115 | #define FTSDC010_STATUS_DATA_CRC_FAIL (1 << 1) | |
116 | #define FTSDC010_STATUS_RSP_TIMEOUT (1 << 2) | |
117 | #define FTSDC010_STATUS_DATA_TIMEOUT (1 << 3) | |
118 | #define FTSDC010_STATUS_RSP_CRC_OK (1 << 4) | |
119 | #define FTSDC010_STATUS_DATA_CRC_OK (1 << 5) | |
120 | #define FTSDC010_STATUS_CMD_SEND (1 << 6) | |
121 | #define FTSDC010_STATUS_DATA_END (1 << 7) | |
122 | #define FTSDC010_STATUS_FIFO_URUN (1 << 8) | |
123 | #define FTSDC010_STATUS_FIFO_ORUN (1 << 9) | |
124 | #define FTSDC010_STATUS_CARD_CHANGE (1 << 10) | |
125 | #define FTSDC010_STATUS_CARD_DETECT (1 << 11) | |
126 | #define FTSDC010_STATUS_WRITE_PROT (1 << 12) | |
127 | #ifdef CONFIG_FTSDC010_SDIO | |
128 | #define FTSDC010_STATUS_CP_READY (1 << 13) /* reserved ? */ | |
129 | #define FTSDC010_STATUS_CP_BUF_READY (1 << 14) /* reserved ? */ | |
130 | #define FTSDC010_STATUS_PLAIN_TEXT_READY (1 << 15) /* reserved ? */ | |
131 | #define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */ | |
132 | #define FTSDC010_STATUS_DATA0_STATUS (1 << 17) | |
133 | #endif /* CONFIG_FTSDC010_SDIO */ | |
f6c3b346 KJS |
134 | #define FTSDC010_STATUS_RSP_ERROR \ |
135 | (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT) | |
136 | #define FTSDC010_STATUS_RSP_MASK \ | |
137 | (FTSDC010_STATUS_RSP_ERROR | FTSDC010_STATUS_RSP_CRC_OK) | |
138 | #define FTSDC010_STATUS_DATA_ERROR \ | |
139 | (FTSDC010_STATUS_DATA_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT) | |
140 | #define FTSDC010_STATUS_DATA_MASK \ | |
141 | (FTSDC010_STATUS_DATA_ERROR | FTSDC010_STATUS_DATA_CRC_OK \ | |
142 | | FTSDC010_STATUS_DATA_END) | |
f8ef0d4f ML |
143 | |
144 | /* 0x2c - clear register */ | |
145 | #define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0) | |
146 | #define FTSDC010_CLR_DATA_CRC_FAIL (1 << 1) | |
147 | #define FTSDC010_CLR_RSP_TIMEOUT (1 << 2) | |
148 | #define FTSDC010_CLR_DATA_TIMEOUT (1 << 3) | |
149 | #define FTSDC010_CLR_RSP_CRC_OK (1 << 4) | |
150 | #define FTSDC010_CLR_DATA_CRC_OK (1 << 5) | |
151 | #define FTSDC010_CLR_CMD_SEND (1 << 6) | |
152 | #define FTSDC010_CLR_DATA_END (1 << 7) | |
153 | #define FTSDC010_STATUS_FIFO_URUN (1 << 8) /* reserved ? */ | |
154 | #define FTSDC010_STATUS_FIFO_ORUN (1 << 9) /* reserved ? */ | |
155 | #define FTSDC010_CLR_CARD_CHANGE (1 << 10) | |
156 | #ifdef CONFIG_FTSDC010_SDIO | |
157 | #define FTSDC010_CLR_SDIO_IRPT (1 << 16) | |
158 | #endif /* CONFIG_FTSDC010_SDIO */ | |
159 | ||
160 | /* 0x30 - interrupt mask register */ | |
161 | #define FTSDC010_INT_MASK_RSP_CRC_FAIL (1 << 0) | |
162 | #define FTSDC010_INT_MASK_DATA_CRC_FAIL (1 << 1) | |
163 | #define FTSDC010_INT_MASK_RSP_TIMEOUT (1 << 2) | |
164 | #define FTSDC010_INT_MASK_DATA_TIMEOUT (1 << 3) | |
165 | #define FTSDC010_INT_MASK_RSP_CRC_OK (1 << 4) | |
166 | #define FTSDC010_INT_MASK_DATA_CRC_OK (1 << 5) | |
167 | #define FTSDC010_INT_MASK_CMD_SEND (1 << 6) | |
168 | #define FTSDC010_INT_MASK_DATA_END (1 << 7) | |
169 | #define FTSDC010_INT_MASK_FIFO_URUN (1 << 8) | |
170 | #define FTSDC010_INT_MASK_FIFO_ORUN (1 << 9) | |
171 | #define FTSDC010_INT_MASK_CARD_CHANGE (1 << 10) | |
172 | #ifdef CONFIG_FTSDC010_SDIO | |
173 | #define FTSDC010_INT_MASK_CP_READY (1 << 13) | |
174 | #define FTSDC010_INT_MASK_CP_BUF_READY (1 << 14) | |
175 | #define FTSDC010_INT_MASK_PLAIN_TEXT_READY (1 << 15) | |
176 | #define FTSDC010_INT_MASK_SDIO_IRPT (1 << 16) | |
177 | #define FTSDC010_STATUS_DATA0_STATUS (1 << 17) | |
178 | #endif /* CONFIG_FTSDC010_SDIO */ | |
179 | ||
180 | /* ? */ | |
181 | #define FTSDC010_CARD_INSERT 0x0 | |
182 | #define FTSDC010_CARD_REMOVE FTSDC010_STATUS_REG_CARD_DETECT | |
183 | ||
184 | /* 0x34 - power control register */ | |
185 | #define FTSDC010_PCR_POWER(x) (((x) & 0xf) << 0) | |
186 | #define FTSDC010_PCR_POWER_ON (1 << 4) | |
187 | ||
188 | /* 0x38 - clock control register */ | |
189 | #define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0) | |
190 | #define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */ | |
191 | #define FTSDC010_CCR_CLK_DIS (1 << 8) | |
f6c3b346 | 192 | #define FTSDC010_CCR_CLK_HISPD (1 << 9) /* high speed */ |
f8ef0d4f ML |
193 | |
194 | /* card type */ | |
195 | #define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE | |
196 | #define FTSDC010_CARD_TYPE_MMC 0x0 | |
197 | ||
198 | /* 0x3c - bus width register */ | |
f6c3b346 KJS |
199 | #define FTSDC010_BWR_MODE_1BIT (1 << 0) /* 1 bit mode enabled */ |
200 | #define FTSDC010_BWR_MODE_8BIT (1 << 1) /* 8 bit mode enabled */ | |
201 | #define FTSDC010_BWR_MODE_4BIT (1 << 2) /* 4 bit mode enabled */ | |
202 | #define FTSDC010_BWR_MODE_MASK (7 << 0) | |
203 | #define FTSDC010_BWR_MODE_SHIFT (0) | |
204 | #define FTSDC010_BWR_CAPS_1BIT (0 << 3) /* 1 bits mode supported */ | |
205 | #define FTSDC010_BWR_CAPS_4BIT (1 << 3) /* 1,4 bits mode supported */ | |
206 | #define FTSDC010_BWR_CAPS_8BIT (2 << 3) /* 1,4,8 bits mode supported */ | |
207 | #define FTSDC010_BWR_CAPS_MASK (3 << 3) | |
208 | #define FTSDC010_BWR_CAPS_SHIFT (3) | |
209 | #define FTSDC010_BWR_CARD_DETECT (1 << 5) | |
f8ef0d4f ML |
210 | |
211 | /* 0x44 or 0x9c - feature register */ | |
212 | #define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff) | |
213 | #define FTSDC010_FEATURE_CPRM_FUNCTION (1 << 8) | |
214 | ||
215 | #define FTSDC010_FIFO_DEPTH_4 0x04 | |
216 | #define FTSDC010_FIFO_DEPTH_8 0x08 | |
217 | #define FTSDC010_FIFO_DEPTH_16 0x10 | |
218 | ||
219 | /* 0x48 or 0xa0 - revision register */ | |
220 | #define FTSDC010_REV_REVISION(x) (((x) & 0xff) >> 0) | |
221 | #define FTSDC010_REV_MINOR(x) (((x) & 0xff00) >> 8) | |
222 | #define FTSDC010_REV_MAJOR(x) (((x) & 0xffff0000) >> 16) | |
223 | ||
224 | #ifdef CONFIG_FTSDC010_SDIO | |
225 | /* 0x44 - general purpose output */ | |
226 | #define FTSDC010_GPO_PORT(x) (((x) & 0xf) << 0) | |
227 | ||
228 | /* 0x6c - sdio control register 1 */ | |
229 | #define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x) (((x) & 0xfff) << 0) | |
230 | #define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE (1 << 12) | |
231 | #define FTSDC010_SDIO_CTRL1_READ_WAIT_EN (1 << 13) | |
232 | #define FTSDC010_SDIO_CTRL1_SDIO_ENABLE (1 << 14) | |
233 | #define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x) (((x) & 0x1ff) << 15) | |
234 | ||
235 | /* 0x70 - sdio control register 2 */ | |
236 | #define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT (1 << 0) | |
237 | #define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT (1 << 1) | |
238 | ||
239 | /* 0x74 - sdio status register */ | |
240 | #define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x) (((x) >> 0) & 0x1ffff) | |
241 | #define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x) (((x) >> 17) & 0xef) | |
242 | ||
243 | #endif /* CONFIG_FTSDC010_SDIO */ | |
244 | ||
245 | #endif /* __FTSDC010_H */ |