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1 | /* |
2 | * (C) Copyright 2009 Faraday Technology | |
3 | * Po-Yu Chuang <ratbert@faraday-tech.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | /* | |
21 | * Timer | |
22 | */ | |
23 | #ifndef __FTTMR010_H | |
24 | #define __FTTMR010_H | |
25 | ||
26 | struct fttmr010 { | |
27 | unsigned int timer1_counter; /* 0x00 */ | |
28 | unsigned int timer1_load; /* 0x04 */ | |
29 | unsigned int timer1_match1; /* 0x08 */ | |
30 | unsigned int timer1_match2; /* 0x0c */ | |
31 | unsigned int timer2_counter; /* 0x10 */ | |
32 | unsigned int timer2_load; /* 0x14 */ | |
33 | unsigned int timer2_match1; /* 0x18 */ | |
34 | unsigned int timer2_match2; /* 0x1c */ | |
35 | unsigned int timer3_counter; /* 0x20 */ | |
36 | unsigned int timer3_load; /* 0x24 */ | |
37 | unsigned int timer3_match1; /* 0x28 */ | |
38 | unsigned int timer3_match2; /* 0x2c */ | |
39 | unsigned int cr; /* 0x30 */ | |
40 | unsigned int interrupt_state; /* 0x34 */ | |
41 | unsigned int interrupt_mask; /* 0x38 */ | |
42 | }; | |
43 | ||
44 | /* | |
45 | * Timer Control Register | |
46 | */ | |
47 | #define FTTMR010_TM3_UPDOWN (1 << 11) | |
48 | #define FTTMR010_TM2_UPDOWN (1 << 10) | |
49 | #define FTTMR010_TM1_UPDOWN (1 << 9) | |
50 | #define FTTMR010_TM3_OFENABLE (1 << 8) | |
51 | #define FTTMR010_TM3_CLOCK (1 << 7) | |
52 | #define FTTMR010_TM3_ENABLE (1 << 6) | |
53 | #define FTTMR010_TM2_OFENABLE (1 << 5) | |
54 | #define FTTMR010_TM2_CLOCK (1 << 4) | |
55 | #define FTTMR010_TM2_ENABLE (1 << 3) | |
56 | #define FTTMR010_TM1_OFENABLE (1 << 2) | |
57 | #define FTTMR010_TM1_CLOCK (1 << 1) | |
58 | #define FTTMR010_TM1_ENABLE (1 << 0) | |
59 | ||
60 | /* | |
61 | * Timer Interrupt State & Mask Registers | |
62 | */ | |
63 | #define FTTMR010_TM3_OVERFLOW (1 << 8) | |
64 | #define FTTMR010_TM3_MATCH2 (1 << 7) | |
65 | #define FTTMR010_TM3_MATCH1 (1 << 6) | |
66 | #define FTTMR010_TM2_OVERFLOW (1 << 5) | |
67 | #define FTTMR010_TM2_MATCH2 (1 << 4) | |
68 | #define FTTMR010_TM2_MATCH1 (1 << 3) | |
69 | #define FTTMR010_TM1_OVERFLOW (1 << 2) | |
70 | #define FTTMR010_TM1_MATCH2 (1 << 1) | |
71 | #define FTTMR010_TM1_MATCH1 (1 << 0) | |
72 | ||
73 | #endif /* __FTTMR010_H */ |