[people/ms/u-boot.git] / include / fm_eth.h

/*
 * Copyright 2009-2012 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __FM_ETH_H__
#define __FM_ETH_H__

#include <common.h>
#include <asm/types.h>
#include <asm/fsl_enet.h>

enum fm_port {
	FM1_DTSEC1,
	FM1_DTSEC2,
	FM1_DTSEC3,
	FM1_DTSEC4,
	FM1_DTSEC5,
	FM1_DTSEC6,
	FM1_DTSEC9,
	FM1_DTSEC10,
	FM1_10GEC1,
	FM1_10GEC2,
	FM2_DTSEC1,
	FM2_DTSEC2,
	FM2_DTSEC3,
	FM2_DTSEC4,
	FM2_DTSEC5,
	FM2_DTSEC6,
	FM2_DTSEC9,
	FM2_DTSEC10,
	FM2_10GEC1,
	FM2_10GEC2,
	NUM_FM_PORTS,
};

enum fm_eth_type {
	FM_ETH_1G_E,
	FM_ETH_10G_E,
};

#ifdef CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
#else
#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
#endif

#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"

/* Fman ethernet info struct */
#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
	.fm		= idx,						\
	.phy_regs	= (void *)pregs,				\
	.enet_if	= PHY_INTERFACE_MODE_NONE,			\

#ifdef CONFIG_SYS_FMAN_V3
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_1G_E,					\
	.port		= FM##idx##_DTSEC##n,				\
	.rx_port_id	= RX_PORT_1G_BASE + n - 1,			\
	.tx_port_id	= TX_PORT_1G_BASE + n - 1,			\
	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
				offsetof(struct ccsr_fman, memac[n-1]),\
}

#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_10G_E,					\
	.port		= FM##idx##_10GEC##n,				\
	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
				offsetof(struct ccsr_fman, memac[n-1+8]),\
}
#else
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_1G_E,					\
	.port		= FM##idx##_DTSEC##n,				\
	.rx_port_id	= RX_PORT_1G_BASE + n - 1,			\
	.tx_port_id	= TX_PORT_1G_BASE + n - 1,			\
	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
				offsetof(struct ccsr_fman, mac_1g[n-1]),\
}

#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{									\
	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
	.index		= idx,						\
	.num		= n - 1,					\
	.type		= FM_ETH_10G_E,					\
	.port		= FM##idx##_10GEC##n,				\
	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
				offsetof(struct ccsr_fman, mac_10g[n-1]),\
}
#endif
struct fm_eth_info {
	u8 enabled;
	u8 fm;
	u8 num;
	u8 phy_addr;
	int index;
	u16 rx_port_id;
	u16 tx_port_id;
	enum fm_port port;
	enum fm_eth_type type;
	void *phy_regs;
	phy_interface_t enet_if;
	u32 compat_offset;
	struct mii_dev *bus;
};

struct tgec_mdio_info {
	struct tgec_mdio_controller *regs;
	char *name;
};

struct memac_mdio_info {
	struct memac_mdio_controller *regs;
	char *name;
};

int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);

int fm_standard_init(bd_t *bis);
void fman_enet_init(void);
void fdt_fixup_fman_ethernet(void *fdt);
phy_interface_t fm_info_get_enet_if(enum fm_port port);
void fm_info_set_phy_address(enum fm_port port, int address);
int fm_info_get_phy_address(enum fm_port port);
void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
void fm_disable_port(enum fm_port port);

#endif
Commit	Line	Data
c916d7c9	1	/*
111fd19e	2	* Copyright 2009-2012 Freescale Semiconductor, Inc.
c916d7c9	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
c916d7c9 KG	5	*/
	6
	7	#ifndef __FM_ETH_H__
	8	#define __FM_ETH_H__
	9
	10	#include <common.h>
	11	#include <asm/types.h>
	12	#include <asm/fsl_enet.h>
	13
	14	enum fm_port {
	15	FM1_DTSEC1,
	16	FM1_DTSEC2,
	17	FM1_DTSEC3,
	18	FM1_DTSEC4,
	19	FM1_DTSEC5,
9e758758 YS	20	FM1_DTSEC6,
	21	FM1_DTSEC9,
	22	FM1_DTSEC10,
c916d7c9	23	FM1_10GEC1,
9e758758	24	FM1_10GEC2,
c916d7c9 KG	25	FM2_DTSEC1,
	26	FM2_DTSEC2,
	27	FM2_DTSEC3,
	28	FM2_DTSEC4,
99abf7de	29	FM2_DTSEC5,
9e758758 YS	30	FM2_DTSEC6,
	31	FM2_DTSEC9,
	32	FM2_DTSEC10,
c916d7c9	33	FM2_10GEC1,
9e758758	34	FM2_10GEC2,
c916d7c9 KG	35	NUM_FM_PORTS,
	36	};
	37
	38	enum fm_eth_type {
	39	FM_ETH_1G_E,
	40	FM_ETH_10G_E,
	41	};
	42
111fd19e RZ	43	#ifdef CONFIG_SYS_FMAN_V3
	44	#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
	45	#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
	46	#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
	47	#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
	48	#else
c916d7c9 KG	49	#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
c916d7c9 KG	50	#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
111fd19e	51	#endif
c916d7c9 KG	52
	53	#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
	54	#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
	55
	56	/* Fman ethernet info struct */
	57	#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
	58	.fm = idx, \
	59	.phy_regs = (void *)pregs, \
	60	.enet_if = PHY_INTERFACE_MODE_NONE, \
	61
111fd19e RZ	62	#ifdef CONFIG_SYS_FMAN_V3
	63	#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
	64	{ \
	65	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \
	66	.index = idx, \
	67	.num = n - 1, \
	68	.type = FM_ETH_1G_E, \
	69	.port = FM##idx##_DTSEC##n, \
	70	.rx_port_id = RX_PORT_1G_BASE + n - 1, \
	71	.tx_port_id = TX_PORT_1G_BASE + n - 1, \
	72	.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
	73	offsetof(struct ccsr_fman, memac[n-1]),\
	74	}
	75
	76	#define FM_TGEC_INFO_INITIALIZER(idx, n) \
	77	{ \
944b6ccf	78	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
111fd19e RZ	79	.index = idx, \
	80	.num = n - 1, \
	81	.type = FM_ETH_10G_E, \
	82	.port = FM##idx##_10GEC##n, \
	83	.rx_port_id = RX_PORT_10G_BASE + n - 1, \
	84	.tx_port_id = TX_PORT_10G_BASE + n - 1, \
	85	.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
944b6ccf	86	offsetof(struct ccsr_fman, memac[n-1+8]),\
111fd19e RZ	87	}
111fd19e RZ	88	#else
c916d7c9 KG	89	#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
	90	{ \
	91	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
	92	.index = idx, \
	93	.num = n - 1, \
	94	.type = FM_ETH_1G_E, \
	95	.port = FM##idx##_DTSEC##n, \
	96	.rx_port_id = RX_PORT_1G_BASE + n - 1, \
	97	.tx_port_id = TX_PORT_1G_BASE + n - 1, \
	98	.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
	99	offsetof(struct ccsr_fman, mac_1g[n-1]),\
	100	}
	101
	102	#define FM_TGEC_INFO_INITIALIZER(idx, n) \
	103	{ \
	104	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
	105	.index = idx, \
	106	.num = n - 1, \
	107	.type = FM_ETH_10G_E, \
	108	.port = FM##idx##_10GEC##n, \
	109	.rx_port_id = RX_PORT_10G_BASE + n - 1, \
	110	.tx_port_id = TX_PORT_10G_BASE + n - 1, \
	111	.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
	112	offsetof(struct ccsr_fman, mac_10g[n-1]),\
	113	}
111fd19e	114	#endif
c916d7c9 KG	115	struct fm_eth_info {
	116	u8 enabled;
	117	u8 fm;
	118	u8 num;
	119	u8 phy_addr;
	120	int index;
	121	u16 rx_port_id;
	122	u16 tx_port_id;
	123	enum fm_port port;
	124	enum fm_eth_type type;
	125	void *phy_regs;
	126	phy_interface_t enet_if;
	127	u32 compat_offset;
	128	struct mii_dev *bus;
	129	};
	130
	131	struct tgec_mdio_info {
	132	struct tgec_mdio_controller *regs;
	133	char *name;
	134	};
	135
111fd19e RZ	136	struct memac_mdio_info {
	137	struct memac_mdio_controller *regs;
	138	char *name;
	139	};
	140
c916d7c9	141	int fm_tgec_mdio_init(bd_t bis, struct tgec_mdio_info info);
111fd19e RZ	142	int fm_memac_mdio_init(bd_t bis, struct memac_mdio_info info);
111fd19e RZ	143
c916d7c9 KG	144	int fm_standard_init(bd_t *bis);
	145	void fman_enet_init(void);
	146	void fdt_fixup_fman_ethernet(void *fdt);
	147	phy_interface_t fm_info_get_enet_if(enum fm_port port);
	148	void fm_info_set_phy_address(enum fm_port port, int address);
ae2291fb	149	int fm_info_get_phy_address(enum fm_port port);
c916d7c9	150	void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
69a85242	151	void fm_disable_port(enum fm_port port);
c916d7c9 KG	152
c916d7c9 KG	153	#endif