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024a26bc WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
024a26bc WD |
6 | */ |
7 | ||
53677ef1 | 8 | #include <linux/types.h> /* for ulong typedef */ |
024a26bc WD |
9 | |
10 | #ifndef _FPGA_H_ | |
11 | #define _FPGA_H_ | |
12 | ||
13 | #ifndef CONFIG_MAX_FPGA_DEVICES | |
14 | #define CONFIG_MAX_FPGA_DEVICES 5 | |
15 | #endif | |
16 | ||
024a26bc | 17 | /* fpga_xxxx function return value definitions */ |
53677ef1 WD |
18 | #define FPGA_SUCCESS 0 |
19 | #define FPGA_FAIL -1 | |
024a26bc WD |
20 | |
21 | /* device numbers must be non-negative */ | |
53677ef1 | 22 | #define FPGA_INVALID_DEVICE -1 |
024a26bc WD |
23 | |
24 | /* root data type defintions */ | |
53677ef1 WD |
25 | typedef enum { /* typedef fpga_type */ |
26 | fpga_min_type, /* range check value */ | |
27 | fpga_xilinx, /* Xilinx Family) */ | |
28 | fpga_altera, /* unimplemented */ | |
3b8ac464 | 29 | fpga_lattice, /* Lattice family */ |
53677ef1 WD |
30 | fpga_undefined /* invalid range check value */ |
31 | } fpga_type; /* end, typedef fpga_type */ | |
024a26bc | 32 | |
53677ef1 WD |
33 | typedef struct { /* typedef fpga_desc */ |
34 | fpga_type devtype; /* switch value to select sub-functions */ | |
35 | void *devdesc; /* real device descriptor */ | |
36 | } fpga_desc; /* end, typedef fpga_desc */ | |
024a26bc WD |
37 | |
38 | ||
39 | /* root function definitions */ | |
e6a857da WD |
40 | extern void fpga_init(void); |
41 | extern int fpga_add(fpga_type devtype, void *desc); | |
42 | extern int fpga_count(void); | |
43 | extern int fpga_load(int devnum, const void *buf, size_t bsize); | |
23f4bd75 | 44 | extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size); |
e6a857da WD |
45 | extern int fpga_dump(int devnum, const void *buf, size_t bsize); |
46 | extern int fpga_info(int devnum); | |
6631db47 MS |
47 | extern const fpga_desc *const fpga_validate(int devnum, const void *buf, |
48 | size_t bsize, char *fn); | |
024a26bc WD |
49 | |
50 | #endif /* _FPGA_H_ */ |