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[people/ms/u-boot.git] / include / fpga.h
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1/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
53677ef1 8#include <linux/types.h> /* for ulong typedef */
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9
10#ifndef _FPGA_H_
11#define _FPGA_H_
12
13#ifndef CONFIG_MAX_FPGA_DEVICES
14#define CONFIG_MAX_FPGA_DEVICES 5
15#endif
16
024a26bc 17/* fpga_xxxx function return value definitions */
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18#define FPGA_SUCCESS 0
19#define FPGA_FAIL -1
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20
21/* device numbers must be non-negative */
53677ef1 22#define FPGA_INVALID_DEVICE -1
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23
24/* root data type defintions */
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25typedef enum { /* typedef fpga_type */
26 fpga_min_type, /* range check value */
27 fpga_xilinx, /* Xilinx Family) */
28 fpga_altera, /* unimplemented */
3b8ac464 29 fpga_lattice, /* Lattice family */
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30 fpga_undefined /* invalid range check value */
31} fpga_type; /* end, typedef fpga_type */
024a26bc 32
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33typedef struct { /* typedef fpga_desc */
34 fpga_type devtype; /* switch value to select sub-functions */
35 void *devdesc; /* real device descriptor */
36} fpga_desc; /* end, typedef fpga_desc */
024a26bc 37
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38typedef struct { /* typedef fpga_desc */
39 unsigned int blocksize;
40 char *interface;
41 char *dev_part;
42 char *filename;
43 int fstype;
44} fpga_fs_info;
024a26bc 45
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46typedef enum {
47 BIT_FULL = 0,
67193864 48 BIT_PARTIAL,
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49} bitstream_type;
50
024a26bc 51/* root function definitions */
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52void fpga_init(void);
53int fpga_add(fpga_type devtype, void *desc);
54int fpga_count(void);
ebd322de 55const fpga_desc *const fpga_get_desc(int devnum);
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56int fpga_load(int devnum, const void *buf, size_t bsize,
57 bitstream_type bstype);
58int fpga_fsload(int devnum, const void *buf, size_t size,
59 fpga_fs_info *fpga_fsinfo);
60int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
61 bitstream_type bstype);
62int fpga_dump(int devnum, const void *buf, size_t bsize);
63int fpga_info(int devnum);
64const fpga_desc *const fpga_validate(int devnum, const void *buf,
65 size_t bsize, char *fn);
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66
67#endif /* _FPGA_H_ */