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58e5e9af | 1 | /* |
34e026f9 | 2 | * Copyright 2008-2014 Freescale Semiconductor, Inc. |
58e5e9af KG |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * Version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef FSL_DDR_MAIN_H | |
10 | #define FSL_DDR_MAIN_H | |
11 | ||
34e026f9 | 12 | #include <fsl_ddrc_version.h> |
5614e71b YS |
13 | #include <fsl_ddr_sdram.h> |
14 | #include <fsl_ddr_dimm_params.h> | |
58e5e9af | 15 | |
5614e71b | 16 | #include <common_timing_params.h> |
58e5e9af | 17 | |
1d71efbb YS |
18 | #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS |
19 | /* All controllers are for main memory */ | |
20 | #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS | |
21 | #endif | |
22 | ||
4e5b1bd0 YS |
23 | #ifdef CONFIG_SYS_FSL_DDR_LE |
24 | #define ddr_in32(a) in_le32(a) | |
25 | #define ddr_out32(a, v) out_le32(a, v) | |
dda3b610 YS |
26 | #define ddr_setbits32(a, v) setbits_le32(a, v) |
27 | #define ddr_clrbits32(a, v) clrbits_le32(a, v) | |
28 | #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) | |
4e5b1bd0 YS |
29 | #else |
30 | #define ddr_in32(a) in_be32(a) | |
31 | #define ddr_out32(a, v) out_be32(a, v) | |
dda3b610 YS |
32 | #define ddr_setbits32(a, v) setbits_be32(a, v) |
33 | #define ddr_clrbits32(a, v) clrbits_be32(a, v) | |
34 | #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) | |
4e5b1bd0 YS |
35 | #endif |
36 | ||
66869f95 | 37 | u32 fsl_ddr_get_version(unsigned int ctrl_num); |
34e026f9 | 38 | |
1b3e3c4f | 39 | #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) |
58e5e9af KG |
40 | /* |
41 | * Bind the main DDR setup driver's generic names | |
42 | * to this specific DDR technology. | |
43 | */ | |
44 | static __inline__ int | |
03e664d8 YS |
45 | compute_dimm_parameters(const unsigned int ctrl_num, |
46 | const generic_spd_eeprom_t *spd, | |
58e5e9af KG |
47 | dimm_params_t *pdimm, |
48 | unsigned int dimm_number) | |
49 | { | |
03e664d8 | 50 | return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number); |
58e5e9af | 51 | } |
1b3e3c4f | 52 | #endif |
58e5e9af KG |
53 | |
54 | /* | |
55 | * Data Structures | |
56 | * | |
57 | * All data structures have to be on the stack | |
58 | */ | |
6d0f6bcf JCPV |
59 | #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS |
60 | #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR | |
58e5e9af KG |
61 | |
62 | typedef struct { | |
63 | generic_spd_eeprom_t | |
6d0f6bcf | 64 | spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; |
58e5e9af | 65 | struct dimm_params_s |
6d0f6bcf JCPV |
66 | dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; |
67 | memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; | |
68 | common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; | |
69 | fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; | |
1d71efbb YS |
70 | unsigned int first_ctrl; |
71 | unsigned int num_ctrls; | |
72 | unsigned long long mem_base; | |
73 | unsigned int dimm_slots_per_ctrl; | |
74 | int (*board_need_mem_reset)(void); | |
75 | void (*board_mem_reset)(void); | |
76 | void (*board_mem_de_reset)(void); | |
58e5e9af KG |
77 | } fsl_ddr_info_t; |
78 | ||
79 | /* Compute steps */ | |
80 | #define STEP_GET_SPD (1 << 0) | |
81 | #define STEP_COMPUTE_DIMM_PARMS (1 << 1) | |
82 | #define STEP_COMPUTE_COMMON_PARMS (1 << 2) | |
83 | #define STEP_GATHER_OPTS (1 << 3) | |
84 | #define STEP_ASSIGN_ADDRESSES (1 << 4) | |
85 | #define STEP_COMPUTE_REGS (1 << 5) | |
86 | #define STEP_PROGRAM_REGS (1 << 6) | |
87 | #define STEP_ALL 0xFFF | |
88 | ||
6f5e1dc5 | 89 | unsigned long long |
fc0c2b6f HW |
90 | fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
91 | unsigned int size_only); | |
6f5e1dc5 | 92 | const char *step_to_string(unsigned int step); |
58e5e9af | 93 | |
03e664d8 YS |
94 | unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num, |
95 | const memctl_options_t *popts, | |
58e5e9af KG |
96 | fsl_ddr_cfg_regs_t *ddr, |
97 | const common_timing_params_t *common_dimm, | |
98 | const dimm_params_t *dimm_parameters, | |
fc0c2b6f HW |
99 | unsigned int dbw_capacity_adjust, |
100 | unsigned int size_only); | |
6f5e1dc5 | 101 | unsigned int compute_lowest_common_dimm_parameters( |
03e664d8 | 102 | const unsigned int ctrl_num, |
6f5e1dc5 YS |
103 | const dimm_params_t *dimm_params, |
104 | common_timing_params_t *outpdimm, | |
105 | unsigned int number_of_dimms); | |
56848428 | 106 | unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, |
58e5e9af | 107 | memctl_options_t *popts, |
dfb49108 | 108 | dimm_params_t *pdimm, |
58e5e9af | 109 | unsigned int ctrl_num); |
6f5e1dc5 | 110 | void check_interleaving_options(fsl_ddr_info_t *pinfo); |
58e5e9af | 111 | |
03e664d8 YS |
112 | unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk); |
113 | unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num); | |
114 | unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos); | |
6f5e1dc5 YS |
115 | void fsl_ddr_set_lawbar( |
116 | const common_timing_params_t *memctl_common_params, | |
117 | unsigned int memctl_interleaved, | |
118 | unsigned int ctrl_num); | |
e32d59a2 YS |
119 | void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, |
120 | unsigned int last_ctrl); | |
6f5e1dc5 | 121 | |
e8ba6c50 JY |
122 | int fsl_ddr_interactive_env_var_exists(void); |
123 | unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); | |
6f5e1dc5 | 124 | void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
1d71efbb | 125 | unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); |
6f5e1dc5 YS |
126 | |
127 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); | |
128 | unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); | |
4e5b1bd0 | 129 | void board_add_ram_info(int use_default); |
6f5e1dc5 YS |
130 | |
131 | /* processor specific function */ | |
132 | void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, | |
c63e1370 | 133 | unsigned int ctrl_num, int step); |
1b3e3c4f YS |
134 | |
135 | /* board specific function */ | |
136 | int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, | |
137 | unsigned int controller_number, | |
138 | unsigned int dimm_number); | |
b92557cd YS |
139 | void update_spd_address(unsigned int ctrl_num, |
140 | unsigned int slot, | |
141 | unsigned int *addr); | |
58e5e9af | 142 | #endif |