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58e5e9af KG |
1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * Version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef DDR2_DIMM_PARAMS_H | |
10 | #define DDR2_DIMM_PARAMS_H | |
11 | ||
08b3f759 YS |
12 | #define EDC_DATA_PARITY 1 |
13 | #define EDC_ECC 2 | |
14 | #define EDC_AC_PARITY 4 | |
15 | ||
58e5e9af KG |
16 | /* Parameters for a DDR2 dimm computed from the SPD */ |
17 | typedef struct dimm_params_s { | |
18 | ||
19 | /* DIMM organization parameters */ | |
20 | char mpart[19]; /* guaranteed null terminated */ | |
21 | ||
22 | unsigned int n_ranks; | |
23 | unsigned long long rank_density; | |
24 | unsigned long long capacity; | |
25 | unsigned int data_width; | |
26 | unsigned int primary_sdram_width; | |
27 | unsigned int ec_sdram_width; | |
28 | unsigned int registered_dimm; | |
b61e0615 | 29 | unsigned int device_width; /* x4, x8, x16 components */ |
58e5e9af KG |
30 | |
31 | /* SDRAM device parameters */ | |
32 | unsigned int n_row_addr; | |
33 | unsigned int n_col_addr; | |
34 | unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ | |
35 | unsigned int n_banks_per_sdram_device; | |
36 | unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ | |
37 | unsigned int row_density; | |
38 | ||
39 | /* used in computing base address of DIMMs */ | |
40 | unsigned long long base_address; | |
c360ceac DL |
41 | /* mirrored DIMMs */ |
42 | unsigned int mirrored_dimm; /* only for ddr3 */ | |
58e5e9af KG |
43 | |
44 | /* DIMM timing parameters */ | |
45 | ||
c360ceac | 46 | unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ |
73b5396b | 47 | unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ |
0dd38a35 PJ |
48 | unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */ |
49 | unsigned int tfaw_ps; /* four active window delay, only for ddr3 */ | |
c360ceac | 50 | |
58e5e9af KG |
51 | /* |
52 | * SDRAM clock periods | |
53 | * The range for these are 1000-10000 so a short should be sufficient | |
54 | */ | |
0dd38a35 PJ |
55 | unsigned int tckmin_x_ps; |
56 | unsigned int tckmin_x_minus_1_ps; | |
57 | unsigned int tckmin_x_minus_2_ps; | |
58 | unsigned int tckmax_ps; | |
58e5e9af KG |
59 | |
60 | /* SPD-defined CAS latencies */ | |
0dd38a35 PJ |
61 | unsigned int caslat_x; |
62 | unsigned int caslat_x_minus_1; | |
63 | unsigned int caslat_x_minus_2; | |
58e5e9af KG |
64 | |
65 | unsigned int caslat_lowest_derated; /* Derated CAS latency */ | |
66 | ||
67 | /* basic timing parameters */ | |
0dd38a35 PJ |
68 | unsigned int trcd_ps; |
69 | unsigned int trp_ps; | |
70 | unsigned int tras_ps; | |
58e5e9af | 71 | |
0dd38a35 PJ |
72 | unsigned int twr_ps; /* maximum = 63750 ps */ |
73 | unsigned int twtr_ps; /* maximum = 63750 ps */ | |
74 | unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns | |
58e5e9af KG |
75 | = 511750 ps */ |
76 | ||
0dd38a35 PJ |
77 | unsigned int trrd_ps; /* maximum = 63750 ps */ |
78 | unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ | |
58e5e9af KG |
79 | |
80 | unsigned int refresh_rate_ps; | |
7e157b0a | 81 | unsigned int extended_op_srt; |
58e5e9af | 82 | |
c360ceac | 83 | /* DDR3 doesn't need these as below */ |
0dd38a35 PJ |
84 | unsigned int tis_ps; /* byte 32, spd->ca_setup */ |
85 | unsigned int tih_ps; /* byte 33, spd->ca_hold */ | |
86 | unsigned int tds_ps; /* byte 34, spd->data_setup */ | |
87 | unsigned int tdh_ps; /* byte 35, spd->data_hold */ | |
88 | unsigned int trtp_ps; /* byte 38, spd->trtp */ | |
89 | unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ | |
90 | unsigned int tqhs_ps; /* byte 45, spd->tqhs */ | |
9490ff48 YS |
91 | |
92 | /* DDR3 RDIMM */ | |
93 | unsigned char rcw[16]; /* Register Control Word 0-15 */ | |
58e5e9af KG |
94 | } dimm_params_t; |
95 | ||
96 | extern unsigned int ddr_compute_dimm_parameters( | |
97 | const generic_spd_eeprom_t *spd, | |
98 | dimm_params_t *pdimm, | |
99 | unsigned int dimm_number); | |
100 | ||
101 | #endif |