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58e5e9af 1/*
34e026f9 2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
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3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#ifndef FSL_DDR_MEMCTL_H
10#define FSL_DDR_MEMCTL_H
11
12/*
13 * Pick a basic DDR Technology.
14 */
15#include <ddr_spd.h>
34e026f9 16#include <fsl_ddrc_version.h>
58e5e9af 17
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18#define SDRAM_TYPE_DDR1 2
19#define SDRAM_TYPE_DDR2 3
20#define SDRAM_TYPE_LPDDR1 6
21#define SDRAM_TYPE_DDR3 7
22#define SDRAM_TYPE_DDR4 5
58e5e9af 23
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24#define DDR_BL4 4 /* burst length 4 */
25#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
26#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
27#define DDR_BL8 8 /* burst length 8 */
28
e1fd16b6 29#define DDR3_RTT_OFF 0
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30#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
31#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
32#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
33#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
34#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
35
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36#define DDR2_RTT_OFF 0
37#define DDR2_RTT_75_OHM 1
38#define DDR2_RTT_150_OHM 2
39#define DDR2_RTT_50_OHM 3
40
5614e71b 41#if defined(CONFIG_SYS_FSL_DDR1)
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42#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
43typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
44#ifndef CONFIG_FSL_SDRAM_TYPE
45#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
46#endif
5614e71b 47#elif defined(CONFIG_SYS_FSL_DDR2)
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48#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
49typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
50#ifndef CONFIG_FSL_SDRAM_TYPE
51#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
52#endif
5614e71b 53#elif defined(CONFIG_SYS_FSL_DDR3)
58e5e9af 54typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
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55#ifndef CONFIG_FSL_SDRAM_TYPE
56#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
58e5e9af 57#endif
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58#elif defined(CONFIG_SYS_FSL_DDR4)
59#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
60typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
61#ifndef CONFIG_FSL_SDRAM_TYPE
62#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
63#endif
5614e71b 64#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
58e5e9af 65
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66#define FSL_DDR_ODT_NEVER 0x0
67#define FSL_DDR_ODT_CS 0x1
68#define FSL_DDR_ODT_ALL_OTHER_CS 0x2
69#define FSL_DDR_ODT_OTHER_DIMM 0x3
70#define FSL_DDR_ODT_ALL 0x4
71#define FSL_DDR_ODT_SAME_DIMM 0x5
72#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
73#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
74
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75/* define bank(chip select) interleaving mode */
76#define FSL_DDR_CS0_CS1 0x40
77#define FSL_DDR_CS2_CS3 0x20
78#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
79#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
80
81/* define memory controller interleaving mode */
82#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
83#define FSL_DDR_PAGE_INTERLEAVING 0x1
84#define FSL_DDR_BANK_INTERLEAVING 0x2
85#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
6b1e1254 86#define FSL_DDR_256B_INTERLEAVING 0x8
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87#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
88#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
89#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
90/* placeholder for 4-way interleaving */
91#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
92#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
93#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
dbbbb3ab 94
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95#define SDRAM_CS_CONFIG_EN 0x80000000
96
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97/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
98 */
99#define SDRAM_CFG_MEM_EN 0x80000000
100#define SDRAM_CFG_SREN 0x40000000
101#define SDRAM_CFG_ECC_EN 0x20000000
102#define SDRAM_CFG_RD_EN 0x10000000
103#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
104#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
105#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
106#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
107#define SDRAM_CFG_DYN_PWR 0x00200000
9c6b47d5 108#define SDRAM_CFG_DBW_MASK 0x00180000
f31cfd19 109#define SDRAM_CFG_DBW_SHIFT 19
e1be0d25 110#define SDRAM_CFG_32_BE 0x00080000
0b3b1766 111#define SDRAM_CFG_16_BE 0x00100000
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112#define SDRAM_CFG_8_BE 0x00040000
113#define SDRAM_CFG_NCAP 0x00020000
114#define SDRAM_CFG_2T_EN 0x00008000
115#define SDRAM_CFG_BI 0x00000001
116
a7787b78 117#define SDRAM_CFG2_FRC_SR 0x80000000
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118#define SDRAM_CFG2_D_INIT 0x00000010
119#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
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120#define SDRAM_CFG2_ODT_NEVER 0
121#define SDRAM_CFG2_ODT_ONLY_WRITE 1
122#define SDRAM_CFG2_ODT_ONLY_READ 2
123#define SDRAM_CFG2_ODT_ALWAYS 3
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124
125#define TIMING_CFG_2_CPO_MASK 0x0F800000
126
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127#if defined(CONFIG_SYS_FSL_DDR_VER) && \
128 (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
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129#define RD_TO_PRE_MASK 0xf
130#define RD_TO_PRE_SHIFT 13
131#define WR_DATA_DELAY_MASK 0xf
132#define WR_DATA_DELAY_SHIFT 9
133#else
134#define RD_TO_PRE_MASK 0x7
135#define RD_TO_PRE_SHIFT 13
136#define WR_DATA_DELAY_MASK 0x7
137#define WR_DATA_DELAY_SHIFT 10
138#endif
139
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140/* DDR_MD_CNTL */
141#define MD_CNTL_MD_EN 0x80000000
142#define MD_CNTL_CS_SEL_CS0 0x00000000
143#define MD_CNTL_CS_SEL_CS1 0x10000000
144#define MD_CNTL_CS_SEL_CS2 0x20000000
145#define MD_CNTL_CS_SEL_CS3 0x30000000
146#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
147#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
148#define MD_CNTL_MD_SEL_MR 0x00000000
149#define MD_CNTL_MD_SEL_EMR 0x01000000
150#define MD_CNTL_MD_SEL_EMR2 0x02000000
151#define MD_CNTL_MD_SEL_EMR3 0x03000000
152#define MD_CNTL_SET_REF 0x00800000
153#define MD_CNTL_SET_PRE 0x00400000
154#define MD_CNTL_CKE_CNTL_LOW 0x00100000
155#define MD_CNTL_CKE_CNTL_HIGH 0x00200000
156#define MD_CNTL_WRCW 0x00080000
157#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
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158#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
159#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
fa8d23c0 160
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161/* DDR_CDR1 */
162#define DDR_CDR1_DHC_EN 0x80000000
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163#define DDR_CDR1_ODT_SHIFT 17
164#define DDR_CDR1_ODT_MASK 0x6
165#define DDR_CDR2_ODT_MASK 0x1
166#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
167#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
34e026f9 168#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
a7787b78 169#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
7288c2c2 170#define DDR_CDR2_VREF_RANGE_2 0x00000040
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171
172#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
173 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
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174#ifdef CONFIG_SYS_FSL_DDR3L
175#define DDR_CDR_ODT_OFF 0x0
176#define DDR_CDR_ODT_120ohm 0x1
177#define DDR_CDR_ODT_200ohm 0x2
178#define DDR_CDR_ODT_75ohm 0x3
179#define DDR_CDR_ODT_60ohm 0x5
180#define DDR_CDR_ODT_46ohm 0x7
181#elif defined(CONFIG_SYS_FSL_DDR4)
182#define DDR_CDR_ODT_OFF 0x0
183#define DDR_CDR_ODT_100ohm 0x1
184#define DDR_CDR_ODT_120OHM 0x2
185#define DDR_CDR_ODT_80ohm 0x3
186#define DDR_CDR_ODT_60ohm 0x4
187#define DDR_CDR_ODT_40ohm 0x5
188#define DDR_CDR_ODT_50ohm 0x6
189#define DDR_CDR_ODT_30ohm 0x7
190#else
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191#define DDR_CDR_ODT_OFF 0x0
192#define DDR_CDR_ODT_120ohm 0x1
193#define DDR_CDR_ODT_180ohm 0x2
194#define DDR_CDR_ODT_75ohm 0x3
195#define DDR_CDR_ODT_110ohm 0x4
196#define DDR_CDR_ODT_60hm 0x5
197#define DDR_CDR_ODT_70ohm 0x6
198#define DDR_CDR_ODT_47ohm 0x7
34e026f9 199#endif /* DDR3L */
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200#else
201#define DDR_CDR_ODT_75ohm 0x0
202#define DDR_CDR_ODT_55ohm 0x1
203#define DDR_CDR_ODT_60ohm 0x2
204#define DDR_CDR_ODT_50ohm 0x3
205#define DDR_CDR_ODT_150ohm 0x4
206#define DDR_CDR_ODT_43ohm 0x5
207#define DDR_CDR_ODT_120ohm 0x6
208#endif
6b06d7dc 209
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210#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
211
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212/* Record of register values computed */
213typedef struct fsl_ddr_cfg_regs_s {
214 struct {
215 unsigned int bnds;
216 unsigned int config;
217 unsigned int config_2;
218 } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
219 unsigned int timing_cfg_3;
220 unsigned int timing_cfg_0;
221 unsigned int timing_cfg_1;
222 unsigned int timing_cfg_2;
223 unsigned int ddr_sdram_cfg;
224 unsigned int ddr_sdram_cfg_2;
34e026f9 225 unsigned int ddr_sdram_cfg_3;
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226 unsigned int ddr_sdram_mode;
227 unsigned int ddr_sdram_mode_2;
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228 unsigned int ddr_sdram_mode_3;
229 unsigned int ddr_sdram_mode_4;
230 unsigned int ddr_sdram_mode_5;
231 unsigned int ddr_sdram_mode_6;
232 unsigned int ddr_sdram_mode_7;
233 unsigned int ddr_sdram_mode_8;
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234 unsigned int ddr_sdram_mode_9;
235 unsigned int ddr_sdram_mode_10;
236 unsigned int ddr_sdram_mode_11;
237 unsigned int ddr_sdram_mode_12;
238 unsigned int ddr_sdram_mode_13;
239 unsigned int ddr_sdram_mode_14;
240 unsigned int ddr_sdram_mode_15;
241 unsigned int ddr_sdram_mode_16;
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242 unsigned int ddr_sdram_md_cntl;
243 unsigned int ddr_sdram_interval;
244 unsigned int ddr_data_init;
245 unsigned int ddr_sdram_clk_cntl;
246 unsigned int ddr_init_addr;
247 unsigned int ddr_init_ext_addr;
248 unsigned int timing_cfg_4;
249 unsigned int timing_cfg_5;
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250 unsigned int timing_cfg_6;
251 unsigned int timing_cfg_7;
252 unsigned int timing_cfg_8;
253 unsigned int timing_cfg_9;
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254 unsigned int ddr_zq_cntl;
255 unsigned int ddr_wrlvl_cntl;
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256 unsigned int ddr_wrlvl_cntl_2;
257 unsigned int ddr_wrlvl_cntl_3;
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258 unsigned int ddr_sr_cntr;
259 unsigned int ddr_sdram_rcw_1;
260 unsigned int ddr_sdram_rcw_2;
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261 unsigned int ddr_sdram_rcw_3;
262 unsigned int ddr_sdram_rcw_4;
263 unsigned int ddr_sdram_rcw_5;
264 unsigned int ddr_sdram_rcw_6;
265 unsigned int dq_map_0;
266 unsigned int dq_map_1;
267 unsigned int dq_map_2;
268 unsigned int dq_map_3;
7fd101c9 269 unsigned int ddr_eor;
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270 unsigned int ddr_cdr1;
271 unsigned int ddr_cdr2;
272 unsigned int err_disable;
273 unsigned int err_int_en;
274 unsigned int debug[32];
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275} fsl_ddr_cfg_regs_t;
276
277typedef struct memctl_options_partial_s {
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278 unsigned int all_dimms_ecc_capable;
279 unsigned int all_dimms_tckmax_ps;
280 unsigned int all_dimms_burst_lengths_bitmask;
281 unsigned int all_dimms_registered;
282 unsigned int all_dimms_unbuffered;
34e026f9 283 /* unsigned int lowest_common_spd_caslat; */
0dd38a35 284 unsigned int all_dimms_minimum_trcd_ps;
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285} memctl_options_partial_t;
286
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287#define DDR_DATA_BUS_WIDTH_64 0
288#define DDR_DATA_BUS_WIDTH_32 1
289#define DDR_DATA_BUS_WIDTH_16 2
ef87cab6 290#define DDR_CSWL_CS0 0x04000001
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291/*
292 * Generalized parameters for memory controller configuration,
293 * might be a little specific to the FSL memory controller
294 */
295typedef struct memctl_options_s {
296 /*
297 * Memory organization parameters
298 *
299 * if DIMM is present in the system
300 * where DIMMs are with respect to chip select
301 * where chip selects are with respect to memory boundaries
302 */
303 unsigned int registered_dimm_en; /* use registered DIMM support */
304
305 /* Options local to a Chip Select */
306 struct cs_local_opts_s {
307 unsigned int auto_precharge;
308 unsigned int odt_rd_cfg;
309 unsigned int odt_wr_cfg;
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310 unsigned int odt_rtt_norm;
311 unsigned int odt_rtt_wr;
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312 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
313
314 /* Special configurations for chip select */
315 unsigned int memctl_interleaving;
316 unsigned int memctl_interleaving_mode;
317 unsigned int ba_intlv_ctl;
7fd101c9 318 unsigned int addr_hash;
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319
320 /* Operational mode parameters */
0dd38a35 321 unsigned int ecc_mode; /* Use ECC? */
58e5e9af 322 /* Initialize ECC using memory controller? */
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323 unsigned int ecc_init_using_memctl;
324 unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
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325 /* SREN - self-refresh during sleep */
326 unsigned int self_refresh_in_sleep;
327 unsigned int dynamic_power; /* DYN_PWR */
328 /* memory data width to use (16-bit, 32-bit, 64-bit) */
329 unsigned int data_bus_width;
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330 unsigned int burst_length; /* BL4, OTF and BL8 */
331 /* On-The-Fly Burst Chop enable */
0dd38a35 332 unsigned int otf_burst_chop_en;
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333 /* mirrior DIMMs for DDR3 */
334 unsigned int mirrored_dimm;
5800e7ab 335 unsigned int quad_rank_present;
d2a9568c 336 unsigned int ap_en; /* address parity enable for RDIMM */
b61e0615 337 unsigned int x4_en; /* enable x4 devices */
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338
339 /* Global Timing Parameters */
340 unsigned int cas_latency_override;
341 unsigned int cas_latency_override_value;
342 unsigned int use_derated_caslat;
343 unsigned int additive_latency_override;
344 unsigned int additive_latency_override_value;
345
346 unsigned int clk_adjust; /* */
347 unsigned int cpo_override;
348 unsigned int write_data_delay; /* DQS adjust */
bdc9f7b5 349
ef87cab6 350 unsigned int cswl_override;
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351 unsigned int wrlvl_override;
352 unsigned int wrlvl_sample; /* Write leveling */
353 unsigned int wrlvl_start;
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354 unsigned int wrlvl_ctl_2;
355 unsigned int wrlvl_ctl_3;
bdc9f7b5 356
58e5e9af 357 unsigned int half_strength_driver_enable;
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358 unsigned int twot_en;
359 unsigned int threet_en;
58e5e9af 360 unsigned int bstopre;
0dd38a35 361 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
22cca7e1 362
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363 /* Rtt impedance */
364 unsigned int rtt_override; /* rtt_override enable */
365 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
1aa3d08a 366 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
c360ceac 367
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368 /* Automatic self refresh */
369 unsigned int auto_self_refresh_en;
370 unsigned int sr_it;
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371 /* ZQ calibration */
372 unsigned int zq_en;
373 /* Write leveling */
374 unsigned int wrlvl_en;
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375 /* RCW override for RDIMM */
376 unsigned int rcw_override;
377 unsigned int rcw_1;
378 unsigned int rcw_2;
379 /* control register 1 */
380 unsigned int ddr_cdr1;
57495e4e 381 unsigned int ddr_cdr2;
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382
383 unsigned int trwt_override;
384 unsigned int trwt; /* read-to-write turnaround */
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385} memctl_options_t;
386
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387phys_size_t fsl_ddr_sdram(void);
388phys_size_t fsl_ddr_sdram_size(void);
389phys_size_t fsl_other_ddr_sdram(unsigned long long base,
390 unsigned int first_ctrl,
391 unsigned int num_ctrls,
392 unsigned int dimm_slots_per_ctrl,
393 int (*board_need_reset)(void),
394 void (*board_reset)(void),
395 void (*board_de_reset)(void));
3dbd5d7d 396extern int fsl_use_spd(void);
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397void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
398 unsigned int ctrl_num, int step);
f31cfd19 399u32 fsl_ddr_get_intl3r(void);
1d71efbb 400void print_ddr_info(unsigned int start_ctrl);
28a96671 401
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402static void __board_assert_mem_reset(void)
403{
404}
405
406static void __board_deassert_mem_reset(void)
407{
408}
409
410void board_assert_mem_reset(void)
411 __attribute__((weak, alias("__board_assert_mem_reset")));
412
413void board_deassert_mem_reset(void)
414 __attribute__((weak, alias("__board_deassert_mem_reset")));
415
416static int __board_need_mem_reset(void)
417{
418 return 0;
419}
420
421int board_need_mem_reset(void)
422 __attribute__((weak, alias("__board_need_mem_reset")));
423
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424#if defined(CONFIG_DEEP_SLEEP)
425void board_mem_sleep_setup(void);
426bool is_warm_boot(void);
427int fsl_dp_resume(void);
428#endif
aade2004 429
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430/*
431 * The 85xx boards have a common prototype for fixed_sdram so put the
432 * declaration here.
433 */
434#ifdef CONFIG_MPC85xx
435extern phys_size_t fixed_sdram(void);
436#endif
437
438#if defined(CONFIG_DDR_ECC)
439extern void ddr_enable_ecc(unsigned int dram_size);
440#endif
441
442
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443typedef struct fixed_ddr_parm{
444 int min_freq;
445 int max_freq;
446 fsl_ddr_cfg_regs_t *ddr_settings;
447} fixed_ddr_parm_t;
58e5e9af 448#endif