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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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2 | /* |
3 | * Copyright 2016 Freescale Semiconductor, Inc. | |
4 | * | |
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5 | */ |
6 | ||
c32449a1 GB |
7 | #if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \ |
8 | defined(CONFIG_ARCH_IMXRT) | |
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9 | struct lpuart_fsl_reg32 { |
10 | u32 verid; | |
11 | u32 param; | |
12 | u32 global; | |
13 | u32 pincfg; | |
14 | u32 baud; | |
15 | u32 stat; | |
16 | u32 ctrl; | |
17 | u32 data; | |
18 | u32 match; | |
19 | u32 modir; | |
20 | u32 fifo; | |
21 | u32 water; | |
22 | }; | |
23 | #else | |
24 | struct lpuart_fsl_reg32 { | |
25 | u32 baud; | |
26 | u32 stat; | |
27 | u32 ctrl; | |
28 | u32 data; | |
29 | u32 match; | |
30 | u32 modir; | |
31 | u32 fifo; | |
32 | u32 water; | |
33 | }; | |
34 | #endif | |
35 | ||
36 | struct lpuart_fsl { | |
37 | u8 ubdh; | |
38 | u8 ubdl; | |
39 | u8 uc1; | |
40 | u8 uc2; | |
41 | u8 us1; | |
42 | u8 us2; | |
43 | u8 uc3; | |
44 | u8 ud; | |
45 | u8 uma1; | |
46 | u8 uma2; | |
47 | u8 uc4; | |
48 | u8 uc5; | |
49 | u8 ued; | |
50 | u8 umodem; | |
51 | u8 uir; | |
52 | u8 reserved; | |
53 | u8 upfifo; | |
54 | u8 ucfifo; | |
55 | u8 usfifo; | |
56 | u8 utwfifo; | |
57 | u8 utcfifo; | |
58 | u8 urwfifo; | |
59 | u8 urcfifo; | |
60 | u8 rsvd[28]; | |
61 | }; | |
62 | ||
63 | /* Used on i.MX7ULP */ | |
64 | #define LPUART_BAUD_BOTHEDGE_MASK (0x20000) | |
65 | #define LPUART_BAUD_OSR_MASK (0x1F000000) | |
66 | #define LPUART_BAUD_OSR_SHIFT (24) | |
67 | #define LPUART_BAUD_OSR(x) ((((uint32_t)(x)) << 24) & 0x1F000000) | |
68 | #define LPUART_BAUD_SBR_MASK (0x1FFF) | |
69 | #define LPUART_BAUD_SBR_SHIFT (0U) | |
70 | #define LPUART_BAUD_SBR(x) (((uint32_t)(x)) & 0x1FFF) | |
71 | #define LPUART_BAUD_M10_MASK (0x20000000U) | |
72 | #define LPUART_BAUD_SBNS_MASK (0x2000U) |