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063c1263 | 1 | /* |
5be00a01 | 2 | * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc. |
063c1263 AF |
3 | * Jun-jie Zhang <b18070@freescale.com> |
4 | * Mingkai Hu <Mingkai.hu@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
063c1263 AF |
7 | */ |
8 | #ifndef __FSL_PHY_H__ | |
9 | #define __FSL_PHY_H__ | |
10 | ||
11 | #include <net.h> | |
12 | #include <miiphy.h> | |
93f26f13 CM |
13 | |
14 | struct tsec_mii_mng { | |
15 | u32 miimcfg; /* MII management configuration reg */ | |
16 | u32 miimcom; /* MII management command reg */ | |
17 | u32 miimadd; /* MII management address reg */ | |
18 | u32 miimcon; /* MII management control reg */ | |
19 | u32 miimstat; /* MII management status reg */ | |
20 | u32 miimind; /* MII management indication reg */ | |
21 | u32 ifstat; /* Interface Status Register */ | |
22 | }; | |
23 | ||
24 | int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); | |
063c1263 AF |
25 | |
26 | /* PHY register offsets */ | |
27 | #define PHY_EXT_PAGE_ACCESS 0x1f | |
28 | ||
29 | /* MII Management Configuration Register */ | |
30 | #define MIIMCFG_RESET_MGMT 0x80000000 | |
31 | #define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 | |
32 | #define MIIMCFG_INIT_VALUE 0x00000003 | |
33 | ||
34 | /* MII Management Command Register */ | |
35 | #define MIIMCOM_READ_CYCLE 0x00000001 | |
36 | #define MIIMCOM_SCAN_CYCLE 0x00000002 | |
37 | ||
38 | /* MII Management Address Register */ | |
39 | #define MIIMADD_PHY_ADDR_SHIFT 8 | |
40 | ||
41 | /* MII Management Indicator Register */ | |
42 | #define MIIMIND_BUSY 0x00000001 | |
43 | #define MIIMIND_NOTVALID 0x00000004 | |
44 | ||
5be00a01 | 45 | void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, |
063c1263 | 46 | int dev_addr, int reg, int value); |
5be00a01 | 47 | int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, |
063c1263 AF |
48 | int dev_addr, int regnum); |
49 | int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); | |
50 | int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, | |
51 | u16 value); | |
111fd19e RZ |
52 | int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, |
53 | int regnum, u16 value); | |
54 | int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, | |
55 | int regnum); | |
063c1263 AF |
56 | |
57 | struct fsl_pq_mdio_info { | |
5be00a01 | 58 | struct tsec_mii_mng __iomem *regs; |
063c1263 AF |
59 | char *name; |
60 | }; | |
61 | int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info); | |
62 | ||
63 | #endif /* __FSL_PHY_H__ */ |