[people/ms/u-boot.git] / include / fsl_nfc.h

/*
 * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __FSL_NFC_H
#define __FSL_NFC_H

/*
 * Register map and bit definitions for the Freescale NAND Flash Controller
 * present in various i.MX devices.
 *
 * MX31 and MX27 have version 1, which has:
 *	4 512-byte main buffers and
 *	4 16-byte spare buffers
 *	to support up to 2K byte pagesize nand.
 *	Reading or writing a 2K page requires 4 FDI/FDO cycles.
 *
 * MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which
 * have:
 *	8 512-byte main buffers and
 *	8 64-byte spare buffers
 *	to support up to 4K byte pagesize nand.
 *	Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
 *	Also some of registers are moved and/or changed meaning as seen below.
 */
#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
#define MXC_NFC_V1
#define is_mxc_nfc_1()		1
#define is_mxc_nfc_21()		0
#define is_mxc_nfc_32()		0
#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
#define MXC_NFC_V2_1
#define is_mxc_nfc_1()		0
#define is_mxc_nfc_21()		1
#define is_mxc_nfc_32()		0
#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
#define MXC_NFC_V3
#define MXC_NFC_V3_2
#define is_mxc_nfc_1()		0
#define is_mxc_nfc_21()		0
#define is_mxc_nfc_32()		1
#else
#error "MXC NFC implementation not supported"
#endif
#define is_mxc_nfc_3()		is_mxc_nfc_32()

#if defined(MXC_NFC_V1)
#define NAND_MXC_NR_BUFS		4
#define NAND_MXC_SPARE_BUF_SIZE		16
#define NAND_MXC_REG_OFFSET		0xe00
#define NAND_MXC_2K_MULTI_CYCLE
#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
#define NAND_MXC_NR_BUFS		8
#define NAND_MXC_SPARE_BUF_SIZE		64
#define NAND_MXC_REG_OFFSET		0x1e00
#endif

struct fsl_nfc_regs {
	u8 main_area[NAND_MXC_NR_BUFS][0x200];
	u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
	/*
	 * reserved size is offset of nfc registers
	 * minus total main and spare sizes
	 */
	u8 reserved1[NAND_MXC_REG_OFFSET
		- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
#if defined(MXC_NFC_V1)
	u16 buf_size;
	u16 reserved2;
	u16 buf_addr;
	u16 flash_addr;
	u16 flash_cmd;
	u16 config;
	u16 ecc_status_result;
	u16 rsltmain_area;
	u16 rsltspare_area;
	u16 wrprot;
	u16 unlockstart_blkaddr;
	u16 unlockend_blkaddr;
	u16 nf_wrprst;
	u16 config1;
	u16 config2;
#elif defined(MXC_NFC_V2_1)
	u16 reserved2[2];
	u16 buf_addr;
	u16 flash_addr;
	u16 flash_cmd;
	u16 config;
	u32 ecc_status_result;
	u16 spare_area_size;
	u16 wrprot;
	u16 reserved3[2];
	u16 nf_wrprst;
	u16 config1;
	u16 config2;
	u16 reserved4;
	u16 unlockstart_blkaddr;
	u16 unlockend_blkaddr;
	u16 unlockstart_blkaddr1;
	u16 unlockend_blkaddr1;
	u16 unlockstart_blkaddr2;
	u16 unlockend_blkaddr2;
	u16 unlockstart_blkaddr3;
	u16 unlockend_blkaddr3;
#elif defined(MXC_NFC_V3_2)
	u32 flash_cmd;
	u32 flash_addr[12];
	u32 config1;
	u32 ecc_status_result;
	u32 status_sum;
	u32 launch;
#endif
};

#ifdef MXC_NFC_V3_2
struct fsl_nfc_ip_regs {
	u32 wrprot;
	u32 wrprot_unlock_blkaddr[8];
	u32 config2;
	u32 config3;
	u32 ipc;
	u32 err_addr;
	u32 delay_line;
};
#endif

/* Set FCMD to 1, rest to 0 for Command operation */
#define NFC_CMD				0x1

/* Set FADD to 1, rest to 0 for Address operation */
#define NFC_ADDR			0x2

/* Set FDI to 1, rest to 0 for Input operation */
#define NFC_INPUT			0x4

/* Set FDO to 001, rest to 0 for Data Output operation */
#define NFC_OUTPUT			0x8

/* Set FDO to 010, rest to 0 for Read ID operation */
#define NFC_ID				0x10

/* Set FDO to 100, rest to 0 for Read Status operation */
#define NFC_STATUS			0x20

#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
#define NFC_CONFIG1_SP_EN		(1 << 2)
#define NFC_CONFIG1_RST			(1 << 6)
#define NFC_CONFIG1_CE			(1 << 7)
#elif defined(MXC_NFC_V3_2)
#define NFC_CONFIG1_SP_EN		(1 << 0)
#define NFC_CONFIG1_CE			(1 << 1)
#define NFC_CONFIG1_RST			(1 << 2)
#endif
#define NFC_V1_V2_CONFIG1_ECC_EN	(1 << 3)
#define NFC_V1_V2_CONFIG1_INT_MSK	(1 << 4)
#define NFC_V1_V2_CONFIG1_BIG		(1 << 5)
#define NFC_V2_CONFIG1_ECC_MODE_4	(1 << 0)
#define NFC_V2_CONFIG1_ONE_CYCLE	(1 << 8)
#define NFC_V2_CONFIG1_FP_INT		(1 << 11)
#define NFC_V3_CONFIG1_RBA_MASK		(0x7 << 4)
#define NFC_V3_CONFIG1_RBA(x)		(((x) & 0x7) << 4)

#define NFC_V1_V2_CONFIG2_INT		(1 << 15)
#define NFC_V3_CONFIG2_PS_MASK		(0x3 << 0)
#define NFC_V3_CONFIG2_PS_512		(0 << 0)
#define NFC_V3_CONFIG2_PS_2048		(1 << 0)
#define NFC_V3_CONFIG2_PS_4096		(2 << 0)
#define NFC_V3_CONFIG2_ONE_CYCLE	(1 << 2)
#define NFC_V3_CONFIG2_ECC_EN		(1 << 3)
#define NFC_V3_CONFIG2_2CMD_PHASES	(1 << 4)
#define NFC_V3_CONFIG2_NUM_ADDR_PH0	(1 << 5)
#define NFC_V3_CONFIG2_ECC_MODE_8	(1 << 6)
#define NFC_V3_CONFIG2_PPB_MASK		(0x3 << 7)
#define NFC_V3_CONFIG2_PPB(x)		(((x) & 0x3) << 7)
#define NFC_V3_CONFIG2_EDC_MASK		(0x7 << 9)
#define NFC_V3_CONFIG2_EDC(x)		(((x) & 0x7) << 9)
#define NFC_V3_CONFIG2_NUM_ADDR_PH1(x)	(((x) & 0x3) << 12)
#define NFC_V3_CONFIG2_INT_MSK		(1 << 15)
#define NFC_V3_CONFIG2_SPAS_MASK	(0xff << 16)
#define NFC_V3_CONFIG2_SPAS(x)		(((x) & 0xff) << 16)
#define NFC_V3_CONFIG2_ST_CMD_MASK	(0xff << 24)
#define NFC_V3_CONFIG2_ST_CMD(x)	(((x) & 0xff) << 24)

#define NFC_V3_CONFIG3_ADD_OP(x)	(((x) & 0x3) << 0)
#define NFC_V3_CONFIG3_FW8		(1 << 3)
#define NFC_V3_CONFIG3_SBB(x)		(((x) & 0x7) << 8)
#define NFC_V3_CONFIG3_NUM_OF_DEVS(x)	(((x) & 0x7) << 12)
#define NFC_V3_CONFIG3_RBB_MODE		(1 << 15)
#define NFC_V3_CONFIG3_NO_SDMA		(1 << 20)

#define NFC_V3_WRPROT_UNLOCK		(1 << 2)
#define NFC_V3_WRPROT_BLS_UNLOCK	(2 << 6)

#define NFC_V3_IPC_CREQ			(1 << 0)
#define NFC_V3_IPC_INT			(1 << 31)

#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
#define operation	config2
#define readnfc		readw
#define writenfc	writew
#elif defined(MXC_NFC_V3_2)
#define operation	launch
#define readnfc		readl
#define writenfc	writel
#endif

#endif /* __FSL_NFC_H */
Commit	Line	Data
40c642bc	1	/*
40c642bc ML	2	* (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#ifndef __FSL_NFC_H
	24	#define __FSL_NFC_H
	25
	26	/*
80c8ab7b BT	27	* Register map and bit definitions for the Freescale NAND Flash Controller
80c8ab7b BT	28	* present in various i.MX devices.
f3bb63a3	29	*
80c8ab7b BT	30	* MX31 and MX27 have version 1, which has:
	31	* 4 512-byte main buffers and
	32	* 4 16-byte spare buffers
	33	* to support up to 2K byte pagesize nand.
	34	* Reading or writing a 2K page requires 4 FDI/FDO cycles.
f3bb63a3	35	*
35537bc7 BT	36	* MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which
35537bc7 BT	37	* have:
80c8ab7b BT	38	* 8 512-byte main buffers and
	39	* 8 64-byte spare buffers
	40	* to support up to 4K byte pagesize nand.
	41	* Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
	42	* Also some of registers are moved and/or changed meaning as seen below.
40c642bc	43	*/
80c8ab7b	44	#if defined(CONFIG_MX27) \|\| defined(CONFIG_MX31)
f3bb63a3	45	#define MXC_NFC_V1
9c60e75e BT	46	#define is_mxc_nfc_1() 1
9c60e75e BT	47	#define is_mxc_nfc_21() 0
35537bc7	48	#define is_mxc_nfc_32() 0
80c8ab7b	49	#elif defined(CONFIG_MX25) \|\| defined(CONFIG_MX35)
9c60e75e BT	50	#define MXC_NFC_V2_1
	51	#define is_mxc_nfc_1() 0
	52	#define is_mxc_nfc_21() 1
35537bc7 BT	53	#define is_mxc_nfc_32() 0
	54	#elif defined(CONFIG_MX51) \|\| defined(CONFIG_MX53)
	55	#define MXC_NFC_V3
	56	#define MXC_NFC_V3_2
	57	#define is_mxc_nfc_1() 0
	58	#define is_mxc_nfc_21() 0
	59	#define is_mxc_nfc_32() 1
f3bb63a3	60	#else
1884d657	61	#error "MXC NFC implementation not supported"
f3bb63a3	62	#endif
35537bc7	63	#define is_mxc_nfc_3() is_mxc_nfc_32()
f3bb63a3 JR	64
	65	#if defined(MXC_NFC_V1)
	66	#define NAND_MXC_NR_BUFS 4
	67	#define NAND_MXC_SPARE_BUF_SIZE 16
	68	#define NAND_MXC_REG_OFFSET 0xe00
80c8ab7b	69	#define NAND_MXC_2K_MULTI_CYCLE
35537bc7	70	#elif defined(MXC_NFC_V2_1) \|\| defined(MXC_NFC_V3_2)
f3bb63a3 JR	71	#define NAND_MXC_NR_BUFS 8
	72	#define NAND_MXC_SPARE_BUF_SIZE 64
	73	#define NAND_MXC_REG_OFFSET 0x1e00
f3bb63a3	74	#endif
40c642bc ML	75
40c642bc ML	76	struct fsl_nfc_regs {
80c8ab7b BT	77	u8 main_area[NAND_MXC_NR_BUFS][0x200];
80c8ab7b BT	78	u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
f3bb63a3 JR	79	/*
	80	* reserved size is offset of nfc registers
	81	* minus total main and spare sizes
	82	*/
	83	u8 reserved1[NAND_MXC_REG_OFFSET
	84	- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
	85	#if defined(MXC_NFC_V1)
80c8ab7b	86	u16 buf_size;
40c642bc	87	u16 reserved2;
80c8ab7b BT	88	u16 buf_addr;
80c8ab7b BT	89	u16 flash_addr;
40c642bc	90	u16 flash_cmd;
80c8ab7b	91	u16 config;
40c642bc	92	u16 ecc_status_result;
80c8ab7b BT	93	u16 rsltmain_area;
	94	u16 rsltspare_area;
	95	u16 wrprot;
	96	u16 unlockstart_blkaddr;
	97	u16 unlockend_blkaddr;
	98	u16 nf_wrprst;
	99	u16 config1;
	100	u16 config2;
9c60e75e	101	#elif defined(MXC_NFC_V2_1)
f3bb63a3	102	u16 reserved2[2];
80c8ab7b BT	103	u16 buf_addr;
80c8ab7b BT	104	u16 flash_addr;
f3bb63a3	105	u16 flash_cmd;
80c8ab7b	106	u16 config;
c1db8dd6	107	u32 ecc_status_result;
f3bb63a3	108	u16 spare_area_size;
80c8ab7b	109	u16 wrprot;
f3bb63a3	110	u16 reserved3[2];
80c8ab7b BT	111	u16 nf_wrprst;
	112	u16 config1;
	113	u16 config2;
f3bb63a3	114	u16 reserved4;
80c8ab7b BT	115	u16 unlockstart_blkaddr;
	116	u16 unlockend_blkaddr;
	117	u16 unlockstart_blkaddr1;
	118	u16 unlockend_blkaddr1;
	119	u16 unlockstart_blkaddr2;
	120	u16 unlockend_blkaddr2;
	121	u16 unlockstart_blkaddr3;
	122	u16 unlockend_blkaddr3;
35537bc7 BT	123	#elif defined(MXC_NFC_V3_2)
	124	u32 flash_cmd;
	125	u32 flash_addr[12];
	126	u32 config1;
	127	u32 ecc_status_result;
	128	u32 status_sum;
	129	u32 launch;
f3bb63a3	130	#endif
40c642bc ML	131	};
40c642bc ML	132
35537bc7 BT	133	#ifdef MXC_NFC_V3_2
	134	struct fsl_nfc_ip_regs {
	135	u32 wrprot;
	136	u32 wrprot_unlock_blkaddr[8];
	137	u32 config2;
	138	u32 config3;
	139	u32 ipc;
	140	u32 err_addr;
	141	u32 delay_line;
	142	};
	143	#endif
	144
2dc0aa02 BT	145	/* Set FCMD to 1, rest to 0 for Command operation */
2dc0aa02 BT	146	#define NFC_CMD 0x1
40c642bc	147
2dc0aa02 BT	148	/* Set FADD to 1, rest to 0 for Address operation */
2dc0aa02 BT	149	#define NFC_ADDR 0x2
40c642bc	150
2dc0aa02 BT	151	/* Set FDI to 1, rest to 0 for Input operation */
2dc0aa02 BT	152	#define NFC_INPUT 0x4
40c642bc	153
2dc0aa02 BT	154	/* Set FDO to 001, rest to 0 for Data Output operation */
2dc0aa02 BT	155	#define NFC_OUTPUT 0x8
40c642bc	156
2dc0aa02 BT	157	/* Set FDO to 010, rest to 0 for Read ID operation */
2dc0aa02 BT	158	#define NFC_ID 0x10
40c642bc	159
2dc0aa02 BT	160	/* Set FDO to 100, rest to 0 for Read Status operation */
2dc0aa02 BT	161	#define NFC_STATUS 0x20
40c642bc	162
35537bc7	163	#if defined(MXC_NFC_V1) \|\| defined(MXC_NFC_V2_1)
2dc0aa02 BT	164	#define NFC_CONFIG1_SP_EN (1 << 2)
	165	#define NFC_CONFIG1_RST (1 << 6)
	166	#define NFC_CONFIG1_CE (1 << 7)
35537bc7 BT	167	#elif defined(MXC_NFC_V3_2)
	168	#define NFC_CONFIG1_SP_EN (1 << 0)
	169	#define NFC_CONFIG1_CE (1 << 1)
	170	#define NFC_CONFIG1_RST (1 << 2)
	171	#endif
2dc0aa02 BT	172	#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
	173	#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
	174	#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
	175	#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
	176	#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
	177	#define NFC_V2_CONFIG1_FP_INT (1 << 11)
35537bc7 BT	178	#define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4)
35537bc7 BT	179	#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4)
40c642bc	180
2dc0aa02	181	#define NFC_V1_V2_CONFIG2_INT (1 << 15)
35537bc7 BT	182	#define NFC_V3_CONFIG2_PS_MASK (0x3 << 0)
	183	#define NFC_V3_CONFIG2_PS_512 (0 << 0)
	184	#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
	185	#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
	186	#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
	187	#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
	188	#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
	189	#define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5)
	190	#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
	191	#define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7)
	192	#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
	193	#define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9)
	194	#define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9)
	195	#define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12)
	196	#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
	197	#define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16)
	198	#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
	199	#define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24)
	200	#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
	201
	202	#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
	203	#define NFC_V3_CONFIG3_FW8 (1 << 3)
	204	#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
	205	#define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12)
	206	#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
	207	#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
2dc0aa02	208
35537bc7 BT	209	#define NFC_V3_WRPROT_UNLOCK (1 << 2)
	210	#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
	211
	212	#define NFC_V3_IPC_CREQ (1 << 0)
	213	#define NFC_V3_IPC_INT (1 << 31)
	214
	215	#if defined(MXC_NFC_V1) \|\| defined(MXC_NFC_V2_1)
2dc0aa02 BT	216	#define operation config2
	217	#define readnfc readw
	218	#define writenfc writew
35537bc7 BT	219	#elif defined(MXC_NFC_V3_2)
	220	#define operation launch
	221	#define readnfc readl
	222	#define writenfc writel
	223	#endif
40c642bc ML	224
40c642bc ML	225	#endif /* __FSL_NFC_H */