[thirdparty/u-boot.git] / include / fsl_sec.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Common internal memory map for some Freescale SoCs
 *
 * Copyright 2014 Freescale Semiconductor, Inc.
 */

#ifndef __FSL_SEC_H
#define __FSL_SEC_H

#include <common.h>
#include <asm/io.h>

#ifdef CONFIG_SYS_FSL_SEC_LE
#define sec_in32(a)       in_le32(a)
#define sec_out32(a, v)   out_le32(a, v)
#define sec_in16(a)       in_le16(a)
#define sec_clrbits32     clrbits_le32
#define sec_setbits32     setbits_le32
#elif defined(CONFIG_SYS_FSL_SEC_BE)
#define sec_in32(a)       in_be32(a)
#define sec_out32(a, v)   out_be32(a, v)
#define sec_in16(a)       in_be16(a)
#define sec_clrbits32     clrbits_be32
#define sec_setbits32     setbits_be32
#elif defined(CONFIG_SYS_FSL_HAS_SEC)
#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
#endif

/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
/* RNG4 TRNG test registers */
struct rng4tst {
#define RTMCTL_PRGM 0x00010000	/* 1 -> program mode, 0 -> run mode */
#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC     0 /* use von Neumann data in
						    both entropy shifter and
						    statistical checker */
#define RTMCTL_SAMP_MODE_RAW_ES_SC             1 /* use raw data in both
						    entropy shifter and
						    statistical checker */
#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
						    entropy shifter, raw data
						    in statistical checker */
#define RTMCTL_SAMP_MODE_INVALID               3 /* invalid combination */
	u32 rtmctl;		/* misc. control register */
	u32 rtscmisc;		/* statistical check misc. register */
	u32 rtpkrrng;		/* poker range register */
#define RTSDCTL_ENT_DLY_MIN	3200
#define RTSDCTL_ENT_DLY_MAX	12800
	union {
		u32 rtpkrmax;	/* PRGM=1: poker max. limit register */
		u32 rtpkrsq;	/* PRGM=0: poker square calc. result register */
	};
#define RTSDCTL_ENT_DLY_SHIFT 16
#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
	u32 rtsdctl;		/* seed control register */
	union {
		u32 rtsblim;	/* PRGM=1: sparse bit limit register */
		u32 rttotsam;	/* PRGM=0: total samples register */
	};
	u32 rtfreqmin;		/* frequency count min. limit register */
#define RTFRQMAX_DISABLE       (1 << 20)
	union {
		u32 rtfreqmax;	/* PRGM=1: freq. count max. limit register */
		u32 rtfreqcnt;	/* PRGM=0: freq. count register */
	};
	u32 rsvd1[40];
#define RNG_STATE0_HANDLE_INSTANTIATED	0x00000001
#define RNG_STATE1_HANDLE_INSTANTIATED	0x00000002
#define RNG_STATE_HANDLE_MASK	\
	(RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
	u32 rdsta;		/*RNG DRNG Status Register*/
	u32 rsvd2[15];
};

typedef struct ccsr_sec {
	u32	res0;
	u32	mcfgr;		/* Master CFG Register */
	u8	res1[0x4];
	u32	scfgr;
	struct {
		u32	ms;	/* Job Ring LIODN Register, MS */
		u32	ls;	/* Job Ring LIODN Register, LS */
	} jrliodnr[4];
	u8	res2[0x2c];
	u32	jrstartr;	/* Job Ring Start Register */
	struct {
		u32	ms;	/* RTIC LIODN Register, MS */
		u32	ls;	/* RTIC LIODN Register, LS */
	} rticliodnr[4];
	u8	res3[0x1c];
	u32	decorr;		/* DECO Request Register */
	struct {
		u32	ms;	/* DECO LIODN Register, MS */
		u32	ls;	/* DECO LIODN Register, LS */
	} decoliodnr[8];
	u8	res4[0x40];
	u32	dar;		/* DECO Avail Register */
	u32	drr;		/* DECO Reset Register */
	u8	res5[0x4d8];
	struct rng4tst rng;	/* RNG Registers */
	u8	res6[0x8a0];
	u32	crnr_ms;	/* CHA Revision Number Register, MS */
	u32	crnr_ls;	/* CHA Revision Number Register, LS */
	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
	u8	res7[0x10];
	u32	far_ms;		/* Fault Address Register, MS */
	u32	far_ls;		/* Fault Address Register, LS */
	u32	falr;		/* Fault Address LIODN Register */
	u32	fadr;		/* Fault Address Detail Register */
	u8	res8[0x4];
	u32	csta;		/* CAAM Status Register */
	u32	smpart;		/* Secure Memory Partition Parameters */
	u32	smvid;		/* Secure Memory Version ID */
	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
	u32	chavid_ms;	/* CHA Version ID Register, MS */
	u32	chavid_ls;	/* CHA Version ID Register, LS */
	u32	chanum_ms;	/* CHA Number Register, MS */
	u32	chanum_ls;	/* CHA Number Register, LS */
	u32	secvid_ms;	/* SEC Version ID Register, MS */
	u32	secvid_ls;	/* SEC Version ID Register, LS */
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
	u8	res9[0x6f020];
#else
	u8	res9[0x6020];
#endif
	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
	u8	res10[0x8ffd8];
#else
	u8	res10[0x8fd8];
#endif
} ccsr_sec_t;

#define SEC_CTPR_MS_AXI_LIODN		0x08000000
#define SEC_CTPR_MS_QI			0x02000000
#define SEC_CTPR_MS_VIRT_EN_INCL	0x00000001
#define SEC_CTPR_MS_VIRT_EN_POR		0x00000002
#define SEC_RVID_MA			0x0f000000
#define SEC_CHANUM_MS_JRNUM_MASK	0xf0000000
#define SEC_CHANUM_MS_JRNUM_SHIFT	28
#define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT	24
#define SEC_SECVID_MS_IPID_MASK	0xffff0000
#define SEC_SECVID_MS_IPID_SHIFT	16
#define SEC_SECVID_MS_MAJ_REV_MASK	0x0000ff00
#define SEC_SECVID_MS_MAJ_REV_SHIFT	8
#define SEC_CCBVID_ERA_MASK		0xff000000
#define SEC_CCBVID_ERA_SHIFT		24
#define SEC_SCFGR_RDBENABLE		0x00000400
#define SEC_SCFGR_VIRT_EN		0x00008000
#define SEC_CHAVID_LS_RNG_SHIFT		16
#define SEC_CHAVID_RNG_LS_MASK		0x000f0000

#define CONFIG_JRSTARTR_JR0		0x00000001

struct jr_regs {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
	u32 irba_l;
	u32 irba_h;
#else
	u32 irba_h;
	u32 irba_l;
#endif
	u32 rsvd1;
	u32 irs;
	u32 rsvd2;
	u32 irsa;
	u32 rsvd3;
	u32 irja;
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
	u32 orba_l;
	u32 orba_h;
#else
	u32 orba_h;
	u32 orba_l;
#endif
	u32 rsvd4;
	u32 ors;
	u32 rsvd5;
	u32 orjr;
	u32 rsvd6;
	u32 orsf;
	u32 rsvd7;
	u32 jrsta;
	u32 rsvd8;
	u32 jrint;
	u32 jrcfg0;
	u32 jrcfg1;
	u32 rsvd9;
	u32 irri;
	u32 rsvd10;
	u32 orwi;
	u32 rsvd11;
	u32 jrcr;
};

/*
 * Scatter Gather Entry - Specifies the the Scatter Gather Format
 * related information
 */
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
	uint32_t addr_lo;	/* Memory Address - lo */
	uint32_t addr_hi;	/* Memory Address of start of buffer - hi */
#else
	uint32_t addr_hi;	/* Memory Address of start of buffer - hi */
	uint32_t addr_lo;	/* Memory Address - lo */
#endif

	uint32_t len_flag;	/* Length of the data in the frame */
#define SG_ENTRY_LENGTH_MASK	0x3FFFFFFF
#define SG_ENTRY_EXTENSION_BIT	0x80000000
#define SG_ENTRY_FINAL_BIT	0x40000000
	uint32_t bpid_offset;
#define SG_ENTRY_BPID_MASK	0x00FF0000
#define SG_ENTRY_BPID_SHIFT	16
#define SG_ENTRY_OFFSET_MASK	0x00001FFF
#define SG_ENTRY_OFFSET_SHIFT	0
};

#define BLOB_SIZE(x)		((x) + 32 + 16) /* Blob buffer size */

#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
/* Job Ring Base Address */
#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
/* Secure Memory Offset varies accross versions */
#define SM_V1_OFFSET 0x0f4
#define SM_V2_OFFSET 0xa00
/*Secure Memory Versioning */
#define SMVID_V2 0x20105
#define SM_VERSION(x)  (x < SMVID_V2 ? 1 : 2)
#define SM_OFFSET(x)  (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
/* CAAM Job Ring 0 Registers */
/* Secure Memory Partition Owner register */
#define SMCSJR_PO		(3 << 6)
/* JR Allocation Error */
#define SMCSJR_AERR		(3 << 12)
/* Secure memory partition 0 page 0 owner register */
#define CAAM_SMPO_0	    (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
/* Secure memory command register */
#define CAAM_SMCJR(v, jr)   (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
/* Secure memory command status register */
#define CAAM_SMCSJR(v, jr)  (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
/* Secure memory access permissions register */
#define CAAM_SMAPJR(v, jr, y) \
	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
/* Secure memory access group 2 register */
#define CAAM_SMAG2JR(v, jr, y) \
	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
/* Secure memory access group 1 register */
#define CAAM_SMAG1JR(v, jr, y)  \
	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)

/* Commands and macros for secure memory */
#define SM_CMD(v)		(v == 1 ? 0x0 : 0x1E4)
#define SM_STATUS(v)		(v == 1 ? 0x8 : 0x1EC)
#define SM_PERM(v)		(v == 1 ?  0x10 : 0x4)
#define SM_GROUP2(v)		(v == 1 ? 0x14 : 0x8)
#define SM_GROUP1(v)		(v == 1 ? 0x18 : 0xC)
#define CMD_PAGE_ALLOC		0x1
#define CMD_PAGE_DEALLOC	0x2
#define CMD_PART_DEALLOC	0x3
#define CMD_INQUIRY		0x5
#define CMD_COMPLETE		(3 << 14)
#define PAGE_AVAILABLE		0
#define PAGE_OWNED		(3 << 6)
#define PAGE(x)			(x << 16)
#define PARTITION(x)		(x << 8)
#define PARTITION_OWNER(x)	(0x3 << (x*2))

/* Address of secure 4kbyte pages */
#define SEC_MEM_PAGE0		CAAM_ARB_BASE_ADDR
#define SEC_MEM_PAGE1		(CAAM_ARB_BASE_ADDR + 0x1000)
#define SEC_MEM_PAGE2		(CAAM_ARB_BASE_ADDR + 0x2000)
#define SEC_MEM_PAGE3		(CAAM_ARB_BASE_ADDR + 0x3000)

#define JR_MID			2               /* Matches ROM configuration */
#define KS_G1			(1 << JR_MID)   /* CAAM only */
#define PERM			0x0000B008      /* Clear on release, lock SMAP
						 * lock SMAG group 1 Blob */

/* HAB WRAPPED KEY header */
#define WRP_HDR_SIZE		0x08
#define HDR_TAG			0x81
#define HDR_PAR			0x41
/* HAB WRAPPED KEY Data */
#define HAB_MOD			0x66
#define HAB_ALG			0x55
#define HAB_FLG			0x00

/* Partition and Page IDs */
#define PARTITION_1	1
#define PAGE_1			1

#define ERROR_IN_PAGE_ALLOC	1
#define ECONSTRJDESC   -1

#endif

/* blob_dek:
 * Encapsulates the src in a secure blob and stores it dst
 * @src: reference to the plaintext
 * @dst: reference to the output adrress
 * @len: size in bytes of src
 * @return: 0 on success, error otherwise
 */
int blob_dek(const u8 *src, u8 *dst, u8 len);

#if defined(CONFIG_ARCH_C29X)
int sec_init_idx(uint8_t);
#endif
int sec_init(void);
#endif

#endif /* __FSL_SEC_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
48ef0d2a RG	2	/*
	3	* Common internal memory map for some Freescale SoCs
	4	*
	5	* Copyright 2014 Freescale Semiconductor, Inc.
48ef0d2a RG	6	*/
	7
	8	#ifndef __FSL_SEC_H
	9	#define __FSL_SEC_H
	10
	11	#include <common.h>
	12	#include <asm/io.h>
	13
028dbb8d RG	14	#ifdef CONFIG_SYS_FSL_SEC_LE
	15	#define sec_in32(a) in_le32(a)
	16	#define sec_out32(a, v) out_le32(a, v)
	17	#define sec_in16(a) in_le16(a)
	18	#define sec_clrbits32 clrbits_le32
	19	#define sec_setbits32 setbits_le32
	20	#elif defined(CONFIG_SYS_FSL_SEC_BE)
	21	#define sec_in32(a) in_be32(a)
	22	#define sec_out32(a, v) out_be32(a, v)
	23	#define sec_in16(a) in_be16(a)
	24	#define sec_clrbits32 clrbits_be32
	25	#define sec_setbits32 setbits_be32
90b80386	26	#elif defined(CONFIG_SYS_FSL_HAS_SEC)
028dbb8d RG	27	#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
	28	#endif
	29
48ef0d2a RG	30	/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
48ef0d2a RG	31	#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
c5de15cb RG	32	/* RNG4 TRNG test registers */
	33	struct rng4tst {
	34	#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
c4065517 AP	35	#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
	36	both entropy shifter and
	37	statistical checker */
	38	#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
	39	entropy shifter and
	40	statistical checker */
	41	#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
	42	entropy shifter, raw data
	43	in statistical checker */
	44	#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
c5de15cb RG	45	u32 rtmctl; /* misc. control register */
	46	u32 rtscmisc; /* statistical check misc. register */
	47	u32 rtpkrrng; /* poker range register */
17649e1b	48	#define RTSDCTL_ENT_DLY_MIN 3200
c5de15cb RG	49	#define RTSDCTL_ENT_DLY_MAX 12800
	50	union {
	51	u32 rtpkrmax; /* PRGM=1: poker max. limit register */
	52	u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
	53	};
	54	#define RTSDCTL_ENT_DLY_SHIFT 16
	55	#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
	56	u32 rtsdctl; /* seed control register */
	57	union {
	58	u32 rtsblim; /* PRGM=1: sparse bit limit register */
	59	u32 rttotsam; /* PRGM=0: total samples register */
	60	};
	61	u32 rtfreqmin; /* frequency count min. limit register */
026a3f1b	62	#define RTFRQMAX_DISABLE (1 << 20)
c5de15cb RG	63	union {
	64	u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
	65	u32 rtfreqcnt; /* PRGM=0: freq. count register */
	66	};
	67	u32 rsvd1[40];
	68	#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
dfaec760 LA	69	#define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
	70	#define RNG_STATE_HANDLE_MASK \
	71	(RNG_STATE0_HANDLE_INSTANTIATED \| RNG_STATE1_HANDLE_INSTANTIATED)
c5de15cb RG	72	u32 rdsta; /RNG DRNG Status Register/
	73	u32 rsvd2[15];
	74	};
	75
48ef0d2a RG	76	typedef struct ccsr_sec {
	77	u32 res0;
	78	u32 mcfgr; /* Master CFG Register */
	79	u8 res1[0x4];
	80	u32 scfgr;
	81	struct {
	82	u32 ms; /* Job Ring LIODN Register, MS */
	83	u32 ls; /* Job Ring LIODN Register, LS */
	84	} jrliodnr[4];
	85	u8 res2[0x2c];
	86	u32 jrstartr; /* Job Ring Start Register */
	87	struct {
	88	u32 ms; /* RTIC LIODN Register, MS */
	89	u32 ls; /* RTIC LIODN Register, LS */
	90	} rticliodnr[4];
	91	u8 res3[0x1c];
	92	u32 decorr; /* DECO Request Register */
	93	struct {
	94	u32 ms; /* DECO LIODN Register, MS */
	95	u32 ls; /* DECO LIODN Register, LS */
	96	} decoliodnr[8];
	97	u8 res4[0x40];
	98	u32 dar; /* DECO Avail Register */
	99	u32 drr; /* DECO Reset Register */
c5de15cb RG	100	u8 res5[0x4d8];
c5de15cb RG	101	struct rng4tst rng; /* RNG Registers */
f91e65a7	102	u8 res6[0x8a0];
48ef0d2a RG	103	u32 crnr_ms; /* CHA Revision Number Register, MS */
	104	u32 crnr_ls; /* CHA Revision Number Register, LS */
	105	u32 ctpr_ms; /* Compile Time Parameters Register, MS */
	106	u32 ctpr_ls; /* Compile Time Parameters Register, LS */
f91e65a7	107	u8 res7[0x10];
48ef0d2a RG	108	u32 far_ms; /* Fault Address Register, MS */
	109	u32 far_ls; /* Fault Address Register, LS */
	110	u32 falr; /* Fault Address LIODN Register */
	111	u32 fadr; /* Fault Address Detail Register */
f91e65a7	112	u8 res8[0x4];
48ef0d2a	113	u32 csta; /* CAAM Status Register */
f91e65a7 UC	114	u32 smpart; /* Secure Memory Partition Parameters */
f91e65a7 UC	115	u32 smvid; /* Secure Memory Version ID */
48ef0d2a RG	116	u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
	117	u32 ccbvid; /* CHA Cluster Block Version ID Register */
	118	u32 chavid_ms; /* CHA Version ID Register, MS */
	119	u32 chavid_ls; /* CHA Version ID Register, LS */
	120	u32 chanum_ms; /* CHA Number Register, MS */
	121	u32 chanum_ls; /* CHA Number Register, LS */
	122	u32 secvid_ms; /* SEC Version ID Register, MS */
	123	u32 secvid_ls; /* SEC Version ID Register, LS */
d8d5fdb7 LT	124	#if defined(CONFIG_FSL_LSCH2) \|\| defined(CONFIG_FSL_LSCH3)
	125	u8 res9[0x6f020];
	126	#else
48ef0d2a	127	u8 res9[0x6020];
d8d5fdb7	128	#endif
48ef0d2a RG	129	u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
48ef0d2a RG	130	u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
d8d5fdb7 LT	131	#if defined(CONFIG_FSL_LSCH2) \|\| defined(CONFIG_FSL_LSCH3)
	132	u8 res10[0x8ffd8];
	133	#else
48ef0d2a	134	u8 res10[0x8fd8];
d8d5fdb7	135	#endif
48ef0d2a RG	136	} ccsr_sec_t;
	137
	138	#define SEC_CTPR_MS_AXI_LIODN 0x08000000
	139	#define SEC_CTPR_MS_QI 0x02000000
	140	#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
	141	#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
	142	#define SEC_RVID_MA 0x0f000000
	143	#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
	144	#define SEC_CHANUM_MS_JRNUM_SHIFT 28
	145	#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
	146	#define SEC_CHANUM_MS_DECONUM_SHIFT 24
	147	#define SEC_SECVID_MS_IPID_MASK 0xffff0000
	148	#define SEC_SECVID_MS_IPID_SHIFT 16
	149	#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
	150	#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
	151	#define SEC_CCBVID_ERA_MASK 0xff000000
	152	#define SEC_CCBVID_ERA_SHIFT 24
	153	#define SEC_SCFGR_RDBENABLE 0x00000400
	154	#define SEC_SCFGR_VIRT_EN 0x00008000
	155	#define SEC_CHAVID_LS_RNG_SHIFT 16
	156	#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
b9eebfad RG	157
	158	#define CONFIG_JRSTARTR_JR0 0x00000001
	159
	160	struct jr_regs {
f91e65a7 UC	161	#if defined(CONFIG_SYS_FSL_SEC_LE) && \
f91e65a7 UC	162	!(defined(CONFIG_MX6) \|\| defined(CONFIG_MX7))
b9eebfad RG	163	u32 irba_l;
	164	u32 irba_h;
	165	#else
	166	u32 irba_h;
	167	u32 irba_l;
	168	#endif
	169	u32 rsvd1;
	170	u32 irs;
	171	u32 rsvd2;
	172	u32 irsa;
	173	u32 rsvd3;
	174	u32 irja;
f91e65a7 UC	175	#if defined(CONFIG_SYS_FSL_SEC_LE) && \
f91e65a7 UC	176	!(defined(CONFIG_MX6) \|\| defined(CONFIG_MX7))
b9eebfad RG	177	u32 orba_l;
	178	u32 orba_h;
	179	#else
	180	u32 orba_h;
	181	u32 orba_l;
	182	#endif
	183	u32 rsvd4;
	184	u32 ors;
	185	u32 rsvd5;
	186	u32 orjr;
	187	u32 rsvd6;
	188	u32 orsf;
	189	u32 rsvd7;
	190	u32 jrsta;
	191	u32 rsvd8;
	192	u32 jrint;
	193	u32 jrcfg0;
	194	u32 jrcfg1;
	195	u32 rsvd9;
	196	u32 irri;
	197	u32 rsvd10;
	198	u32 orwi;
	199	u32 rsvd11;
	200	u32 jrcr;
	201	};
	202
94e3c8c4	203	/*
	204	* Scatter Gather Entry - Specifies the the Scatter Gather Format
	205	* related information
	206	*/
	207	struct sg_entry {
f91e65a7 UC	208	#if defined(CONFIG_SYS_FSL_SEC_LE) && \
f91e65a7 UC	209	!(defined(CONFIG_MX6) \|\| defined(CONFIG_MX7))
94e3c8c4	210	uint32_t addr_lo; /* Memory Address - lo */
f59e69cb	211	uint32_t addr_hi; /* Memory Address of start of buffer - hi */
94e3c8c4	212	#else
f59e69cb	213	uint32_t addr_hi; /* Memory Address of start of buffer - hi */
94e3c8c4	214	uint32_t addr_lo; /* Memory Address - lo */
	215	#endif
	216
	217	uint32_t len_flag; /* Length of the data in the frame */
	218	#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
	219	#define SG_ENTRY_EXTENSION_BIT 0x80000000
	220	#define SG_ENTRY_FINAL_BIT 0x40000000
	221	uint32_t bpid_offset;
	222	#define SG_ENTRY_BPID_MASK 0x00FF0000
	223	#define SG_ENTRY_BPID_SHIFT 16
	224	#define SG_ENTRY_OFFSET_MASK 0x00001FFF
	225	#define SG_ENTRY_OFFSET_SHIFT 0
	226	};
	227
598e9dcc CG	228	#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
598e9dcc CG	229
f91e65a7 UC	230	#if defined(CONFIG_MX6) \|\| defined(CONFIG_MX7)
	231	/* Job Ring Base Address */
	232	#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
	233	/* Secure Memory Offset varies accross versions */
	234	#define SM_V1_OFFSET 0x0f4
	235	#define SM_V2_OFFSET 0xa00
	236	/Secure Memory Versioning /
	237	#define SMVID_V2 0x20105
	238	#define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2)
	239	#define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
0200020b RC	240	/* CAAM Job Ring 0 Registers */
	241	/* Secure Memory Partition Owner register */
	242	#define SMCSJR_PO (3 << 6)
	243	/* JR Allocation Error */
	244	#define SMCSJR_AERR (3 << 12)
	245	/* Secure memory partition 0 page 0 owner register */
f91e65a7	246	#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
0200020b	247	/* Secure memory command register */
f91e65a7	248	#define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
0200020b	249	/* Secure memory command status register */
f91e65a7	250	#define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
0200020b	251	/* Secure memory access permissions register */
f91e65a7 UC	252	#define CAAM_SMAPJR(v, jr, y) \
f91e65a7 UC	253	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
0200020b	254	/* Secure memory access group 2 register */
f91e65a7 UC	255	#define CAAM_SMAG2JR(v, jr, y) \
f91e65a7 UC	256	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
0200020b	257	/* Secure memory access group 1 register */
f91e65a7 UC	258	#define CAAM_SMAG1JR(v, jr, y) \
f91e65a7 UC	259	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
0200020b RC	260
0200020b RC	261	/* Commands and macros for secure memory */
f91e65a7 UC	262	#define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4)
	263	#define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC)
	264	#define SM_PERM(v) (v == 1 ? 0x10 : 0x4)
	265	#define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8)
	266	#define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC)
0200020b RC	267	#define CMD_PAGE_ALLOC 0x1
	268	#define CMD_PAGE_DEALLOC 0x2
	269	#define CMD_PART_DEALLOC 0x3
	270	#define CMD_INQUIRY 0x5
	271	#define CMD_COMPLETE (3 << 14)
	272	#define PAGE_AVAILABLE 0
	273	#define PAGE_OWNED (3 << 6)
	274	#define PAGE(x) (x << 16)
	275	#define PARTITION(x) (x << 8)
	276	#define PARTITION_OWNER(x) (0x3 << (x*2))
	277
	278	/* Address of secure 4kbyte pages */
	279	#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
	280	#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
	281	#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
	282	#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
	283
	284	#define JR_MID 2 /* Matches ROM configuration */
	285	#define KS_G1 (1 << JR_MID) /* CAAM only */
	286	#define PERM 0x0000B008 /* Clear on release, lock SMAP
	287	* lock SMAG group 1 Blob */
	288
0200020b RC	289	/* HAB WRAPPED KEY header */
	290	#define WRP_HDR_SIZE 0x08
	291	#define HDR_TAG 0x81
	292	#define HDR_PAR 0x41
	293	/* HAB WRAPPED KEY Data */
	294	#define HAB_MOD 0x66
	295	#define HAB_ALG 0x55
	296	#define HAB_FLG 0x00
	297
	298	/* Partition and Page IDs */
	299	#define PARTITION_1 1
	300	#define PAGE_1 1
	301
	302	#define ERROR_IN_PAGE_ALLOC 1
	303	#define ECONSTRJDESC -1
	304
	305	#endif
	306
0200020b RC	307	/* blob_dek:
	308	* Encapsulates the src in a secure blob and stores it dst
	309	* @src: reference to the plaintext
	310	* @dst: reference to the output adrress
	311	* @len: size in bytes of src
	312	* @return: 0 on success, error otherwise
	313	*/
	314	int blob_dek(const u8 src, u8 dst, u8 len);
	315
4fd64746	316	#if defined(CONFIG_ARCH_C29X)
76394c9c AP	317	int sec_init_idx(uint8_t);
	318	#endif
	319	int sec_init(void);
48ef0d2a RG	320	#endif
	321
	322	#endif /* __FSL_SEC_H */