[people/ms/u-boot.git] / include / fsl_sec.h

/*
 * Common internal memory map for some Freescale SoCs
 *
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 */

#ifndef __FSL_SEC_H
#define __FSL_SEC_H

#include <common.h>
#include <asm/io.h>

#ifdef CONFIG_SYS_FSL_SEC_LE
#define sec_in32(a)       in_le32(a)
#define sec_out32(a, v)   out_le32(a, v)
#define sec_in16(a)       in_le16(a)
#define sec_clrbits32     clrbits_le32
#define sec_setbits32     setbits_le32
#elif defined(CONFIG_SYS_FSL_SEC_BE)
#define sec_in32(a)       in_be32(a)
#define sec_out32(a, v)   out_be32(a, v)
#define sec_in16(a)       in_be16(a)
#define sec_clrbits32     clrbits_be32
#define sec_setbits32     setbits_be32
#else
#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
#endif

/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
/* RNG4 TRNG test registers */
struct rng4tst {
#define RTMCTL_PRGM 0x00010000	/* 1 -> program mode, 0 -> run mode */
	u32 rtmctl;		/* misc. control register */
	u32 rtscmisc;		/* statistical check misc. register */
	u32 rtpkrrng;		/* poker range register */
#define RTSDCTL_ENT_DLY_MIN	3200
#define RTSDCTL_ENT_DLY_MAX	12800
	union {
		u32 rtpkrmax;	/* PRGM=1: poker max. limit register */
		u32 rtpkrsq;	/* PRGM=0: poker square calc. result register */
	};
#define RTSDCTL_ENT_DLY_SHIFT 16
#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
	u32 rtsdctl;		/* seed control register */
	union {
		u32 rtsblim;	/* PRGM=1: sparse bit limit register */
		u32 rttotsam;	/* PRGM=0: total samples register */
	};
	u32 rtfreqmin;		/* frequency count min. limit register */
#define RTFRQMAX_DISABLE       (1 << 20)
	union {
		u32 rtfreqmax;	/* PRGM=1: freq. count max. limit register */
		u32 rtfreqcnt;	/* PRGM=0: freq. count register */
	};
	u32 rsvd1[40];
#define RNG_STATE0_HANDLE_INSTANTIATED	0x00000001
	u32 rdsta;		/*RNG DRNG Status Register*/
	u32 rsvd2[15];
};

typedef struct ccsr_sec {
	u32	res0;
	u32	mcfgr;		/* Master CFG Register */
	u8	res1[0x4];
	u32	scfgr;
	struct {
		u32	ms;	/* Job Ring LIODN Register, MS */
		u32	ls;	/* Job Ring LIODN Register, LS */
	} jrliodnr[4];
	u8	res2[0x2c];
	u32	jrstartr;	/* Job Ring Start Register */
	struct {
		u32	ms;	/* RTIC LIODN Register, MS */
		u32	ls;	/* RTIC LIODN Register, LS */
	} rticliodnr[4];
	u8	res3[0x1c];
	u32	decorr;		/* DECO Request Register */
	struct {
		u32	ms;	/* DECO LIODN Register, MS */
		u32	ls;	/* DECO LIODN Register, LS */
	} decoliodnr[8];
	u8	res4[0x40];
	u32	dar;		/* DECO Avail Register */
	u32	drr;		/* DECO Reset Register */
	u8	res5[0x4d8];
	struct rng4tst rng;	/* RNG Registers */
	u8	res11[0x8a0];
	u32	crnr_ms;	/* CHA Revision Number Register, MS */
	u32	crnr_ls;	/* CHA Revision Number Register, LS */
	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
	u8	res6[0x10];
	u32	far_ms;		/* Fault Address Register, MS */
	u32	far_ls;		/* Fault Address Register, LS */
	u32	falr;		/* Fault Address LIODN Register */
	u32	fadr;		/* Fault Address Detail Register */
	u8	res7[0x4];
	u32	csta;		/* CAAM Status Register */
	u8	res8[0x8];
	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
	u32	chavid_ms;	/* CHA Version ID Register, MS */
	u32	chavid_ls;	/* CHA Version ID Register, LS */
	u32	chanum_ms;	/* CHA Number Register, MS */
	u32	chanum_ls;	/* CHA Number Register, LS */
	u32	secvid_ms;	/* SEC Version ID Register, MS */
	u32	secvid_ls;	/* SEC Version ID Register, LS */
	u8	res9[0x6020];
	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
	u8	res10[0x8fd8];
} ccsr_sec_t;

#define SEC_CTPR_MS_AXI_LIODN		0x08000000
#define SEC_CTPR_MS_QI			0x02000000
#define SEC_CTPR_MS_VIRT_EN_INCL	0x00000001
#define SEC_CTPR_MS_VIRT_EN_POR		0x00000002
#define SEC_RVID_MA			0x0f000000
#define SEC_CHANUM_MS_JRNUM_MASK	0xf0000000
#define SEC_CHANUM_MS_JRNUM_SHIFT	28
#define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT	24
#define SEC_SECVID_MS_IPID_MASK	0xffff0000
#define SEC_SECVID_MS_IPID_SHIFT	16
#define SEC_SECVID_MS_MAJ_REV_MASK	0x0000ff00
#define SEC_SECVID_MS_MAJ_REV_SHIFT	8
#define SEC_CCBVID_ERA_MASK		0xff000000
#define SEC_CCBVID_ERA_SHIFT		24
#define SEC_SCFGR_RDBENABLE		0x00000400
#define SEC_SCFGR_VIRT_EN		0x00008000
#define SEC_CHAVID_LS_RNG_SHIFT		16
#define SEC_CHAVID_RNG_LS_MASK		0x000f0000

#define CONFIG_JRSTARTR_JR0		0x00000001

struct jr_regs {
#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
	u32 irba_l;
	u32 irba_h;
#else
	u32 irba_h;
	u32 irba_l;
#endif
	u32 rsvd1;
	u32 irs;
	u32 rsvd2;
	u32 irsa;
	u32 rsvd3;
	u32 irja;
#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
	u32 orba_l;
	u32 orba_h;
#else
	u32 orba_h;
	u32 orba_l;
#endif
	u32 rsvd4;
	u32 ors;
	u32 rsvd5;
	u32 orjr;
	u32 rsvd6;
	u32 orsf;
	u32 rsvd7;
	u32 jrsta;
	u32 rsvd8;
	u32 jrint;
	u32 jrcfg0;
	u32 jrcfg1;
	u32 rsvd9;
	u32 irri;
	u32 rsvd10;
	u32 orwi;
	u32 rsvd11;
	u32 jrcr;
};

/*
 * Scatter Gather Entry - Specifies the the Scatter Gather Format
 * related information
 */
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
	uint32_t addr_lo;	/* Memory Address - lo */
	uint16_t addr_hi;	/* Memory Address of start of buffer - hi */
	uint16_t reserved_zero;
#else
	uint16_t reserved_zero;
	uint16_t addr_hi;	/* Memory Address of start of buffer - hi */
	uint32_t addr_lo;	/* Memory Address - lo */
#endif

	uint32_t len_flag;	/* Length of the data in the frame */
#define SG_ENTRY_LENGTH_MASK	0x3FFFFFFF
#define SG_ENTRY_EXTENSION_BIT	0x80000000
#define SG_ENTRY_FINAL_BIT	0x40000000
	uint32_t bpid_offset;
#define SG_ENTRY_BPID_MASK	0x00FF0000
#define SG_ENTRY_BPID_SHIFT	16
#define SG_ENTRY_OFFSET_MASK	0x00001FFF
#define SG_ENTRY_OFFSET_SHIFT	0
};

#ifdef CONFIG_MX6
/* CAAM Job Ring 0 Registers */
/* Secure Memory Partition Owner register */
#define SMCSJR_PO		(3 << 6)
/* JR Allocation Error */
#define SMCSJR_AERR		(3 << 12)
/* Secure memory partition 0 page 0 owner register */
#define CAAM_SMPO_0		CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC
/* Secure memory command register */
#define CAAM_SMCJR0		CONFIG_SYS_FSL_SEC_ADDR + 0x10f4
/* Secure memory command status register */
#define CAAM_SMCSJR0		CONFIG_SYS_FSL_SEC_ADDR + 0x10fc
/* Secure memory access permissions register */
#define CAAM_SMAPJR0(y)	(CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
/* Secure memory access group 2 register */
#define CAAM_SMAG2JR0(y)	(CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
/* Secure memory access group 1 register */
#define CAAM_SMAG1JR0(y)	(CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)

/* Commands and macros for secure memory */
#define CMD_PAGE_ALLOC		0x1
#define CMD_PAGE_DEALLOC	0x2
#define CMD_PART_DEALLOC	0x3
#define CMD_INQUIRY		0x5
#define CMD_COMPLETE		(3 << 14)
#define PAGE_AVAILABLE		0
#define PAGE_OWNED		(3 << 6)
#define PAGE(x)			(x << 16)
#define PARTITION(x)		(x << 8)
#define PARTITION_OWNER(x)	(0x3 << (x*2))

/* Address of secure 4kbyte pages */
#define SEC_MEM_PAGE0		CAAM_ARB_BASE_ADDR
#define SEC_MEM_PAGE1		(CAAM_ARB_BASE_ADDR + 0x1000)
#define SEC_MEM_PAGE2		(CAAM_ARB_BASE_ADDR + 0x2000)
#define SEC_MEM_PAGE3		(CAAM_ARB_BASE_ADDR + 0x3000)

#define JR_MID			2               /* Matches ROM configuration */
#define KS_G1			(1 << JR_MID)   /* CAAM only */
#define PERM			0x0000B008      /* Clear on release, lock SMAP
						 * lock SMAG group 1 Blob */

#define BLOB_SIZE(x)       (x + 32 + 16) /* Blob buffer size */

/* HAB WRAPPED KEY header */
#define WRP_HDR_SIZE		0x08
#define HDR_TAG			0x81
#define HDR_PAR			0x41
/* HAB WRAPPED KEY Data */
#define HAB_MOD			0x66
#define HAB_ALG			0x55
#define HAB_FLG			0x00

/* Partition and Page IDs */
#define PARTITION_1	1
#define PAGE_1			1

#define ERROR_IN_PAGE_ALLOC	1
#define ECONSTRJDESC   -1

#endif

int sec_init(void);

/* blob_dek:
 * Encapsulates the src in a secure blob and stores it dst
 * @src: reference to the plaintext
 * @dst: reference to the output adrress
 * @len: size in bytes of src
 * @return: 0 on success, error otherwise
 */
int blob_dek(const u8 *src, u8 *dst, u8 len);

#endif

#endif /* __FSL_SEC_H */
Commit	Line	Data
48ef0d2a RG	1	/*
	2	* Common internal memory map for some Freescale SoCs
	3	*
	4	* Copyright 2014 Freescale Semiconductor, Inc.
	5	*
	6	*/
	7
	8	#ifndef __FSL_SEC_H
	9	#define __FSL_SEC_H
	10
	11	#include <common.h>
	12	#include <asm/io.h>
	13
028dbb8d RG	14	#ifdef CONFIG_SYS_FSL_SEC_LE
	15	#define sec_in32(a) in_le32(a)
	16	#define sec_out32(a, v) out_le32(a, v)
	17	#define sec_in16(a) in_le16(a)
	18	#define sec_clrbits32 clrbits_le32
	19	#define sec_setbits32 setbits_le32
	20	#elif defined(CONFIG_SYS_FSL_SEC_BE)
	21	#define sec_in32(a) in_be32(a)
	22	#define sec_out32(a, v) out_be32(a, v)
	23	#define sec_in16(a) in_be16(a)
	24	#define sec_clrbits32 clrbits_be32
	25	#define sec_setbits32 setbits_be32
	26	#else
	27	#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
	28	#endif
	29
48ef0d2a RG	30	/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
48ef0d2a RG	31	#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
c5de15cb RG	32	/* RNG4 TRNG test registers */
	33	struct rng4tst {
	34	#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
	35	u32 rtmctl; /* misc. control register */
	36	u32 rtscmisc; /* statistical check misc. register */
	37	u32 rtpkrrng; /* poker range register */
17649e1b	38	#define RTSDCTL_ENT_DLY_MIN 3200
c5de15cb RG	39	#define RTSDCTL_ENT_DLY_MAX 12800
	40	union {
	41	u32 rtpkrmax; /* PRGM=1: poker max. limit register */
	42	u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
	43	};
	44	#define RTSDCTL_ENT_DLY_SHIFT 16
	45	#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
	46	u32 rtsdctl; /* seed control register */
	47	union {
	48	u32 rtsblim; /* PRGM=1: sparse bit limit register */
	49	u32 rttotsam; /* PRGM=0: total samples register */
	50	};
	51	u32 rtfreqmin; /* frequency count min. limit register */
026a3f1b	52	#define RTFRQMAX_DISABLE (1 << 20)
c5de15cb RG	53	union {
	54	u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
	55	u32 rtfreqcnt; /* PRGM=0: freq. count register */
	56	};
	57	u32 rsvd1[40];
	58	#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
	59	u32 rdsta; /RNG DRNG Status Register/
	60	u32 rsvd2[15];
	61	};
	62
48ef0d2a RG	63	typedef struct ccsr_sec {
	64	u32 res0;
	65	u32 mcfgr; /* Master CFG Register */
	66	u8 res1[0x4];
	67	u32 scfgr;
	68	struct {
	69	u32 ms; /* Job Ring LIODN Register, MS */
	70	u32 ls; /* Job Ring LIODN Register, LS */
	71	} jrliodnr[4];
	72	u8 res2[0x2c];
	73	u32 jrstartr; /* Job Ring Start Register */
	74	struct {
	75	u32 ms; /* RTIC LIODN Register, MS */
	76	u32 ls; /* RTIC LIODN Register, LS */
	77	} rticliodnr[4];
	78	u8 res3[0x1c];
	79	u32 decorr; /* DECO Request Register */
	80	struct {
	81	u32 ms; /* DECO LIODN Register, MS */
	82	u32 ls; /* DECO LIODN Register, LS */
	83	} decoliodnr[8];
	84	u8 res4[0x40];
	85	u32 dar; /* DECO Avail Register */
	86	u32 drr; /* DECO Reset Register */
c5de15cb RG	87	u8 res5[0x4d8];
	88	struct rng4tst rng; /* RNG Registers */
	89	u8 res11[0x8a0];
48ef0d2a RG	90	u32 crnr_ms; /* CHA Revision Number Register, MS */
	91	u32 crnr_ls; /* CHA Revision Number Register, LS */
	92	u32 ctpr_ms; /* Compile Time Parameters Register, MS */
	93	u32 ctpr_ls; /* Compile Time Parameters Register, LS */
	94	u8 res6[0x10];
	95	u32 far_ms; /* Fault Address Register, MS */
	96	u32 far_ls; /* Fault Address Register, LS */
	97	u32 falr; /* Fault Address LIODN Register */
	98	u32 fadr; /* Fault Address Detail Register */
	99	u8 res7[0x4];
	100	u32 csta; /* CAAM Status Register */
	101	u8 res8[0x8];
	102	u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
	103	u32 ccbvid; /* CHA Cluster Block Version ID Register */
	104	u32 chavid_ms; /* CHA Version ID Register, MS */
	105	u32 chavid_ls; /* CHA Version ID Register, LS */
	106	u32 chanum_ms; /* CHA Number Register, MS */
	107	u32 chanum_ls; /* CHA Number Register, LS */
	108	u32 secvid_ms; /* SEC Version ID Register, MS */
	109	u32 secvid_ls; /* SEC Version ID Register, LS */
	110	u8 res9[0x6020];
	111	u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
	112	u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
	113	u8 res10[0x8fd8];
	114	} ccsr_sec_t;
	115
	116	#define SEC_CTPR_MS_AXI_LIODN 0x08000000
	117	#define SEC_CTPR_MS_QI 0x02000000
	118	#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
	119	#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
	120	#define SEC_RVID_MA 0x0f000000
	121	#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
	122	#define SEC_CHANUM_MS_JRNUM_SHIFT 28
	123	#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
	124	#define SEC_CHANUM_MS_DECONUM_SHIFT 24
	125	#define SEC_SECVID_MS_IPID_MASK 0xffff0000
	126	#define SEC_SECVID_MS_IPID_SHIFT 16
	127	#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
	128	#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
	129	#define SEC_CCBVID_ERA_MASK 0xff000000
	130	#define SEC_CCBVID_ERA_SHIFT 24
	131	#define SEC_SCFGR_RDBENABLE 0x00000400
	132	#define SEC_SCFGR_VIRT_EN 0x00008000
	133	#define SEC_CHAVID_LS_RNG_SHIFT 16
	134	#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
b9eebfad RG	135
	136	#define CONFIG_JRSTARTR_JR0 0x00000001
	137
	138	struct jr_regs {
0200020b	139	#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
b9eebfad RG	140	u32 irba_l;
	141	u32 irba_h;
	142	#else
	143	u32 irba_h;
	144	u32 irba_l;
	145	#endif
	146	u32 rsvd1;
	147	u32 irs;
	148	u32 rsvd2;
	149	u32 irsa;
	150	u32 rsvd3;
	151	u32 irja;
0200020b	152	#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
b9eebfad RG	153	u32 orba_l;
	154	u32 orba_h;
	155	#else
	156	u32 orba_h;
	157	u32 orba_l;
	158	#endif
	159	u32 rsvd4;
	160	u32 ors;
	161	u32 rsvd5;
	162	u32 orjr;
	163	u32 rsvd6;
	164	u32 orsf;
	165	u32 rsvd7;
	166	u32 jrsta;
	167	u32 rsvd8;
	168	u32 jrint;
	169	u32 jrcfg0;
	170	u32 jrcfg1;
	171	u32 rsvd9;
	172	u32 irri;
	173	u32 rsvd10;
	174	u32 orwi;
	175	u32 rsvd11;
	176	u32 jrcr;
	177	};
	178
94e3c8c4	179	/*
	180	* Scatter Gather Entry - Specifies the the Scatter Gather Format
	181	* related information
	182	*/
	183	struct sg_entry {
33d5156f	184	#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
94e3c8c4	185	uint32_t addr_lo; /* Memory Address - lo */
	186	uint16_t addr_hi; /* Memory Address of start of buffer - hi */
	187	uint16_t reserved_zero;
	188	#else
	189	uint16_t reserved_zero;
	190	uint16_t addr_hi; /* Memory Address of start of buffer - hi */
	191	uint32_t addr_lo; /* Memory Address - lo */
	192	#endif
	193
	194	uint32_t len_flag; /* Length of the data in the frame */
	195	#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
	196	#define SG_ENTRY_EXTENSION_BIT 0x80000000
	197	#define SG_ENTRY_FINAL_BIT 0x40000000
	198	uint32_t bpid_offset;
	199	#define SG_ENTRY_BPID_MASK 0x00FF0000
	200	#define SG_ENTRY_BPID_SHIFT 16
	201	#define SG_ENTRY_OFFSET_MASK 0x00001FFF
	202	#define SG_ENTRY_OFFSET_SHIFT 0
	203	};
	204
0200020b RC	205	#ifdef CONFIG_MX6
	206	/* CAAM Job Ring 0 Registers */
	207	/* Secure Memory Partition Owner register */
	208	#define SMCSJR_PO (3 << 6)
	209	/* JR Allocation Error */
	210	#define SMCSJR_AERR (3 << 12)
	211	/* Secure memory partition 0 page 0 owner register */
	212	#define CAAM_SMPO_0 CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC
	213	/* Secure memory command register */
	214	#define CAAM_SMCJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10f4
	215	/* Secure memory command status register */
	216	#define CAAM_SMCSJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10fc
	217	/* Secure memory access permissions register */
	218	#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
	219	/* Secure memory access group 2 register */
	220	#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
	221	/* Secure memory access group 1 register */
	222	#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)
	223
	224	/* Commands and macros for secure memory */
	225	#define CMD_PAGE_ALLOC 0x1
	226	#define CMD_PAGE_DEALLOC 0x2
	227	#define CMD_PART_DEALLOC 0x3
	228	#define CMD_INQUIRY 0x5
	229	#define CMD_COMPLETE (3 << 14)
	230	#define PAGE_AVAILABLE 0
	231	#define PAGE_OWNED (3 << 6)
	232	#define PAGE(x) (x << 16)
	233	#define PARTITION(x) (x << 8)
	234	#define PARTITION_OWNER(x) (0x3 << (x*2))
	235
	236	/* Address of secure 4kbyte pages */
	237	#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
	238	#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
	239	#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
	240	#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
	241
	242	#define JR_MID 2 /* Matches ROM configuration */
	243	#define KS_G1 (1 << JR_MID) /* CAAM only */
	244	#define PERM 0x0000B008 /* Clear on release, lock SMAP
	245	* lock SMAG group 1 Blob */
	246
	247	#define BLOB_SIZE(x) (x + 32 + 16) /* Blob buffer size */
	248
	249	/* HAB WRAPPED KEY header */
	250	#define WRP_HDR_SIZE 0x08
	251	#define HDR_TAG 0x81
	252	#define HDR_PAR 0x41
	253	/* HAB WRAPPED KEY Data */
	254	#define HAB_MOD 0x66
	255	#define HAB_ALG 0x55
	256	#define HAB_FLG 0x00
	257
	258	/* Partition and Page IDs */
	259	#define PARTITION_1 1
	260	#define PAGE_1 1
	261
	262	#define ERROR_IN_PAGE_ALLOC 1
	263	#define ECONSTRJDESC -1
	264
	265	#endif
	266
b9eebfad	267	int sec_init(void);
0200020b RC	268
	269	/* blob_dek:
	270	* Encapsulates the src in a secure blob and stores it dst
	271	* @src: reference to the plaintext
	272	* @dst: reference to the output adrress
	273	* @len: size in bytes of src
	274	* @return: 0 on success, error otherwise
	275	*/
	276	int blob_dek(const u8 src, u8 dst, u8 len);
	277
48ef0d2a RG	278	#endif
	279
	280	#endif /* __FSL_SEC_H */