projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 9dee205d | 2 | /* |
| 3 | * Freescale USB Controller | |
| 4 | * | |
| 5 | * Copyright 2013 Freescale Semiconductor, Inc. | |
| 9dee205d | 6 | */ |
| 7 | ||
| 8 | #ifndef _ASM_FSL_USB_H_ | |
| 9 | #define _ASM_FSL_USB_H_ | |
| 10 | ||
| 11 | #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE | |
| 12 | struct ccsr_usb_port_ctrl { | |
| 13 | u32 ctrl; | |
| 14 | u32 drvvbuscfg; | |
| 15 | u32 pwrfltcfg; | |
| 16 | u32 sts; | |
| 17 | u8 res_14[0xc]; | |
| 18 | u32 bistcfg; | |
| 19 | u32 biststs; | |
| 20 | u32 abistcfg; | |
| 21 | u32 abiststs; | |
| 22 | u8 res_30[0x10]; | |
| 23 | u32 xcvrprg; | |
| 24 | u32 anaprg; | |
| 25 | u32 anadrv; | |
| 26 | u32 anasts; | |
| 27 | }; | |
| 28 | ||
| 29 | struct ccsr_usb_phy { | |
| 30 | u32 id; | |
| 31 | struct ccsr_usb_port_ctrl port1; | |
| 32 | u8 res_50[0xc]; | |
| 33 | u32 tvr; | |
| 34 | u32 pllprg[4]; | |
| 35 | u8 res_70[0x4]; | |
| 36 | u32 anaccfg; | |
| 37 | u32 dbg; | |
| 38 | u8 res_7c[0x4]; | |
| 39 | struct ccsr_usb_port_ctrl port2; | |
| 40 | u8 res_dc[0x334]; | |
| 41 | }; | |
| 42 | ||
| 6e7df1d1 TR |
43 | #define CFG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) |
| 44 | #define CFG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) | |
| 45 | #define CFG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) | |
| 46 | #define CFG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) | |
| 47 | #define CFG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) | |
| d1c561cd | 48 | #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK |
| 6e7df1d1 TR |
49 | #define CFG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4) |
| 50 | #define CFG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16) | |
| 51 | #define CFG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20) | |
| d1c561cd | 52 | #endif |
| 6e7df1d1 TR |
53 | #define CFG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4) |
| 54 | #define CFG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) | |
| 55 | #define CFG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) | |
| 56 | #define CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7) | |
| 57 | #define CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4) | |
| 9c641a87 SG |
58 | |
| 59 | #define INC_DCNT_THRESHOLD_25MV (0 << 4) | |
| 60 | #define INC_DCNT_THRESHOLD_50MV (1 << 4) | |
| 61 | #define DEC_DCNT_THRESHOLD_25MV (2 << 4) | |
| 62 | #define DEC_DCNT_THRESHOLD_50MV (3 << 4) | |
| 9dee205d | 63 | #else |
| 64 | struct ccsr_usb_phy { | |
| 9c641a87 SG |
65 | u32 config1; |
| 66 | u32 config2; | |
| 67 | u32 config3; | |
| 68 | u32 config4; | |
| 69 | u32 config5; | |
| 70 | u32 status1; | |
| 9dee205d | 71 | u32 usb_enable_override; |
| 72 | u8 res[0xe4]; | |
| 73 | }; | |
| 6e7df1d1 TR |
74 | #define CFG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22) |
| 75 | #define CFG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20) | |
| 76 | #define CFG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13 | |
| 77 | #define CFG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16 | |
| 78 | #define CFG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0 | |
| 79 | #define CFG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3 | |
| 80 | #define CFG_SYS_FSL_USB_ENABLE_OVERRIDE 1 | |
| 81 | #define CFG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07 | |
| 9dee205d | 82 | #endif |
| 83 | ||
| c26c80a1 | 84 | /* USB Erratum Checking code */ |
| 92623672 SD |
85 | #if defined(CONFIG_PPC) || defined(CONFIG_ARM) |
| 86 | bool has_dual_phy(void); | |
| 4eaf7f52 | 87 | bool has_erratum_a005275(void); |
| 92623672 SD |
88 | bool has_erratum_a006261(void); |
| 89 | bool has_erratum_a007075(void); | |
| 90 | bool has_erratum_a007798(void); | |
| 91 | bool has_erratum_a007792(void); | |
| 92 | bool has_erratum_a005697(void); | |
| 93 | bool has_erratum_a004477(void); | |
| ef53b8c4 | 94 | bool has_erratum_a008751(void); |
| 4c043712 | 95 | bool has_erratum_a010151(void); |
| c26c80a1 | 96 | #endif |
| 9dee205d | 97 | #endif /*_ASM_FSL_USB_H_ */ |