projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2da0fc0d DE |
2 | /* |
| 3 | * (C) Copyright 2010 | |
| d38826a3 | 4 | * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
| 2da0fc0d DE |
5 | */ |
| 6 | ||
| 7 | #ifndef __GDSYS_FPGA_H | |
| 8 | #define __GDSYS_FPGA_H | |
| 9 | ||
| fe4a9675 | 10 | #ifdef CONFIG_GDSYS_LEGACY_DRIVERS |
| 255ef4d9 DE |
11 | int init_func_fpga(void); |
| 12 | ||
| 2da0fc0d DE |
13 | enum { |
| 14 | FPGA_STATE_DONE_FAILED = 1 << 0, | |
| 15 | FPGA_STATE_REFLECTION_FAILED = 1 << 1, | |
| 255ef4d9 | 16 | FPGA_STATE_PLATFORM = 1 << 2, |
| 2da0fc0d DE |
17 | }; |
| 18 | ||
| 19 | int get_fpga_state(unsigned dev); | |
| 2da0fc0d | 20 | |
| aba27acf DE |
21 | int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data); |
| 22 | int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data); | |
| 23 | ||
| 24 | extern struct ihs_fpga *fpga_ptr[]; | |
| 25 | ||
| 26 | #define FPGA_SET_REG(ix, fld, val) \ | |
| 27 | fpga_set_reg((ix), \ | |
| 28 | &fpga_ptr[ix]->fld, \ | |
| 29 | offsetof(struct ihs_fpga, fld), \ | |
| 30 | val) | |
| 31 | ||
| 32 | #define FPGA_GET_REG(ix, fld, val) \ | |
| 33 | fpga_get_reg((ix), \ | |
| 34 | &fpga_ptr[ix]->fld, \ | |
| 35 | offsetof(struct ihs_fpga, fld), \ | |
| 36 | val) | |
| fe4a9675 | 37 | #endif |
| aba27acf | 38 | |
| 0e60aa85 | 39 | struct ihs_gpio { |
| 2da0fc0d DE |
40 | u16 read; |
| 41 | u16 clear; | |
| 42 | u16 set; | |
| 0e60aa85 | 43 | }; |
| 2da0fc0d | 44 | |
| 0e60aa85 | 45 | struct ihs_i2c { |
| b46226bd DE |
46 | u16 interrupt_status; |
| 47 | u16 interrupt_enable; | |
| 2da0fc0d | 48 | u16 write_mailbox_ext; |
| b46226bd | 49 | u16 write_mailbox; |
| 2da0fc0d | 50 | u16 read_mailbox_ext; |
| b46226bd | 51 | u16 read_mailbox; |
| 0e60aa85 | 52 | }; |
| 2da0fc0d | 53 | |
| 0e60aa85 | 54 | struct ihs_osd { |
| 2da0fc0d DE |
55 | u16 version; |
| 56 | u16 features; | |
| 57 | u16 control; | |
| 58 | u16 xy_size; | |
| 52158e36 DE |
59 | u16 xy_scale; |
| 60 | u16 x_pos; | |
| 61 | u16 y_pos; | |
| 0e60aa85 | 62 | }; |
| 2da0fc0d | 63 | |
| 50dcf89d DE |
64 | struct ihs_mdio { |
| 65 | u16 control; | |
| 66 | u16 address_data; | |
| 67 | u16 rx_data; | |
| 68 | }; | |
| 69 | ||
| 70 | struct ihs_io_ep { | |
| 71 | u16 transmit_data; | |
| 72 | u16 rx_tx_control; | |
| 73 | u16 receive_data; | |
| 74 | u16 rx_tx_status; | |
| 75 | u16 reserved; | |
| 76 | u16 device_address; | |
| 77 | u16 target_address; | |
| 78 | }; | |
| 79 | ||
| 6e9e6c36 | 80 | #ifdef CONFIG_NEO |
| 0e60aa85 | 81 | struct ihs_fpga { |
| 6e9e6c36 DE |
82 | u16 reflection_low; /* 0x0000 */ |
| 83 | u16 versions; /* 0x0002 */ | |
| 84 | u16 fpga_features; /* 0x0004 */ | |
| 85 | u16 fpga_version; /* 0x0006 */ | |
| 86 | u16 reserved_0[8187]; /* 0x0008 */ | |
| 87 | u16 reflection_high; /* 0x3ffe */ | |
| 0e60aa85 | 88 | }; |
| 6e9e6c36 DE |
89 | #endif |
| 90 | ||
| d6918816 | 91 | #if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP) |
| 50dcf89d DE |
92 | struct ihs_fpga { |
| 93 | u16 reflection_low; /* 0x0000 */ | |
| 94 | u16 versions; /* 0x0002 */ | |
| 95 | u16 fpga_version; /* 0x0004 */ | |
| 96 | u16 fpga_features; /* 0x0006 */ | |
| 97 | u16 reserved_0[1]; /* 0x0008 */ | |
| 98 | u16 top_interrupt; /* 0x000a */ | |
| 7ed45d3d DE |
99 | u16 reserved_1[2]; /* 0x000c */ |
| 100 | u16 control; /* 0x0010 */ | |
| 101 | u16 extended_control; /* 0x0012 */ | |
| 0e60aa85 | 102 | struct ihs_gpio gpio; /* 0x0014 */ |
| 2da0fc0d | 103 | u16 mpc3w_control; /* 0x001a */ |
| 50dcf89d DE |
104 | u16 reserved_2[2]; /* 0x001c */ |
| 105 | struct ihs_io_ep ep; /* 0x0020 */ | |
| 106 | u16 reserved_3[9]; /* 0x002e */ | |
| 071be896 | 107 | struct ihs_i2c i2c0; /* 0x0040 */ |
| 50dcf89d | 108 | u16 reserved_4[10]; /* 0x004c */ |
| e50e8968 DE |
109 | u16 mc_int; /* 0x0060 */ |
| 110 | u16 mc_int_en; /* 0x0062 */ | |
| 111 | u16 mc_status; /* 0x0064 */ | |
| 112 | u16 mc_control; /* 0x0066 */ | |
| 113 | u16 mc_tx_data; /* 0x0068 */ | |
| 114 | u16 mc_tx_address; /* 0x006a */ | |
| 115 | u16 mc_tx_cmd; /* 0x006c */ | |
| 116 | u16 mc_res; /* 0x006e */ | |
| 117 | u16 mc_rx_cmd_status; /* 0x0070 */ | |
| 118 | u16 mc_rx_data; /* 0x0072 */ | |
| 50dcf89d | 119 | u16 reserved_5[69]; /* 0x0074 */ |
| 2da0fc0d | 120 | u16 reflection_high; /* 0x00fe */ |
| 7ed45d3d DE |
121 | struct ihs_osd osd0; /* 0x0100 */ |
| 122 | #ifdef CONFIG_SYS_OSD_DH | |
| 123 | u16 reserved_6[57]; /* 0x010e */ | |
| 124 | struct ihs_osd osd1; /* 0x0180 */ | |
| 125 | u16 reserved_7[9]; /* 0x018e */ | |
| 126 | struct ihs_i2c i2c1; /* 0x01a0 */ | |
| 127 | u16 reserved_8[1834]; /* 0x01ac */ | |
| 128 | u16 videomem0[2048]; /* 0x1000 */ | |
| 129 | u16 videomem1[2048]; /* 0x2000 */ | |
| 130 | #else | |
| 50dcf89d | 131 | u16 reserved_6[889]; /* 0x010e */ |
| 7ed45d3d DE |
132 | u16 videomem0[2048]; /* 0x0800 */ |
| 133 | #endif | |
| 0e60aa85 | 134 | }; |
| 2da0fc0d DE |
135 | #endif |
| 136 | ||
| a3f9d6c7 DE |
137 | #ifdef CONFIG_STRIDER_CPU |
| 138 | struct ihs_fpga { | |
| 139 | u16 reflection_low; /* 0x0000 */ | |
| 140 | u16 versions; /* 0x0002 */ | |
| 141 | u16 fpga_version; /* 0x0004 */ | |
| 142 | u16 fpga_features; /* 0x0006 */ | |
| 143 | u16 reserved_0[1]; /* 0x0008 */ | |
| 144 | u16 top_interrupt; /* 0x000a */ | |
| 145 | u16 reserved_1[3]; /* 0x000c */ | |
| 146 | u16 extended_control; /* 0x0012 */ | |
| 147 | struct ihs_gpio gpio; /* 0x0014 */ | |
| 148 | u16 mpc3w_control; /* 0x001a */ | |
| 149 | u16 reserved_2[2]; /* 0x001c */ | |
| 150 | struct ihs_io_ep ep; /* 0x0020 */ | |
| 151 | u16 reserved_3[9]; /* 0x002e */ | |
| 152 | u16 mc_int; /* 0x0040 */ | |
| 153 | u16 mc_int_en; /* 0x0042 */ | |
| 154 | u16 mc_status; /* 0x0044 */ | |
| 155 | u16 mc_control; /* 0x0046 */ | |
| 156 | u16 mc_tx_data; /* 0x0048 */ | |
| 157 | u16 mc_tx_address; /* 0x004a */ | |
| 158 | u16 mc_tx_cmd; /* 0x004c */ | |
| 159 | u16 mc_res; /* 0x004e */ | |
| 160 | u16 mc_rx_cmd_status; /* 0x0050 */ | |
| 161 | u16 mc_rx_data; /* 0x0052 */ | |
| 162 | u16 reserved_4[62]; /* 0x0054 */ | |
| 163 | struct ihs_i2c i2c0; /* 0x00d0 */ | |
| 164 | }; | |
| 165 | #endif | |
| 166 | ||
| 167 | #ifdef CONFIG_STRIDER_CON | |
| 168 | struct ihs_fpga { | |
| 169 | u16 reflection_low; /* 0x0000 */ | |
| 170 | u16 versions; /* 0x0002 */ | |
| 171 | u16 fpga_version; /* 0x0004 */ | |
| 172 | u16 fpga_features; /* 0x0006 */ | |
| 173 | u16 reserved_0[1]; /* 0x0008 */ | |
| 174 | u16 top_interrupt; /* 0x000a */ | |
| 175 | u16 reserved_1[4]; /* 0x000c */ | |
| 176 | struct ihs_gpio gpio; /* 0x0014 */ | |
| 177 | u16 mpc3w_control; /* 0x001a */ | |
| 178 | u16 reserved_2[2]; /* 0x001c */ | |
| 179 | struct ihs_io_ep ep; /* 0x0020 */ | |
| 180 | u16 reserved_3[9]; /* 0x002e */ | |
| 181 | struct ihs_i2c i2c0; /* 0x0040 */ | |
| 182 | u16 reserved_4[10]; /* 0x004c */ | |
| 183 | u16 mc_int; /* 0x0060 */ | |
| 184 | u16 mc_int_en; /* 0x0062 */ | |
| 185 | u16 mc_status; /* 0x0064 */ | |
| 186 | u16 mc_control; /* 0x0066 */ | |
| 187 | u16 mc_tx_data; /* 0x0068 */ | |
| 188 | u16 mc_tx_address; /* 0x006a */ | |
| 189 | u16 mc_tx_cmd; /* 0x006c */ | |
| 190 | u16 mc_res; /* 0x006e */ | |
| 191 | u16 mc_rx_cmd_status; /* 0x0070 */ | |
| 192 | u16 mc_rx_data; /* 0x0072 */ | |
| 193 | u16 reserved_5[70]; /* 0x0074 */ | |
| 7ed45d3d | 194 | struct ihs_osd osd0; /* 0x0100 */ |
| a3f9d6c7 | 195 | u16 reserved_6[889]; /* 0x010e */ |
| 7ed45d3d | 196 | u16 videomem0[2048]; /* 0x0800 */ |
| a3f9d6c7 DE |
197 | }; |
| 198 | #endif | |
| 199 | ||
| 2da0fc0d | 200 | #endif |