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a7240d1e MC |
1 | /* |
2 | * SiFive U series machine interface | |
3 | * | |
4 | * Copyright (c) 2017 SiFive, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #ifndef HW_SIFIVE_U_H | |
20 | #define HW_SIFIVE_U_H | |
21 | ||
5a7f76a3 | 22 | #include "hw/net/cadence_gem.h" |
ec150c7e | 23 | #include "hw/riscv/riscv_hart.h" |
20f41c86 | 24 | #include "hw/riscv/sifive_cpu.h" |
af14c840 | 25 | #include "hw/riscv/sifive_u_prci.h" |
5461c4fe | 26 | #include "hw/riscv/sifive_u_otp.h" |
5a7f76a3 | 27 | |
2308092b AF |
28 | #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" |
29 | #define RISCV_U_SOC(obj) \ | |
30 | OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC) | |
31 | ||
32 | typedef struct SiFiveUSoCState { | |
a7240d1e MC |
33 | /*< private >*/ |
34 | SysBusDevice parent_obj; | |
35 | ||
36 | /*< public >*/ | |
ecdfe393 BM |
37 | CPUClusterState e_cluster; |
38 | CPUClusterState u_cluster; | |
39 | RISCVHartArrayState e_cpus; | |
40 | RISCVHartArrayState u_cpus; | |
a7240d1e | 41 | DeviceState *plic; |
af14c840 | 42 | SiFiveUPRCIState prci; |
5461c4fe | 43 | SiFiveUOTPState otp; |
5a7f76a3 | 44 | CadenceGEMState gem; |
2308092b AF |
45 | } SiFiveUSoCState; |
46 | ||
687caef1 AF |
47 | #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") |
48 | #define RISCV_U_MACHINE(obj) \ | |
49 | OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) | |
50 | ||
2308092b AF |
51 | typedef struct SiFiveUState { |
52 | /*< private >*/ | |
687caef1 | 53 | MachineState parent_obj; |
2308092b AF |
54 | |
55 | /*< public >*/ | |
56 | SiFiveUSoCState soc; | |
687caef1 | 57 | |
a7240d1e MC |
58 | void *fdt; |
59 | int fdt_size; | |
fc41ae23 AF |
60 | |
61 | bool start_in_flash; | |
a7240d1e MC |
62 | } SiFiveUState; |
63 | ||
64 | enum { | |
65 | SIFIVE_U_DEBUG, | |
66 | SIFIVE_U_MROM, | |
67 | SIFIVE_U_CLINT, | |
a6902ef0 | 68 | SIFIVE_U_L2LIM, |
a7240d1e | 69 | SIFIVE_U_PLIC, |
af14c840 | 70 | SIFIVE_U_PRCI, |
a7240d1e MC |
71 | SIFIVE_U_UART0, |
72 | SIFIVE_U_UART1, | |
5461c4fe | 73 | SIFIVE_U_OTP, |
1b3a2308 | 74 | SIFIVE_U_FLASH0, |
5a7f76a3 | 75 | SIFIVE_U_DRAM, |
7b6bb66f BM |
76 | SIFIVE_U_GEM, |
77 | SIFIVE_U_GEM_MGMT | |
a7240d1e MC |
78 | }; |
79 | ||
80 | enum { | |
4b55bc2b BM |
81 | SIFIVE_U_UART0_IRQ = 4, |
82 | SIFIVE_U_UART1_IRQ = 5, | |
5a7f76a3 | 83 | SIFIVE_U_GEM_IRQ = 0x35 |
a7240d1e MC |
84 | }; |
85 | ||
2a8756ed | 86 | enum { |
e1724d09 | 87 | SIFIVE_U_HFCLK_FREQ = 33333333, |
81e94379 | 88 | SIFIVE_U_RTCCLK_FREQ = 1000000 |
2a8756ed MC |
89 | }; |
90 | ||
f3d47d58 | 91 | #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 |
ecdfe393 | 92 | #define SIFIVE_U_COMPUTE_CPU_COUNT 4 |
f3d47d58 | 93 | |
a7240d1e | 94 | #define SIFIVE_U_PLIC_HART_CONFIG "MS" |
0feb4a71 | 95 | #define SIFIVE_U_PLIC_NUM_SOURCES 54 |
a7240d1e | 96 | #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 |
0feb4a71 | 97 | #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04 |
a7240d1e MC |
98 | #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 |
99 | #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 | |
100 | #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 | |
101 | #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 | |
102 | #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 | |
103 | ||
a7240d1e | 104 | #endif |