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display/virtio: add edid support.
[thirdparty/qemu.git] / include / hw / virtio / virtio-gpu.h
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1/*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2.
11 * See the COPYING file in the top-level directory.
12 */
13
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14#ifndef HW_VIRTIO_GPU_H
15#define HW_VIRTIO_GPU_H
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16
17#include "qemu/queue.h"
18#include "ui/qemu-pixman.h"
19#include "ui/console.h"
20#include "hw/virtio/virtio.h"
8afc224f 21#include "qemu/log.h"
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22
23#include "standard-headers/linux/virtio_gpu.h"
a8bff79e 24
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25#define TYPE_VIRTIO_GPU "virtio-gpu-device"
26#define VIRTIO_GPU(obj) \
27 OBJECT_CHECK(VirtIOGPU, (obj), TYPE_VIRTIO_GPU)
28
29#define VIRTIO_ID_GPU 16
30
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31struct virtio_gpu_simple_resource {
32 uint32_t resource_id;
33 uint32_t width;
34 uint32_t height;
35 uint32_t format;
0c244e50 36 uint64_t *addrs;
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37 struct iovec *iov;
38 unsigned int iov_cnt;
39 uint32_t scanout_bitmask;
40 pixman_image_t *image;
9b7621bc 41 uint64_t hostmem;
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42 QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
43};
44
45struct virtio_gpu_scanout {
46 QemuConsole *con;
47 DisplaySurface *ds;
48 uint32_t width, height;
49 int x, y;
50 int invalidate;
51 uint32_t resource_id;
0c244e50 52 struct virtio_gpu_update_cursor cursor;
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53 QEMUCursor *current_cursor;
54};
55
56struct virtio_gpu_requested_state {
57 uint32_t width, height;
58 int x, y;
59};
60
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61enum virtio_gpu_conf_flags {
62 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
63 VIRTIO_GPU_FLAG_STATS_ENABLED,
1ed2cb32 64 VIRTIO_GPU_FLAG_EDID_ENABLED,
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65};
66
67#define virtio_gpu_virgl_enabled(_cfg) \
68 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
69#define virtio_gpu_stats_enabled(_cfg) \
70 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
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71#define virtio_gpu_edid_enabled(_cfg) \
72 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED))
9d9e1521 73
62232bf4 74struct virtio_gpu_conf {
9b7621bc 75 uint64_t max_hostmem;
62232bf4 76 uint32_t max_outputs;
9d9e1521 77 uint32_t flags;
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78 uint32_t xres;
79 uint32_t yres;
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80};
81
82struct virtio_gpu_ctrl_command {
83 VirtQueueElement elem;
84 VirtQueue *vq;
85 struct virtio_gpu_ctrl_hdr cmd_hdr;
86 uint32_t error;
87 bool finished;
88 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
89};
90
91typedef struct VirtIOGPU {
92 VirtIODevice parent_obj;
93
94 QEMUBH *ctrl_bh;
95 QEMUBH *cursor_bh;
96 VirtQueue *ctrl_vq;
97 VirtQueue *cursor_vq;
98
99 int enable;
100
62232bf4 101 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
3eb769fd 102 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
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103 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
104
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105 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
106 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
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107
108 struct virtio_gpu_conf conf;
9b7621bc 109 uint64_t hostmem;
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110 int enabled_output_bitmask;
111 struct virtio_gpu_config virtio_config;
112
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113 bool use_virgl_renderer;
114 bool renderer_inited;
c540128f 115 int renderer_blocked;
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116 QEMUTimer *fence_poll;
117 QEMUTimer *print_stats;
118
9d9e1521 119 uint32_t inflight;
62232bf4 120 struct {
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121 uint32_t max_inflight;
122 uint32_t requests;
123 uint32_t req_3d;
124 uint32_t bytes_3d;
125 } stats;
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126
127 Error *migration_blocker;
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128} VirtIOGPU;
129
130extern const GraphicHwOps virtio_gpu_ops;
131
132/* to share between PCI and VGA */
133#define DEFINE_VIRTIO_GPU_PCI_PROPERTIES(_state) \
134 DEFINE_PROP_BIT("ioeventfd", _state, flags, \
135 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, false), \
136 DEFINE_PROP_UINT32("vectors", _state, nvectors, 3)
137
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138#define VIRTIO_GPU_FILL_CMD(out) do { \
139 size_t s; \
140 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
141 &out, sizeof(out)); \
142 if (s != sizeof(out)) { \
143 qemu_log_mask(LOG_GUEST_ERROR, \
144 "%s: command size incorrect %zu vs %zu\n", \
145 __func__, s, sizeof(out)); \
146 return; \
147 } \
148 } while (0)
149
150/* virtio-gpu.c */
43e4dbe2 151void virtio_gpu_reset(VirtIODevice *vdev);
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152void virtio_gpu_ctrl_response(VirtIOGPU *g,
153 struct virtio_gpu_ctrl_command *cmd,
154 struct virtio_gpu_ctrl_hdr *resp,
155 size_t resp_len);
156void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
157 struct virtio_gpu_ctrl_command *cmd,
158 enum virtio_gpu_ctrl_type type);
159void virtio_gpu_get_display_info(VirtIOGPU *g,
160 struct virtio_gpu_ctrl_command *cmd);
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161void virtio_gpu_get_edid(VirtIOGPU *g,
162 struct virtio_gpu_ctrl_command *cmd);
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163int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
164 struct virtio_gpu_resource_attach_backing *ab,
62232bf4 165 struct virtio_gpu_ctrl_command *cmd,
0c244e50 166 uint64_t **addr, struct iovec **iov);
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167void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
168 struct iovec *iov, uint32_t count);
0c55a1cf 169void virtio_gpu_process_cmdq(VirtIOGPU *g);
62232bf4 170
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171/* virtio-gpu-3d.c */
172void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
173 struct virtio_gpu_ctrl_command *cmd);
174void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
175void virtio_gpu_virgl_reset(VirtIOGPU *g);
176int virtio_gpu_virgl_init(VirtIOGPU *g);
5643cc94 177int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g);
62232bf4 178#endif