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[thirdparty/u-boot.git] / include / imx8image.h
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1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8#ifndef _IMX8IMAGE_H_
9#define _IMX8IMAGE_H_
10
11#include <image.h>
12#include <inttypes.h>
13#include "imagetool.h"
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14
15#define __packed __attribute__((packed))
16
17#define IV_MAX_LEN 32
18#define HASH_MAX_LEN 64
19#define MAX_NUM_IMGS 6
20#define MAX_NUM_SRK_RECORDS 4
21
22#define IVT_HEADER_TAG_B0 0x87
23#define IVT_VERSION_B0 0x00
24
25#define IMG_FLAG_HASH_SHA256 0x000
26#define IMG_FLAG_HASH_SHA384 0x100
27#define IMG_FLAG_HASH_SHA512 0x200
28
29#define IMG_FLAG_ENCRYPTED_MASK 0x400
30#define IMG_FLAG_ENCRYPTED_SHIFT 0x0A
31
32#define IMG_FLAG_BOOTFLAGS_MASK 0xFFFF0000
33#define IMG_FLAG_BOOTFLAGS_SHIFT 0x10
34
35#define IMG_ARRAY_ENTRY_SIZE 128
36#define HEADER_IMG_ARRAY_OFFSET 0x10
37
38#define HASH_TYPE_SHA_256 256
39#define HASH_TYPE_SHA_384 384
40#define HASH_TYPE_SHA_512 512
41
42#define IMAGE_HASH_ALGO_DEFAULT 384
43#define IMAGE_PADDING_DEFAULT 0x1000
44
45#define DCD_ENTRY_ADDR_IN_SCFW 0x240
46
47#define CONTAINER_ALIGNMENT 0x400
48#define CONTAINER_FLAGS_DEFAULT 0x10
49#define CONTAINER_FUSE_DEFAULT 0x0
50
51#define SIGNATURE_BLOCK_HEADER_LENGTH 0x10
52
53#define MAX_NUM_OF_CONTAINER 2
54
55#define FIRST_CONTAINER_HEADER_LENGTH 0x400
56
57#define BOOT_IMG_META_MU_RID_SHIFT 10
58#define BOOT_IMG_META_PART_ID_SHIFT 20
59
60#define IMAGE_A35_DEFAULT_META(PART) (((PART == 0) ? \
61 PARTITION_ID_AP : PART) << \
62 BOOT_IMG_META_PART_ID_SHIFT | \
63 SC_R_MU_0A << \
64 BOOT_IMG_META_MU_RID_SHIFT | \
65 SC_R_A35_0)
66
67#define IMAGE_A53_DEFAULT_META(PART) (((PART == 0) ? \
68 PARTITION_ID_AP : PART) << \
69 BOOT_IMG_META_PART_ID_SHIFT | \
70 SC_R_MU_0A << \
71 BOOT_IMG_META_MU_RID_SHIFT | \
72 SC_R_A53_0)
73
74#define IMAGE_A72_DEFAULT_META(PART) (((PART == 0) ? \
75 PARTITION_ID_AP : PART) << \
76 BOOT_IMG_META_PART_ID_SHIFT | \
77 SC_R_MU_0A << \
78 BOOT_IMG_META_MU_RID_SHIFT | \
79 SC_R_A72_0)
80
81#define IMAGE_M4_0_DEFAULT_META(PART) (((PART == 0) ? \
82 PARTITION_ID_M4 : PART) << \
83 BOOT_IMG_META_PART_ID_SHIFT | \
84 SC_R_M4_0_MU_1A << \
85 BOOT_IMG_META_MU_RID_SHIFT | \
86 SC_R_M4_0_PID0)
87
88#define IMAGE_M4_1_DEFAULT_META(PART) (((PART == 0) ? \
89 PARTITION_ID_M4 : PART) << \
90 BOOT_IMG_META_PART_ID_SHIFT | \
91 SC_R_M4_1_MU_1A << \
92 BOOT_IMG_META_MU_RID_SHIFT | \
93 SC_R_M4_1_PID0)
94
95#define CONTAINER_IMAGE_ARRAY_START_OFFSET 0x2000
96
97typedef struct {
98 uint8_t version;
99 uint16_t length;
100 uint8_t tag;
101 uint16_t srk_table_offset;
102 uint16_t cert_offset;
103 uint16_t blob_offset;
104 uint16_t signature_offset;
105 uint32_t reserved;
106} __packed sig_blk_hdr_t;
107
108typedef struct {
109 uint32_t offset;
110 uint32_t size;
111 uint64_t dst;
112 uint64_t entry;
113 uint32_t hab_flags;
114 uint32_t meta;
115 uint8_t hash[HASH_MAX_LEN];
116 uint8_t iv[IV_MAX_LEN];
117} __packed boot_img_t;
118
119typedef struct {
120 uint8_t version;
121 uint16_t length;
122 uint8_t tag;
123 uint32_t flags;
124 uint16_t sw_version;
125 uint8_t fuse_version;
126 uint8_t num_images;
127 uint16_t sig_blk_offset;
128 uint16_t reserved;
129 boot_img_t img[MAX_NUM_IMGS];
130 sig_blk_hdr_t sig_blk_hdr;
131 uint32_t sigblk_size;
132 uint32_t padding;
133} __packed flash_header_v3_t;
134
135typedef struct {
136 flash_header_v3_t fhdr[MAX_NUM_OF_CONTAINER];
137} __packed imx_header_v3_t;
138
139struct image_array {
140 char *name;
141 unsigned int core_type;
142 unsigned int core_id;
143 unsigned int load_addr;
144};
145
146enum imx8image_cmd {
147 CMD_INVALID,
148 CMD_BOOT_FROM,
254c0080 149 CMD_DCD_SKIP,
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150 CMD_FUSE_VERSION,
151 CMD_SW_VERSION,
152 CMD_MSG_BLOCK,
153 CMD_FILEOFF,
154 CMD_FLAG,
155 CMD_APPEND,
156 CMD_PARTITION,
157 CMD_SOC_TYPE,
158 CMD_CONTAINER,
159 CMD_IMAGE,
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160 CMD_DATA,
161 CMD_DUMMY_V2X,
162 CMD_HOLD,
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163};
164
165enum imx8image_core_type {
166 CFG_CORE_INVALID,
167 CFG_SCU,
68a431e6 168 CFG_PWR,
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169 CFG_M40,
170 CFG_M41,
171 CFG_A35,
6ec65c85 172 CFG_A55,
a2b96ece 173 CFG_A53,
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174 CFG_A72,
175 CFG_M33,
176 CFG_OEI,
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177};
178
179enum imx8image_fld_types {
180 CFG_INVALID = -1,
181 CFG_COMMAND,
182 CFG_CORE_TYPE,
183 CFG_IMAGE_NAME,
184 CFG_LOAD_ADDR
185};
186
187typedef enum SOC_TYPE {
188 NONE = 0,
189 QX,
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190 QM,
191 ULP,
192 IMX9
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193} soc_type_t;
194
195typedef enum option_type {
196 NO_IMG = 0,
197 DCD,
198 SCFW,
199 SECO,
200 M40,
201 M41,
202 AP,
203 OUTPUT,
204 SCD,
205 CSF,
206 FLAG,
207 DEVICE,
208 NEW_CONTAINER,
209 APPEND,
210 DATA,
211 PARTITION,
212 FILEOFF,
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213 MSG_BLOCK,
214 SENTINEL,
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215 UPOWER,
216 OEI,
217 DUMMY_V2X,
218 HOLD,
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219} option_type_t;
220
221typedef struct {
222 option_type_t option;
223 char *filename;
224 uint64_t src;
225 uint64_t dst;
226 uint64_t entry;
227 uint64_t ext;
228} image_t;
229
230#define CORE_SC 1
231#define CORE_CM4_0 2
232#define CORE_CM4_1 3
233#define CORE_CA53 4
234#define CORE_CA35 4
235#define CORE_CA72 5
236#define CORE_SECO 6
5f28a659 237#define CORE_M33 7
a2b96ece 238
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239#define CORE_ULP_CM33 0x1
240#define CORE_ULP_CA35 0x2
241#define CORE_ULP_UPOWER 0x4
242#define CORE_ULP_SENTINEL 0x6
243
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244#define CORE_IMX95_M33P 0
245#define CORE_IMX95_A55C0 2
246
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247#define SC_R_OTP 357U
248#define SC_R_DEBUG 354U
249#define SC_R_ROM_0 236U
250
251#define MSG_DEBUG_EN SC_R_DEBUG
252#define MSG_FUSE SC_R_OTP
253#define MSG_FIELD SC_R_ROM_0
254
255#define IMG_TYPE_CSF 0x01 /* CSF image type */
256#define IMG_TYPE_SCD 0x02 /* SCD image type */
257#define IMG_TYPE_EXEC 0x03 /* Executable image type */
258#define IMG_TYPE_DATA 0x04 /* Data image type */
259#define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */
5f28a659 260#define IMG_TYPE_OEI 0x05 /* Optional Executable image type */
a2b96ece 261#define IMG_TYPE_SECO 0x06 /* SECO image type */
6ec65c85 262#define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */
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263#define IMG_TYPE_PROV 0x07 /* Provisioning image type */
264#define IMG_TYPE_DEK 0x08 /* DEK validation type */
5f28a659 265#define IMG_TYPE_V2X_DUMMY 0x0E /* V2X Dummy image */
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266
267#define IMG_TYPE_SHIFT 0
268#define IMG_TYPE_MASK 0x1f
269#define IMG_TYPE(x) (((x) & IMG_TYPE_MASK) >> IMG_TYPE_SHIFT)
270
271#define BOOT_IMG_FLAGS_CORE_MASK 0xF
272#define BOOT_IMG_FLAGS_CORE_SHIFT 0x04
273#define BOOT_IMG_FLAGS_CPU_RID_MASK 0x3FF0
274#define BOOT_IMG_FLAGS_CPU_RID_SHIFT 4
275#define BOOT_IMG_FLAGS_MU_RID_MASK 0xFFC000
276#define BOOT_IMG_FLAGS_MU_RID_SHIFT 14
277#define BOOT_IMG_FLAGS_PARTITION_ID_MASK 0x1F000000
278#define BOOT_IMG_FLAGS_PARTITION_ID_SHIFT 24
279
280/* Resource id used in scfw */
281#define SC_R_A35_0 508
282#define SC_R_A53_0 1
283#define SC_R_A72_0 6
284#define SC_R_MU_0A 213
285#define SC_R_M4_0_PID0 278
286#define SC_R_M4_0_MU_1A 297
287#define SC_R_M4_1_PID0 298
288#define SC_R_M4_1_MU_1A 317
289#define PARTITION_ID_M4 0
290#define PARTITION_ID_AP 1
291
292#define IMG_STACK_SIZE 32
293
294#define append(p, s, l) do { \
295 memcpy((p), (uint8_t *)(s), (l)); (p) += (l); \
296 } while (0)
297
298#endif