[people/ms/u-boot.git] / include / lcd.h

/*
 * MPC823 and PXA LCD Controller
 *
 * Modeled after video interface by Paolo Scaffardi
 *
 *
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _LCD_H_
#define _LCD_H_

extern char lcd_is_enabled;

extern int lcd_line_length;

extern struct vidinfo panel_info;

void lcd_ctrl_init(void *lcdbase);
void lcd_enable(void);
int board_splash_screen_prepare(void);

/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue);
void lcd_initcolregs(void);

int lcd_getfgcolor(void);

/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
int bmp_display(ulong addr, int x, int y);

/**
 * Set whether we need to flush the dcache when changing the LCD image. This
 * defaults to off.
 *
 * @param flush		non-zero to flush cache after update, 0 to skip
 */
void lcd_set_flush_dcache(int flush);

#if defined CONFIG_MPC823
/*
 * LCD controller stucture for MPC823 CPU
 */
typedef struct vidinfo {
	ushort	vl_col;		/* Number of columns (i.e. 640) */
	ushort	vl_row;		/* Number of rows (i.e. 480) */
	ushort	vl_width;	/* Width of display area in millimeters */
	ushort	vl_height;	/* Height of display area in millimeters */

	/* LCD configuration register */
	u_char	vl_clkp;	/* Clock polarity */
	u_char	vl_oep;		/* Output Enable polarity */
	u_char	vl_hsp;		/* Horizontal Sync polarity */
	u_char	vl_vsp;		/* Vertical Sync polarity */
	u_char	vl_dp;		/* Data polarity */
	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
	u_char	vl_tft;		/* 0 = passive, 1 = TFT */

	/* Horizontal control register. Timing from data sheet */
	ushort	vl_wbl;		/* Wait between lines */

	/* Vertical control register */
	u_char	vl_vpw;		/* Vertical sync pulse width */
	u_char	vl_lcdac;	/* LCD AC timing */
	u_char	vl_wbf;		/* Wait between frames */
} vidinfo_t;

#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
	defined CONFIG_CPU_MONAHANS
/*
 * PXA LCD DMA descriptor
 */
struct pxafb_dma_descriptor {
	u_long	fdadr;		/* Frame descriptor address register */
	u_long	fsadr;		/* Frame source address register */
	u_long	fidr;		/* Frame ID register */
	u_long	ldcmd;		/* Command register */
};

/*
 * PXA LCD info
 */
struct pxafb_info {

	/* Misc registers */
	u_long	reg_lccr3;
	u_long	reg_lccr2;
	u_long	reg_lccr1;
	u_long	reg_lccr0;
	u_long	fdadr0;
	u_long	fdadr1;

	/* DMA descriptors */
	struct	pxafb_dma_descriptor *	dmadesc_fblow;
	struct	pxafb_dma_descriptor *	dmadesc_fbhigh;
	struct	pxafb_dma_descriptor *	dmadesc_palette;

	u_long	screen;		/* physical address of frame buffer */
	u_long	palette;	/* physical address of palette memory */
	u_int	palette_size;
};

/*
 * LCD controller stucture for PXA CPU
 */
typedef struct vidinfo {
	ushort	vl_col;		/* Number of columns (i.e. 640) */
	ushort	vl_row;		/* Number of rows (i.e. 480) */
	ushort	vl_width;	/* Width of display area in millimeters */
	ushort	vl_height;	/* Height of display area in millimeters */

	/* LCD configuration register */
	u_char	vl_clkp;	/* Clock polarity */
	u_char	vl_oep;		/* Output Enable polarity */
	u_char	vl_hsp;		/* Horizontal Sync polarity */
	u_char	vl_vsp;		/* Vertical Sync polarity */
	u_char	vl_dp;		/* Data polarity */
	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
	u_char	vl_tft;		/* 0 = passive, 1 = TFT */

	/* Horizontal control register. Timing from data sheet */
	ushort	vl_hpw;		/* Horz sync pulse width */
	u_char	vl_blw;		/* Wait before of line */
	u_char	vl_elw;		/* Wait end of line */

	/* Vertical control register. */
	u_char	vl_vpw;		/* Vertical sync pulse width */
	u_char	vl_bfw;		/* Wait before of frame */
	u_char	vl_efw;		/* Wait end of frame */

	/* PXA LCD controller params */
	struct	pxafb_info pxa;
} vidinfo_t;

#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)

typedef struct vidinfo {
	ushort vl_col;		/* Number of columns (i.e. 640) */
	ushort vl_row;		/* Number of rows (i.e. 480) */
	u_long vl_clk;	/* pixel clock in ps    */

	/* LCD configuration register */
	u_long vl_sync;		/* Horizontal / vertical sync */
	u_long vl_bpix;		/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
	u_long vl_tft;		/* 0 = passive, 1 = TFT */
	u_long vl_cont_pol_low;	/* contrast polarity is low */
	u_long vl_clk_pol;	/* clock polarity */

	/* Horizontal control register. */
	u_long vl_hsync_len;	/* Length of horizontal sync */
	u_long vl_left_margin;	/* Time from sync to picture */
	u_long vl_right_margin;	/* Time from picture to sync */

	/* Vertical control register. */
	u_long vl_vsync_len;	/* Length of vertical sync */
	u_long vl_upper_margin;	/* Time from sync to picture */
	u_long vl_lower_margin;	/* Time from picture to sync */

	u_long	mmio;		/* Memory mapped registers */
} vidinfo_t;

#elif defined(CONFIG_EXYNOS_FB)

enum {
	FIMD_RGB_INTERFACE = 1,
	FIMD_CPU_INTERFACE = 2,
};

enum exynos_fb_rgb_mode_t {
	MODE_RGB_P = 0,
	MODE_BGR_P = 1,
	MODE_RGB_S = 2,
	MODE_BGR_S = 3,
};

typedef struct vidinfo {
	ushort vl_col;		/* Number of columns (i.e. 640) */
	ushort vl_row;		/* Number of rows (i.e. 480) */
	ushort vl_width;	/* Width of display area in millimeters */
	ushort vl_height;	/* Height of display area in millimeters */

	/* LCD configuration register */
	u_char vl_freq;		/* Frequency */
	u_char vl_clkp;		/* Clock polarity */
	u_char vl_oep;		/* Output Enable polarity */
	u_char vl_hsp;		/* Horizontal Sync polarity */
	u_char vl_vsp;		/* Vertical Sync polarity */
	u_char vl_dp;		/* Data polarity */
	u_char vl_bpix;		/* Bits per pixel */

	/* Horizontal control register. Timing from data sheet */
	u_char vl_hspw;		/* Horz sync pulse width */
	u_char vl_hfpd;		/* Wait before of line */
	u_char vl_hbpd;		/* Wait end of line */

	/* Vertical control register. */
	u_char	vl_vspw;	/* Vertical sync pulse width */
	u_char	vl_vfpd;	/* Wait before of frame */
	u_char	vl_vbpd;	/* Wait end of frame */
	u_char  vl_cmd_allow_len; /* Wait end of frame */

	unsigned int win_id;
	unsigned int init_delay;
	unsigned int power_on_delay;
	unsigned int reset_delay;
	unsigned int interface_mode;
	unsigned int mipi_enabled;
	unsigned int dp_enabled;
	unsigned int cs_setup;
	unsigned int wr_setup;
	unsigned int wr_act;
	unsigned int wr_hold;
	unsigned int logo_on;
	unsigned int logo_width;
	unsigned int logo_height;
	unsigned long logo_addr;
	unsigned int rgb_mode;
	unsigned int resolution;

	/* parent clock name(MPLL, EPLL or VPLL) */
	unsigned int pclk_name;
	/* ratio value for source clock from parent clock. */
	unsigned int sclk_div;

	unsigned int dual_lcd_enabled;
} vidinfo_t;

void init_panel_info(vidinfo_t *vid);

#else

typedef struct vidinfo {
	ushort	vl_col;		/* Number of columns (i.e. 160) */
	ushort	vl_row;		/* Number of rows (i.e. 100) */

	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */

	ushort	*cmap;		/* Pointer to the colormap */

	void	*priv;		/* Pointer to driver-specific data */
} vidinfo_t;

#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */

extern vidinfo_t panel_info;

/* Video functions */

#if defined(CONFIG_RBC823)
void	lcd_disable(void);
#endif

void	lcd_putc(const char c);
void	lcd_puts(const char *s);
void	lcd_printf(const char *fmt, ...);
void	lcd_clear(void);
int	lcd_display_bitmap(ulong bmp_image, int x, int y);

/**
 * Get the width of the LCD in pixels
 *
 * @return width of LCD in pixels
 */
int lcd_get_pixel_width(void);

/**
 * Get the height of the LCD in pixels
 *
 * @return height of LCD in pixels
 */
int lcd_get_pixel_height(void);

/**
 * Get the number of text lines/rows on the LCD
 *
 * @return number of rows
 */
int lcd_get_screen_rows(void);

/**
 * Get the number of text columns on the LCD
 *
 * @return number of columns
 */
int lcd_get_screen_columns(void);

/**
 * Set the position of the text cursor
 *
 * @param col	Column to place cursor (0 = left side)
 * @param row	Row to place cursor (0 = top line)
 */
void lcd_position_cursor(unsigned col, unsigned row);

/* Allow boards to customize the information displayed */
void lcd_show_board_info(void);

/* Return the size of the LCD frame buffer, and the line length */
int lcd_get_size(int *line_length);

/************************************************************************/
/* ** BITMAP DISPLAY SUPPORT						*/
/************************************************************************/
#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
# include <bmp_layout.h>
# include <asm/byteorder.h>
#endif

/*
 *  Information about displays we are using. This is for configuring
 *  the LCD controller and memory allocation. Someone has to know what
 *  is connected, as we can't autodetect anything.
 */
#define CONFIG_SYS_HIGH	0	/* Pins are active high			*/
#define CONFIG_SYS_LOW	1	/* Pins are active low			*/

#define LCD_MONOCHROME	0
#define LCD_COLOR2	1
#define LCD_COLOR4	2
#define LCD_COLOR8	3
#define LCD_COLOR16	4

/*----------------------------------------------------------------------*/
#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
# define LCD_INFO_X		0
# define LCD_INFO_Y		(BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
#elif defined(CONFIG_LCD_LOGO)
# define LCD_INFO_X		(BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH)
# define LCD_INFO_Y		VIDEO_FONT_HEIGHT
#else
# define LCD_INFO_X		VIDEO_FONT_WIDTH
# define LCD_INFO_Y		VIDEO_FONT_HEIGHT
#endif

/* Default to 8bpp if bit depth not specified */
#ifndef LCD_BPP
# define LCD_BPP			LCD_COLOR8
#endif
#ifndef LCD_DF
# define LCD_DF			1
#endif

/* Calculate nr. of bits per pixel  and nr. of colors */
#define NBITS(bit_code)		(1 << (bit_code))
#define NCOLORS(bit_code)	(1 << NBITS(bit_code))

/************************************************************************/
/* ** CONSOLE CONSTANTS							*/
/************************************************************************/
#if LCD_BPP == LCD_MONOCHROME

/*
 * Simple black/white definitions
 */
# define CONSOLE_COLOR_BLACK	0
# define CONSOLE_COLOR_WHITE	1	/* Must remain last / highest	*/

#elif LCD_BPP == LCD_COLOR8

/*
 * 8bpp color definitions
 */
# define CONSOLE_COLOR_BLACK	0
# define CONSOLE_COLOR_RED	1
# define CONSOLE_COLOR_GREEN	2
# define CONSOLE_COLOR_YELLOW	3
# define CONSOLE_COLOR_BLUE	4
# define CONSOLE_COLOR_MAGENTA	5
# define CONSOLE_COLOR_CYAN	6
# define CONSOLE_COLOR_GREY	14
# define CONSOLE_COLOR_WHITE	15	/* Must remain last / highest	*/

#else

/*
 * 16bpp color definitions
 */
# define CONSOLE_COLOR_BLACK	0x0000
# define CONSOLE_COLOR_WHITE	0xffff	/* Must remain last / highest	*/

#endif /* color definitions */

/************************************************************************/
#ifndef PAGE_SIZE
# define PAGE_SIZE	4096
#endif

/************************************************************************/

#endif	/* _LCD_H_ */
Commit	Line	Data
fe8c2806	1	/*
8655b6f8	2	* MPC823 and PXA LCD Controller
fe8c2806 WD	3	*
	4	* Modeled after video interface by Paolo Scaffardi
	5	*
	6	*
	7	* (C) Copyright 2001
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
8655b6f8	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
fe8c2806 WD	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#ifndef _LCD_H_
	30	#define _LCD_H_
	31
682011ff WD	32	extern char lcd_is_enabled;
682011ff WD	33
8655b6f8	34	extern int lcd_line_length;
8655b6f8	35
6111722a AR	36	extern struct vidinfo panel_info;
6111722a AR	37
6b035141 JH	38	void lcd_ctrl_init(void *lcdbase);
	39	void lcd_enable(void);
	40	int board_splash_screen_prepare(void);
6111722a AR	41
6111722a AR	42	/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
6b035141 JH	43	void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue);
6b035141 JH	44	void lcd_initcolregs(void);
6111722a	45
6b035141	46	int lcd_getfgcolor(void);
6111722a AR	47
6111722a AR	48	/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
6b035141 JH	49	struct bmp_image gunzip_bmp(unsigned long addr, unsigned long lenp);
6b035141 JH	50	int bmp_display(ulong addr, int x, int y);
8655b6f8	51
9a8efc46 SG	52	/**
	53	* Set whether we need to flush the dcache when changing the LCD image. This
	54	* defaults to off.
	55	*
	56	* @param flush non-zero to flush cache after update, 0 to skip
	57	*/
	58	void lcd_set_flush_dcache(int flush);
	59
8655b6f8 WD	60	#if defined CONFIG_MPC823
	61	/*
	62	* LCD controller stucture for MPC823 CPU
	63	*/
	64	typedef struct vidinfo {
	65	ushort vl_col; /* Number of columns (i.e. 640) */
	66	ushort vl_row; /* Number of rows (i.e. 480) */
	67	ushort vl_width; /* Width of display area in millimeters */
	68	ushort vl_height; /* Height of display area in millimeters */
	69
	70	/* LCD configuration register */
	71	u_char vl_clkp; /* Clock polarity */
	72	u_char vl_oep; /* Output Enable polarity */
	73	u_char vl_hsp; /* Horizontal Sync polarity */
	74	u_char vl_vsp; /* Vertical Sync polarity */
	75	u_char vl_dp; /* Data polarity */
	76	u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
	77	u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
	78	u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
	79	u_char vl_clor; /* Color, 0 = mono, 1 = color */
	80	u_char vl_tft; /* 0 = passive, 1 = TFT */
	81
	82	/* Horizontal control register. Timing from data sheet */
	83	ushort vl_wbl; /* Wait between lines */
	84
	85	/* Vertical control register */
	86	u_char vl_vpw; /* Vertical sync pulse width */
	87	u_char vl_lcdac; /* LCD AC timing */
	88	u_char vl_wbf; /* Wait between frames */
	89	} vidinfo_t;
	90
abc20aba MV	91	#elif defined(CONFIG_CPU_PXA25X) \|\| defined(CONFIG_CPU_PXA27X) \|\| \
abc20aba MV	92	defined CONFIG_CPU_MONAHANS
8655b6f8 WD	93	/*
	94	* PXA LCD DMA descriptor
	95	*/
	96	struct pxafb_dma_descriptor {
	97	u_long fdadr; /* Frame descriptor address register */
	98	u_long fsadr; /* Frame source address register */
	99	u_long fidr; /* Frame ID register */
	100	u_long ldcmd; /* Command register */
	101	};
	102
	103	/*
	104	* PXA LCD info
	105	*/
	106	struct pxafb_info {
	107
	108	/* Misc registers */
	109	u_long reg_lccr3;
	110	u_long reg_lccr2;
	111	u_long reg_lccr1;
	112	u_long reg_lccr0;
	113	u_long fdadr0;
	114	u_long fdadr1;
	115
	116	/* DMA descriptors */
	117	struct pxafb_dma_descriptor * dmadesc_fblow;
	118	struct pxafb_dma_descriptor * dmadesc_fbhigh;
	119	struct pxafb_dma_descriptor * dmadesc_palette;
	120
	121	u_long screen; /* physical address of frame buffer */
	122	u_long palette; /* physical address of palette memory */
	123	u_int palette_size;
	124	};
	125
	126	/*
	127	* LCD controller stucture for PXA CPU
	128	*/
	129	typedef struct vidinfo {
	130	ushort vl_col; /* Number of columns (i.e. 640) */
	131	ushort vl_row; /* Number of rows (i.e. 480) */
	132	ushort vl_width; /* Width of display area in millimeters */
	133	ushort vl_height; /* Height of display area in millimeters */
	134
	135	/* LCD configuration register */
	136	u_char vl_clkp; /* Clock polarity */
	137	u_char vl_oep; /* Output Enable polarity */
	138	u_char vl_hsp; /* Horizontal Sync polarity */
	139	u_char vl_vsp; /* Vertical Sync polarity */
	140	u_char vl_dp; /* Data polarity */
	141	u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
	142	u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
	143	u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
	144	u_char vl_clor; /* Color, 0 = mono, 1 = color */
	145	u_char vl_tft; /* 0 = passive, 1 = TFT */
	146
	147	/* Horizontal control register. Timing from data sheet */
	148	ushort vl_hpw; /* Horz sync pulse width */
	149	u_char vl_blw; /* Wait before of line */
	150	u_char vl_elw; /* Wait end of line */
	151
	152	/* Vertical control register. */
	153	u_char vl_vpw; /* Vertical sync pulse width */
	154	u_char vl_bfw; /* Wait before of frame */
	155	u_char vl_efw; /* Wait end of frame */
	156
157	/* PXA LCD controller params */
158	struct pxafb_info pxa;
159	} vidinfo_t;
160
f6b690e6	161	#elif defined(CONFIG_ATMEL_LCD) \|\| defined(CONFIG_ATMEL_HLCD)
39cf4804 SP	162
39cf4804 SP	163	typedef struct vidinfo {
78459123 MV	164	ushort vl_col; /* Number of columns (i.e. 640) */
78459123 MV	165	ushort vl_row; /* Number of rows (i.e. 480) */
39cf4804 SP	166	u_long vl_clk; /* pixel clock in ps */
	167
	168	/* LCD configuration register */
	169	u_long vl_sync; /* Horizontal / vertical sync */
	170	u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
	171	u_long vl_tft; /* 0 = passive, 1 = TFT */
cdfcedbf	172	u_long vl_cont_pol_low; /* contrast polarity is low */
f6b690e6	173	u_long vl_clk_pol; /* clock polarity */
39cf4804 SP	174
	175	/* Horizontal control register. */
	176	u_long vl_hsync_len; /* Length of horizontal sync */
	177	u_long vl_left_margin; /* Time from sync to picture */
	178	u_long vl_right_margin; /* Time from picture to sync */
	179
	180	/* Vertical control register. */
	181	u_long vl_vsync_len; /* Length of vertical sync */
	182	u_long vl_upper_margin; /* Time from sync to picture */
	183	u_long vl_lower_margin; /* Time from picture to sync */
	184
	185	u_long mmio; /* Memory mapped registers */
	186	} vidinfo_t;
	187
559a05cc DL	188	#elif defined(CONFIG_EXYNOS_FB)
	189
	190	enum {
	191	FIMD_RGB_INTERFACE = 1,
	192	FIMD_CPU_INTERFACE = 2,
	193	};
	194
90464971 DL	195	enum exynos_fb_rgb_mode_t {
	196	MODE_RGB_P = 0,
	197	MODE_BGR_P = 1,
	198	MODE_RGB_S = 2,
	199	MODE_BGR_S = 3,
	200	};
	201
559a05cc DL	202	typedef struct vidinfo {
	203	ushort vl_col; /* Number of columns (i.e. 640) */
	204	ushort vl_row; /* Number of rows (i.e. 480) */
	205	ushort vl_width; /* Width of display area in millimeters */
	206	ushort vl_height; /* Height of display area in millimeters */
	207
	208	/* LCD configuration register */
	209	u_char vl_freq; /* Frequency */
	210	u_char vl_clkp; /* Clock polarity */
	211	u_char vl_oep; /* Output Enable polarity */
	212	u_char vl_hsp; /* Horizontal Sync polarity */
	213	u_char vl_vsp; /* Vertical Sync polarity */
	214	u_char vl_dp; /* Data polarity */
	215	u_char vl_bpix; /* Bits per pixel */
	216
	217	/* Horizontal control register. Timing from data sheet */
	218	u_char vl_hspw; /* Horz sync pulse width */
	219	u_char vl_hfpd; /* Wait before of line */
	220	u_char vl_hbpd; /* Wait end of line */
	221
	222	/* Vertical control register. */
	223	u_char vl_vspw; /* Vertical sync pulse width */
	224	u_char vl_vfpd; /* Wait before of frame */
	225	u_char vl_vbpd; /* Wait end of frame */
	226	u_char vl_cmd_allow_len; /* Wait end of frame */
	227
559a05cc DL	228	unsigned int win_id;
	229	unsigned int init_delay;
	230	unsigned int power_on_delay;
	231	unsigned int reset_delay;
	232	unsigned int interface_mode;
	233	unsigned int mipi_enabled;
5addfcfc	234	unsigned int dp_enabled;
559a05cc DL	235	unsigned int cs_setup;
	236	unsigned int wr_setup;
	237	unsigned int wr_act;
	238	unsigned int wr_hold;
90464971 DL	239	unsigned int logo_on;
	240	unsigned int logo_width;
	241	unsigned int logo_height;
	242	unsigned long logo_addr;
	243	unsigned int rgb_mode;
	244	unsigned int resolution;
559a05cc DL	245
	246	/* parent clock name(MPLL, EPLL or VPLL) */
	247	unsigned int pclk_name;
	248	/* ratio value for source clock from parent clock. */
	249	unsigned int sclk_div;
	250
	251	unsigned int dual_lcd_enabled;
559a05cc DL	252	} vidinfo_t;
	253
	254	void init_panel_info(vidinfo_t *vid);
	255
b245e65e GL	256	#else
	257
	258	typedef struct vidinfo {
	259	ushort vl_col; /* Number of columns (i.e. 160) */
	260	ushort vl_row; /* Number of rows (i.e. 100) */
	261
	262	u_char vl_bpix; /* Bits per pixel, 0 = 1 */
	263
	264	ushort cmap; / Pointer to the colormap */
	265
	266	void priv; / Pointer to driver-specific data */
	267	} vidinfo_t;
	268
abc20aba	269	#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
8655b6f8	270
60e97419 AR	271	extern vidinfo_t panel_info;
60e97419 AR	272
fe8c2806 WD	273	/* Video functions */
fe8c2806 WD	274
8655b6f8	275	#if defined(CONFIG_RBC823)
6b035141	276	void lcd_disable(void);
8655b6f8 WD	277	#endif
8655b6f8 WD	278
6b035141 JH	279	void lcd_putc(const char c);
	280	void lcd_puts(const char *s);
	281	void lcd_printf(const char *fmt, ...);
02110903 CLC	282	void lcd_clear(void);
02110903 CLC	283	int lcd_display_bitmap(ulong bmp_image, int x, int y);
fe8c2806	284
395166cf VB	285	/**
	286	* Get the width of the LCD in pixels
	287	*
	288	* @return width of LCD in pixels
	289	*/
	290	int lcd_get_pixel_width(void);
	291
	292	/**
	293	* Get the height of the LCD in pixels
	294	*
	295	* @return height of LCD in pixels
	296	*/
	297	int lcd_get_pixel_height(void);
	298
	299	/**
	300	* Get the number of text lines/rows on the LCD
	301	*
	302	* @return number of rows
	303	*/
	304	int lcd_get_screen_rows(void);
	305
	306	/**
	307	* Get the number of text columns on the LCD
	308	*
	309	* @return number of columns
	310	*/
	311	int lcd_get_screen_columns(void);
	312
	313	/**
	314	* Set the position of the text cursor
	315	*
	316	* @param col Column to place cursor (0 = left side)
	317	* @param row Row to place cursor (0 = top line)
	318	*/
	319	void lcd_position_cursor(unsigned col, unsigned row);
	320
6b59e03e HS	321	/* Allow boards to customize the information displayed */
6b59e03e HS	322	void lcd_show_board_info(void);
8655b6f8	323
676d319e SG	324	/* Return the size of the LCD frame buffer, and the line length */
	325	int lcd_get_size(int *line_length);
	326
8655b6f8 WD	327	/************************************************************************/
	328	/* ** BITMAP DISPLAY SUPPORT */
	329	/************************************************************************/
639221c7	330	#if defined(CONFIG_CMD_BMP) \|\| defined(CONFIG_SPLASH_SCREEN)
8655b6f8 WD	331	# include <bmp_layout.h>
8655b6f8 WD	332	# include <asm/byteorder.h>
639221c7	333	#endif
8655b6f8	334
8655b6f8 WD	335	/*
	336	* Information about displays we are using. This is for configuring
	337	* the LCD controller and memory allocation. Someone has to know what
	338	* is connected, as we can't autodetect anything.
	339	*/
6d0f6bcf	340	#define CONFIG_SYS_HIGH 0 /* Pins are active high */
6b035141	341	#define CONFIG_SYS_LOW 1 /* Pins are active low */
8655b6f8 WD	342
	343	#define LCD_MONOCHROME 0
	344	#define LCD_COLOR2 1
	345	#define LCD_COLOR4 2
	346	#define LCD_COLOR8 3
	347	#define LCD_COLOR16 4
	348
	349	/----------------------------------------------------------------------/
88804d19	350	#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
8655b6f8 WD	351	# define LCD_INFO_X 0
	352	# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
	353	#elif defined(CONFIG_LCD_LOGO)
	354	# define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH)
6b035141	355	# define LCD_INFO_Y VIDEO_FONT_HEIGHT
8655b6f8	356	#else
6b035141 JH	357	# define LCD_INFO_X VIDEO_FONT_WIDTH
6b035141 JH	358	# define LCD_INFO_Y VIDEO_FONT_HEIGHT
8655b6f8 WD	359	#endif
	360
	361	/* Default to 8bpp if bit depth not specified */
	362	#ifndef LCD_BPP
	363	# define LCD_BPP LCD_COLOR8
	364	#endif
	365	#ifndef LCD_DF
	366	# define LCD_DF 1
	367	#endif
	368
	369	/* Calculate nr. of bits per pixel and nr. of colors */
	370	#define NBITS(bit_code) (1 << (bit_code))
	371	#define NCOLORS(bit_code) (1 << NBITS(bit_code))
	372
	373	/************************************************************************/
	374	/* ** CONSOLE CONSTANTS */
	375	/************************************************************************/
	376	#if LCD_BPP == LCD_MONOCHROME
	377
	378	/*
	379	* Simple black/white definitions
	380	*/
	381	# define CONSOLE_COLOR_BLACK 0
	382	# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */
	383
	384	#elif LCD_BPP == LCD_COLOR8
	385
	386	/*
	387	* 8bpp color definitions
	388	*/
	389	# define CONSOLE_COLOR_BLACK 0
	390	# define CONSOLE_COLOR_RED 1
	391	# define CONSOLE_COLOR_GREEN 2
	392	# define CONSOLE_COLOR_YELLOW 3
	393	# define CONSOLE_COLOR_BLUE 4
	394	# define CONSOLE_COLOR_MAGENTA 5
	395	# define CONSOLE_COLOR_CYAN 6
	396	# define CONSOLE_COLOR_GREY 14
	397	# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
	398
	399	#else
	400
	401	/*
	402	* 16bpp color definitions
	403	*/
	404	# define CONSOLE_COLOR_BLACK 0x0000
	405	# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
	406
	407	#endif /* color definitions */
	408
8655b6f8 WD	409	/************************************************************************/
	410	#ifndef PAGE_SIZE
	411	# define PAGE_SIZE 4096
	412	#endif
	413
8655b6f8 WD	414	/************************************************************************/
	415
	416	#endif /* _LCD_H_ */