[thirdparty/linux.git] / include / linux / cper.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * UEFI Common Platform Error Record
 *
 * Copyright (C) 2010, Intel Corp.
 *	Author: Huang Ying <ying.huang@intel.com>
 */

#ifndef LINUX_CPER_H
#define LINUX_CPER_H

#include <linux/uuid.h>
#include <linux/trace_seq.h>

/* CPER record signature and the size */
#define CPER_SIG_RECORD				"CPER"
#define CPER_SIG_SIZE				4
/* Used in signature_end field in struct cper_record_header */
#define CPER_SIG_END				0xffffffff

/*
 * CPER record header revision, used in revision field in struct
 * cper_record_header
 */
#define CPER_RECORD_REV				0x0100

/*
 * CPER record length contains the CPER fields which are relevant for further
 * handling of a memory error in userspace (we don't carry all the fields
 * defined in the UEFI spec because some of them don't make any sense.)
 * Currently, a length of 256 should be more than enough.
 */
#define CPER_REC_LEN					256
/*
 * Severity definition for error_severity in struct cper_record_header
 * and section_severity in struct cper_section_descriptor
 */
enum {
	CPER_SEV_RECOVERABLE,
	CPER_SEV_FATAL,
	CPER_SEV_CORRECTED,
	CPER_SEV_INFORMATIONAL,
};

/*
 * Validation bits definition for validation_bits in struct
 * cper_record_header. If set, corresponding fields in struct
 * cper_record_header contain valid information.
 */
#define CPER_VALID_PLATFORM_ID			0x0001
#define CPER_VALID_TIMESTAMP			0x0002
#define CPER_VALID_PARTITION_ID			0x0004

/*
 * Notification type used to generate error record, used in
 * notification_type in struct cper_record_header.  These UUIDs are defined
 * in the UEFI spec v2.7, sec N.2.1.
 */

/* Corrected Machine Check */
#define CPER_NOTIFY_CMC							\
	GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4,	\
		  0xEB, 0xD4, 0xF8, 0x90)
/* Corrected Platform Error */
#define CPER_NOTIFY_CPE							\
	GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81,	\
		  0xF2, 0x7E, 0xBE, 0xEE)
/* Machine Check Exception */
#define CPER_NOTIFY_MCE							\
	GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB,	\
		  0xE1, 0x49, 0x13, 0xBB)
/* PCI Express Error */
#define CPER_NOTIFY_PCIE						\
	GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D,	\
		  0xAF, 0x67, 0xC1, 0x04)
/* INIT Record (for IPF) */
#define CPER_NOTIFY_INIT						\
	GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B,	\
		  0xD3, 0x9B, 0xC9, 0x8E)
/* Non-Maskable Interrupt */
#define CPER_NOTIFY_NMI							\
	GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24,	\
		  0x85, 0xD6, 0xE9, 0x8A)
/* BOOT Error Record */
#define CPER_NOTIFY_BOOT						\
	GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62,	\
		  0xD4, 0x64, 0xB3, 0x8F)
/* DMA Remapping Error */
#define CPER_NOTIFY_DMAR						\
	GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E,	\
		  0x72, 0x2D, 0xEB, 0x41)

/*
 * Flags bits definitions for flags in struct cper_record_header
 * If set, the error has been recovered
 */
#define CPER_HW_ERROR_FLAGS_RECOVERED		0x1
/* If set, the error is for previous boot */
#define CPER_HW_ERROR_FLAGS_PREVERR		0x2
/* If set, the error is injected for testing */
#define CPER_HW_ERROR_FLAGS_SIMULATED		0x4

/*
 * CPER section header revision, used in revision field in struct
 * cper_section_descriptor
 */
#define CPER_SEC_REV				0x0100

/*
 * Validation bits definition for validation_bits in struct
 * cper_section_descriptor. If set, corresponding fields in struct
 * cper_section_descriptor contain valid information.
 */
#define CPER_SEC_VALID_FRU_ID			0x1
#define CPER_SEC_VALID_FRU_TEXT			0x2

/*
 * Flags bits definitions for flags in struct cper_section_descriptor
 *
 * If set, the section is associated with the error condition
 * directly, and should be focused on
 */
#define CPER_SEC_PRIMARY			0x0001
/*
 * If set, the error was not contained within the processor or memory
 * hierarchy and the error may have propagated to persistent storage
 * or network
 */
#define CPER_SEC_CONTAINMENT_WARNING		0x0002
/* If set, the component must be re-initialized or re-enabled prior to use */
#define CPER_SEC_RESET				0x0004
/* If set, Linux may choose to discontinue use of the resource */
#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED	0x0008
/*
 * If set, resource could not be queried for error information due to
 * conflicts with other system software or resources. Some fields of
 * the section will be invalid
 */
#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE	0x0010
/*
 * If set, action has been taken to ensure error containment (such as
 * poisoning data), but the error has not been fully corrected and the
 * data has not been consumed. Linux may choose to take further
 * corrective action before the data is consumed
 */
#define CPER_SEC_LATENT_ERROR			0x0020

/*
 * Section type definitions, used in section_type field in struct
 * cper_section_descriptor.  These UUIDs are defined in the UEFI spec
 * v2.7, sec N.2.2.
 */

/* Processor Generic */
#define CPER_SEC_PROC_GENERIC						\
	GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1,	\
		  0x93, 0xC4, 0xF3, 0xDB)
/* Processor Specific: X86/X86_64 */
#define CPER_SEC_PROC_IA						\
	GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA,	\
		  0x24, 0x2B, 0x6E, 0x1D)
/* Processor Specific: IA64 */
#define CPER_SEC_PROC_IPF						\
	GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00,	\
		  0x80, 0xC7, 0x3C, 0x88, 0x81)
/* Processor Specific: ARM */
#define CPER_SEC_PROC_ARM						\
	GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05,	\
		  0x1D, 0x5D, 0x46, 0xB0)
/* Platform Memory */
#define CPER_SEC_PLATFORM_MEM						\
	GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83,	\
		  0xED, 0x7C, 0x83, 0xB1)
#define CPER_SEC_PCIE							\
	GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D,	\
		  0xCB, 0x3C, 0x6F, 0x35)
/* Firmware Error Record Reference */
#define CPER_SEC_FW_ERR_REC_REF						\
	GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72,	\
		  0x9C, 0x8E, 0x69, 0xED)
/* PCI/PCI-X Bus */
#define CPER_SEC_PCI_X_BUS						\
	GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA,	\
		  0xD3, 0xF9, 0xC9, 0xDD)
/* PCI Component/Device */
#define CPER_SEC_PCI_DEV						\
	GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06,	\
		  0x8B, 0x00, 0x13, 0x26)
#define CPER_SEC_DMAR_GENERIC						\
	GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62,	\
		  0xDE, 0x3E, 0x2C, 0x64)
/* Intel VT for Directed I/O specific DMAr */
#define CPER_SEC_DMAR_VT						\
	GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE,	\
		  0xDD, 0x93, 0xE8, 0xCF)
/* IOMMU specific DMAr */
#define CPER_SEC_DMAR_IOMMU						\
	GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F,	\
		  0xDF, 0xAA, 0x84, 0xEC)

#define CPER_PROC_VALID_TYPE			0x0001
#define CPER_PROC_VALID_ISA			0x0002
#define CPER_PROC_VALID_ERROR_TYPE		0x0004
#define CPER_PROC_VALID_OPERATION		0x0008
#define CPER_PROC_VALID_FLAGS			0x0010
#define CPER_PROC_VALID_LEVEL			0x0020
#define CPER_PROC_VALID_VERSION			0x0040
#define CPER_PROC_VALID_BRAND_INFO		0x0080
#define CPER_PROC_VALID_ID			0x0100
#define CPER_PROC_VALID_TARGET_ADDRESS		0x0200
#define CPER_PROC_VALID_REQUESTOR_ID		0x0400
#define CPER_PROC_VALID_RESPONDER_ID		0x0800
#define CPER_PROC_VALID_IP			0x1000

#define CPER_MEM_VALID_ERROR_STATUS		0x0001
#define CPER_MEM_VALID_PA			0x0002
#define CPER_MEM_VALID_PA_MASK			0x0004
#define CPER_MEM_VALID_NODE			0x0008
#define CPER_MEM_VALID_CARD			0x0010
#define CPER_MEM_VALID_MODULE			0x0020
#define CPER_MEM_VALID_BANK			0x0040
#define CPER_MEM_VALID_DEVICE			0x0080
#define CPER_MEM_VALID_ROW			0x0100
#define CPER_MEM_VALID_COLUMN			0x0200
#define CPER_MEM_VALID_BIT_POSITION		0x0400
#define CPER_MEM_VALID_REQUESTOR_ID		0x0800
#define CPER_MEM_VALID_RESPONDER_ID		0x1000
#define CPER_MEM_VALID_TARGET_ID		0x2000
#define CPER_MEM_VALID_ERROR_TYPE		0x4000
#define CPER_MEM_VALID_RANK_NUMBER		0x8000
#define CPER_MEM_VALID_CARD_HANDLE		0x10000
#define CPER_MEM_VALID_MODULE_HANDLE		0x20000

#define CPER_PCIE_VALID_PORT_TYPE		0x0001
#define CPER_PCIE_VALID_VERSION			0x0002
#define CPER_PCIE_VALID_COMMAND_STATUS		0x0004
#define CPER_PCIE_VALID_DEVICE_ID		0x0008
#define CPER_PCIE_VALID_SERIAL_NUMBER		0x0010
#define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS	0x0020
#define CPER_PCIE_VALID_CAPABILITY		0x0040
#define CPER_PCIE_VALID_AER_INFO		0x0080

#define CPER_PCIE_SLOT_SHIFT			3

#define CPER_ARM_VALID_MPIDR			BIT(0)
#define CPER_ARM_VALID_AFFINITY_LEVEL		BIT(1)
#define CPER_ARM_VALID_RUNNING_STATE		BIT(2)
#define CPER_ARM_VALID_VENDOR_INFO		BIT(3)

#define CPER_ARM_INFO_VALID_MULTI_ERR		BIT(0)
#define CPER_ARM_INFO_VALID_FLAGS		BIT(1)
#define CPER_ARM_INFO_VALID_ERR_INFO		BIT(2)
#define CPER_ARM_INFO_VALID_VIRT_ADDR		BIT(3)
#define CPER_ARM_INFO_VALID_PHYSICAL_ADDR	BIT(4)

#define CPER_ARM_INFO_FLAGS_FIRST		BIT(0)
#define CPER_ARM_INFO_FLAGS_LAST		BIT(1)
#define CPER_ARM_INFO_FLAGS_PROPAGATED		BIT(2)
#define CPER_ARM_INFO_FLAGS_OVERFLOW		BIT(3)

#define CPER_ARM_CACHE_ERROR			0
#define CPER_ARM_TLB_ERROR			1
#define CPER_ARM_BUS_ERROR			2
#define CPER_ARM_VENDOR_ERROR			3
#define CPER_ARM_MAX_TYPE			CPER_ARM_VENDOR_ERROR

#define CPER_ARM_ERR_VALID_TRANSACTION_TYPE	BIT(0)
#define CPER_ARM_ERR_VALID_OPERATION_TYPE	BIT(1)
#define CPER_ARM_ERR_VALID_LEVEL		BIT(2)
#define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT	BIT(3)
#define CPER_ARM_ERR_VALID_CORRECTED		BIT(4)
#define CPER_ARM_ERR_VALID_PRECISE_PC		BIT(5)
#define CPER_ARM_ERR_VALID_RESTARTABLE_PC	BIT(6)
#define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE	BIT(7)
#define CPER_ARM_ERR_VALID_TIME_OUT		BIT(8)
#define CPER_ARM_ERR_VALID_ADDRESS_SPACE	BIT(9)
#define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES	BIT(10)
#define CPER_ARM_ERR_VALID_ACCESS_MODE		BIT(11)

#define CPER_ARM_ERR_TRANSACTION_SHIFT		16
#define CPER_ARM_ERR_TRANSACTION_MASK		GENMASK(1,0)
#define CPER_ARM_ERR_OPERATION_SHIFT		18
#define CPER_ARM_ERR_OPERATION_MASK		GENMASK(3,0)
#define CPER_ARM_ERR_LEVEL_SHIFT		22
#define CPER_ARM_ERR_LEVEL_MASK			GENMASK(2,0)
#define CPER_ARM_ERR_PC_CORRUPT_SHIFT		25
#define CPER_ARM_ERR_PC_CORRUPT_MASK		GENMASK(0,0)
#define CPER_ARM_ERR_CORRECTED_SHIFT		26
#define CPER_ARM_ERR_CORRECTED_MASK		GENMASK(0,0)
#define CPER_ARM_ERR_PRECISE_PC_SHIFT		27
#define CPER_ARM_ERR_PRECISE_PC_MASK		GENMASK(0,0)
#define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT	28
#define CPER_ARM_ERR_RESTARTABLE_PC_MASK	GENMASK(0,0)
#define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT	29
#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK	GENMASK(1,0)
#define CPER_ARM_ERR_TIME_OUT_SHIFT		31
#define CPER_ARM_ERR_TIME_OUT_MASK		GENMASK(0,0)
#define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT	32
#define CPER_ARM_ERR_ADDRESS_SPACE_MASK		GENMASK(1,0)
#define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT	34
#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK	GENMASK(8,0)
#define CPER_ARM_ERR_ACCESS_MODE_SHIFT		43
#define CPER_ARM_ERR_ACCESS_MODE_MASK		GENMASK(0,0)

/*
 * All tables and structs must be byte-packed to match CPER
 * specification, since the tables are provided by the system BIOS
 */
#pragma pack(1)

/* Record Header, UEFI v2.7 sec N.2.1 */
struct cper_record_header {
	char	signature[CPER_SIG_SIZE];	/* must be CPER_SIG_RECORD */
	u16	revision;			/* must be CPER_RECORD_REV */
	u32	signature_end;			/* must be CPER_SIG_END */
	u16	section_count;
	u32	error_severity;
	u32	validation_bits;
	u32	record_length;
	u64	timestamp;
	guid_t	platform_id;
	guid_t	partition_id;
	guid_t	creator_id;
	guid_t	notification_type;
	u64	record_id;
	u32	flags;
	u64	persistence_information;
	u8	reserved[12];			/* must be zero */
};

/* Section Descriptor, UEFI v2.7 sec N.2.2 */
struct cper_section_descriptor {
	u32	section_offset;		/* Offset in bytes of the
					 *  section body from the base
					 *  of the record header */
	u32	section_length;
	u16	revision;		/* must be CPER_RECORD_REV */
	u8	validation_bits;
	u8	reserved;		/* must be zero */
	u32	flags;
	guid_t	section_type;
	guid_t	fru_id;
	u32	section_severity;
	u8	fru_text[20];
};

/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
struct cper_sec_proc_generic {
	u64	validation_bits;
	u8	proc_type;
	u8	proc_isa;
	u8	proc_error_type;
	u8	operation;
	u8	flags;
	u8	level;
	u16	reserved;
	u64	cpu_version;
	char	cpu_brand[128];
	u64	proc_id;
	u64	target_addr;
	u64	requestor_id;
	u64	responder_id;
	u64	ip;
};

/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
struct cper_sec_proc_ia {
	u64	validation_bits;
	u64	lapic_id;
	u8	cpuid[48];
};

/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
struct cper_ia_err_info {
	guid_t	err_type;
	u64	validation_bits;
	u64	check_info;
	u64	target_id;
	u64	requestor_id;
	u64	responder_id;
	u64	ip;
};

/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
struct cper_ia_proc_ctx {
	u16	reg_ctx_type;
	u16	reg_arr_size;
	u32	msr_addr;
	u64	mm_reg_addr;
};

/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
struct cper_sec_proc_arm {
	u32	validation_bits;
	u16	err_info_num;		/* Number of Processor Error Info */
	u16	context_info_num;	/* Number of Processor Context Info Records*/
	u32	section_length;
	u8	affinity_level;
	u8	reserved[3];		/* must be zero */
	u64	mpidr;
	u64	midr;
	u32	running_state;		/* Bit 0 set - Processor running. PSCI = 0 */
	u32	psci_state;
};

/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
struct cper_arm_err_info {
	u8	version;
	u8	length;
	u16	validation_bits;
	u8	type;
	u16	multiple_error;
	u8	flags;
	u64	error_info;
	u64	virt_fault_addr;
	u64	physical_fault_addr;
};

/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
struct cper_arm_ctx_info {
	u16	version;
	u16	type;
	u32	size;
};

/* Old Memory Error Section, UEFI v2.1, v2.2 */
struct cper_sec_mem_err_old {
	u64	validation_bits;
	u64	error_status;
	u64	physical_addr;
	u64	physical_addr_mask;
	u16	node;
	u16	card;
	u16	module;
	u16	bank;
	u16	device;
	u16	row;
	u16	column;
	u16	bit_pos;
	u64	requestor_id;
	u64	responder_id;
	u64	target_id;
	u8	error_type;
};

/* Memory Error Section (UEFI >= v2.3), UEFI v2.7 sec N.2.5 */
struct cper_sec_mem_err {
	u64	validation_bits;
	u64	error_status;
	u64	physical_addr;
	u64	physical_addr_mask;
	u16	node;
	u16	card;
	u16	module;
	u16	bank;
	u16	device;
	u16	row;
	u16	column;
	u16	bit_pos;
	u64	requestor_id;
	u64	responder_id;
	u64	target_id;
	u8	error_type;
	u8	reserved;
	u16	rank;
	u16	mem_array_handle;	/* "card handle" in UEFI 2.4 */
	u16	mem_dev_handle;		/* "module handle" in UEFI 2.4 */
};

struct cper_mem_err_compact {
	u64	validation_bits;
	u16	node;
	u16	card;
	u16	module;
	u16	bank;
	u16	device;
	u16	row;
	u16	column;
	u16	bit_pos;
	u64	requestor_id;
	u64	responder_id;
	u64	target_id;
	u16	rank;
	u16	mem_array_handle;
	u16	mem_dev_handle;
};

/* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
struct cper_sec_pcie {
	u64		validation_bits;
	u32		port_type;
	struct {
		u8	minor;
		u8	major;
		u8	reserved[2];
	}		version;
	u16		command;
	u16		status;
	u32		reserved;
	struct {
		u16	vendor_id;
		u16	device_id;
		u8	class_code[3];
		u8	function;
		u8	device;
		u16	segment;
		u8	bus;
		u8	secondary_bus;
		u16	slot;
		u8	reserved;
	}		device_id;
	struct {
		u32	lower;
		u32	upper;
	}		serial_number;
	struct {
		u16	secondary_status;
		u16	control;
	}		bridge;
	u8	capability[60];
	u8	aer_info[96];
};

/* Firmware Error Record Reference, UEFI v2.7 sec N.2.10  */
struct cper_sec_fw_err_rec_ref {
	u8 record_type;
	u8 revision;
	u8 reserved[6];
	u64 record_identifier;
	guid_t record_identifier_guid;
};

/* Reset to default packing */
#pragma pack()

extern const char *const cper_proc_error_type_strs[4];

u64 cper_next_record_id(void);
const char *cper_severity_str(unsigned int);
const char *cper_mem_err_type_str(unsigned int);
void cper_print_bits(const char *prefix, unsigned int bits,
		     const char * const strs[], unsigned int strs_size);
void cper_mem_err_pack(const struct cper_sec_mem_err *,
		       struct cper_mem_err_compact *);
const char *cper_mem_err_unpack(struct trace_seq *,
				struct cper_mem_err_compact *);
void cper_print_proc_arm(const char *pfx,
			 const struct cper_sec_proc_arm *proc);
void cper_print_proc_ia(const char *pfx,
			const struct cper_sec_proc_ia *proc);

#endif
Commit	Line	Data
45051539	1	/* SPDX-License-Identifier: GPL-2.0-only */
06d65dea HY	2	/*
	3	* UEFI Common Platform Error Record
	4	*
	5	* Copyright (C) 2010, Intel Corp.
	6	* Author: Huang Ying <ying.huang@intel.com>
06d65dea HY	7	*/
	8
	9	#ifndef LINUX_CPER_H
	10	#define LINUX_CPER_H
	11
	12	#include <linux/uuid.h>
2dfb7d51	13	#include <linux/trace_seq.h>
06d65dea HY	14
	15	/* CPER record signature and the size */
	16	#define CPER_SIG_RECORD "CPER"
	17	#define CPER_SIG_SIZE 4
	18	/* Used in signature_end field in struct cper_record_header */
	19	#define CPER_SIG_END 0xffffffff
	20
	21	/*
	22	* CPER record header revision, used in revision field in struct
	23	* cper_record_header
	24	*/
	25	#define CPER_RECORD_REV 0x0100
	26
3760cd20 CG	27	/*
	28	* CPER record length contains the CPER fields which are relevant for further
	29	* handling of a memory error in userspace (we don't carry all the fields
	30	* defined in the UEFI spec because some of them don't make any sense.)
	31	* Currently, a length of 256 should be more than enough.
	32	*/
	33	#define CPER_REC_LEN 256
06d65dea	34	/*
12fa4f47	35	* Severity definition for error_severity in struct cper_record_header
06d65dea HY	36	* and section_severity in struct cper_section_descriptor
06d65dea HY	37	*/
c9aa308f HY	38	enum {
	39	CPER_SEV_RECOVERABLE,
	40	CPER_SEV_FATAL,
	41	CPER_SEV_CORRECTED,
	42	CPER_SEV_INFORMATIONAL,
	43	};
06d65dea HY	44
06d65dea HY	45	/*
12fa4f47	46	* Validation bits definition for validation_bits in struct
06d65dea HY	47	* cper_record_header. If set, corresponding fields in struct
06d65dea HY	48	* cper_record_header contain valid information.
06d65dea HY	49	*/
06d65dea HY	50	#define CPER_VALID_PLATFORM_ID 0x0001
06d65dea	51	#define CPER_VALID_TIMESTAMP 0x0002
06d65dea HY	52	#define CPER_VALID_PARTITION_ID 0x0004
	53
	54	/*
	55	* Notification type used to generate error record, used in
12fa4f47 BH	56	* notification_type in struct cper_record_header. These UUIDs are defined
12fa4f47 BH	57	* in the UEFI spec v2.7, sec N.2.1.
06d65dea	58	*/
12fa4f47 BH	59
12fa4f47 BH	60	/* Corrected Machine Check */
06d65dea	61	#define CPER_NOTIFY_CMC \
c0020756 AS	62	GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
c0020756 AS	63	0xEB, 0xD4, 0xF8, 0x90)
06d65dea HY	64	/* Corrected Platform Error */
06d65dea HY	65	#define CPER_NOTIFY_CPE \
c0020756 AS	66	GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \
c0020756 AS	67	0xF2, 0x7E, 0xBE, 0xEE)
06d65dea HY	68	/* Machine Check Exception */
06d65dea HY	69	#define CPER_NOTIFY_MCE \
c0020756 AS	70	GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \
c0020756 AS	71	0xE1, 0x49, 0x13, 0xBB)
06d65dea HY	72	/* PCI Express Error */
06d65dea HY	73	#define CPER_NOTIFY_PCIE \
c0020756 AS	74	GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \
c0020756 AS	75	0xAF, 0x67, 0xC1, 0x04)
06d65dea HY	76	/* INIT Record (for IPF) */
06d65dea HY	77	#define CPER_NOTIFY_INIT \
c0020756 AS	78	GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \
c0020756 AS	79	0xD3, 0x9B, 0xC9, 0x8E)
06d65dea HY	80	/* Non-Maskable Interrupt */
06d65dea HY	81	#define CPER_NOTIFY_NMI \
c0020756 AS	82	GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \
c0020756 AS	83	0x85, 0xD6, 0xE9, 0x8A)
06d65dea HY	84	/* BOOT Error Record */
06d65dea HY	85	#define CPER_NOTIFY_BOOT \
c0020756 AS	86	GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \
c0020756 AS	87	0xD4, 0x64, 0xB3, 0x8F)
06d65dea HY	88	/* DMA Remapping Error */
06d65dea HY	89	#define CPER_NOTIFY_DMAR \
c0020756 AS	90	GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \
c0020756 AS	91	0x72, 0x2D, 0xEB, 0x41)
06d65dea HY	92
	93	/*
	94	* Flags bits definitions for flags in struct cper_record_header
	95	* If set, the error has been recovered
	96	*/
	97	#define CPER_HW_ERROR_FLAGS_RECOVERED 0x1
	98	/* If set, the error is for previous boot */
	99	#define CPER_HW_ERROR_FLAGS_PREVERR 0x2
	100	/* If set, the error is injected for testing */
	101	#define CPER_HW_ERROR_FLAGS_SIMULATED 0x4
	102
	103	/*
	104	* CPER section header revision, used in revision field in struct
	105	* cper_section_descriptor
	106	*/
	107	#define CPER_SEC_REV 0x0100
	108
	109	/*
12fa4f47	110	* Validation bits definition for validation_bits in struct
06d65dea HY	111	* cper_section_descriptor. If set, corresponding fields in struct
06d65dea HY	112	* cper_section_descriptor contain valid information.
06d65dea HY	113	*/
06d65dea HY	114	#define CPER_SEC_VALID_FRU_ID 0x1
06d65dea HY	115	#define CPER_SEC_VALID_FRU_TEXT 0x2
	116
	117	/*
	118	* Flags bits definitions for flags in struct cper_section_descriptor
	119	*
	120	* If set, the section is associated with the error condition
	121	* directly, and should be focused on
	122	*/
	123	#define CPER_SEC_PRIMARY 0x0001
	124	/*
	125	* If set, the error was not contained within the processor or memory
	126	* hierarchy and the error may have propagated to persistent storage
	127	* or network
	128	*/
	129	#define CPER_SEC_CONTAINMENT_WARNING 0x0002
	130	/* If set, the component must be re-initialized or re-enabled prior to use */
	131	#define CPER_SEC_RESET 0x0004
	132	/* If set, Linux may choose to discontinue use of the resource */
	133	#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED 0x0008
	134	/*
	135	* If set, resource could not be queried for error information due to
	136	* conflicts with other system software or resources. Some fields of
	137	* the section will be invalid
	138	*/
	139	#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE 0x0010
	140	/*
	141	* If set, action has been taken to ensure error containment (such as
	142	* poisoning data), but the error has not been fully corrected and the
	143	* data has not been consumed. Linux may choose to take further
	144	* corrective action before the data is consumed
	145	*/
	146	#define CPER_SEC_LATENT_ERROR 0x0020
	147
	148	/*
	149	* Section type definitions, used in section_type field in struct
12fa4f47 BH	150	* cper_section_descriptor. These UUIDs are defined in the UEFI spec
12fa4f47 BH	151	* v2.7, sec N.2.2.
06d65dea	152	*/
12fa4f47 BH	153
12fa4f47 BH	154	/* Processor Generic */
06d65dea	155	#define CPER_SEC_PROC_GENERIC \
c0020756 AS	156	GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \
c0020756 AS	157	0x93, 0xC4, 0xF3, 0xDB)
06d65dea HY	158	/* Processor Specific: X86/X86_64 */
06d65dea HY	159	#define CPER_SEC_PROC_IA \
c0020756 AS	160	GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \
c0020756 AS	161	0x24, 0x2B, 0x6E, 0x1D)
06d65dea HY	162	/* Processor Specific: IA64 */
06d65dea HY	163	#define CPER_SEC_PROC_IPF \
c0020756 AS	164	GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00, \
c0020756 AS	165	0x80, 0xC7, 0x3C, 0x88, 0x81)
2f74f09b TB	166	/* Processor Specific: ARM */
2f74f09b TB	167	#define CPER_SEC_PROC_ARM \
c0020756 AS	168	GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05, \
c0020756 AS	169	0x1D, 0x5D, 0x46, 0xB0)
06d65dea HY	170	/* Platform Memory */
06d65dea HY	171	#define CPER_SEC_PLATFORM_MEM \
c0020756 AS	172	GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
c0020756 AS	173	0xED, 0x7C, 0x83, 0xB1)
06d65dea	174	#define CPER_SEC_PCIE \
c0020756 AS	175	GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \
c0020756 AS	176	0xCB, 0x3C, 0x6F, 0x35)
06d65dea HY	177	/* Firmware Error Record Reference */
06d65dea HY	178	#define CPER_SEC_FW_ERR_REC_REF \
c0020756 AS	179	GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72, \
c0020756 AS	180	0x9C, 0x8E, 0x69, 0xED)
06d65dea HY	181	/* PCI/PCI-X Bus */
06d65dea HY	182	#define CPER_SEC_PCI_X_BUS \
c0020756 AS	183	GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA, \
c0020756 AS	184	0xD3, 0xF9, 0xC9, 0xDD)
06d65dea HY	185	/* PCI Component/Device */
06d65dea HY	186	#define CPER_SEC_PCI_DEV \
c0020756 AS	187	GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06, \
c0020756 AS	188	0x8B, 0x00, 0x13, 0x26)
06d65dea	189	#define CPER_SEC_DMAR_GENERIC \
c0020756 AS	190	GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62, \
c0020756 AS	191	0xDE, 0x3E, 0x2C, 0x64)
06d65dea HY	192	/* Intel VT for Directed I/O specific DMAr */
06d65dea HY	193	#define CPER_SEC_DMAR_VT \
c0020756 AS	194	GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE, \
c0020756 AS	195	0xDD, 0x93, 0xE8, 0xCF)
06d65dea HY	196	/* IOMMU specific DMAr */
06d65dea HY	197	#define CPER_SEC_DMAR_IOMMU \
c0020756 AS	198	GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F, \
c0020756 AS	199	0xDF, 0xAA, 0x84, 0xEC)
06d65dea	200
c9aa308f HY	201	#define CPER_PROC_VALID_TYPE 0x0001
	202	#define CPER_PROC_VALID_ISA 0x0002
	203	#define CPER_PROC_VALID_ERROR_TYPE 0x0004
	204	#define CPER_PROC_VALID_OPERATION 0x0008
	205	#define CPER_PROC_VALID_FLAGS 0x0010
	206	#define CPER_PROC_VALID_LEVEL 0x0020
	207	#define CPER_PROC_VALID_VERSION 0x0040
	208	#define CPER_PROC_VALID_BRAND_INFO 0x0080
	209	#define CPER_PROC_VALID_ID 0x0100
	210	#define CPER_PROC_VALID_TARGET_ADDRESS 0x0200
	211	#define CPER_PROC_VALID_REQUESTOR_ID 0x0400
	212	#define CPER_PROC_VALID_RESPONDER_ID 0x0800
	213	#define CPER_PROC_VALID_IP 0x1000
	214
	215	#define CPER_MEM_VALID_ERROR_STATUS 0x0001
147de147 CG	216	#define CPER_MEM_VALID_PA 0x0002
147de147 CG	217	#define CPER_MEM_VALID_PA_MASK 0x0004
c9aa308f HY	218	#define CPER_MEM_VALID_NODE 0x0008
	219	#define CPER_MEM_VALID_CARD 0x0010
	220	#define CPER_MEM_VALID_MODULE 0x0020
	221	#define CPER_MEM_VALID_BANK 0x0040
	222	#define CPER_MEM_VALID_DEVICE 0x0080
	223	#define CPER_MEM_VALID_ROW 0x0100
	224	#define CPER_MEM_VALID_COLUMN 0x0200
	225	#define CPER_MEM_VALID_BIT_POSITION 0x0400
	226	#define CPER_MEM_VALID_REQUESTOR_ID 0x0800
	227	#define CPER_MEM_VALID_RESPONDER_ID 0x1000
	228	#define CPER_MEM_VALID_TARGET_ID 0x2000
	229	#define CPER_MEM_VALID_ERROR_TYPE 0x4000
147de147 CG	230	#define CPER_MEM_VALID_RANK_NUMBER 0x8000
	231	#define CPER_MEM_VALID_CARD_HANDLE 0x10000
	232	#define CPER_MEM_VALID_MODULE_HANDLE 0x20000
c9aa308f HY	233
	234	#define CPER_PCIE_VALID_PORT_TYPE 0x0001
	235	#define CPER_PCIE_VALID_VERSION 0x0002
	236	#define CPER_PCIE_VALID_COMMAND_STATUS 0x0004
	237	#define CPER_PCIE_VALID_DEVICE_ID 0x0008
	238	#define CPER_PCIE_VALID_SERIAL_NUMBER 0x0010
	239	#define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS 0x0020
	240	#define CPER_PCIE_VALID_CAPABILITY 0x0040
	241	#define CPER_PCIE_VALID_AER_INFO 0x0080
	242
	243	#define CPER_PCIE_SLOT_SHIFT 3
	244
2f74f09b TB	245	#define CPER_ARM_VALID_MPIDR BIT(0)
	246	#define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1)
	247	#define CPER_ARM_VALID_RUNNING_STATE BIT(2)
	248	#define CPER_ARM_VALID_VENDOR_INFO BIT(3)
	249
	250	#define CPER_ARM_INFO_VALID_MULTI_ERR BIT(0)
	251	#define CPER_ARM_INFO_VALID_FLAGS BIT(1)
	252	#define CPER_ARM_INFO_VALID_ERR_INFO BIT(2)
	253	#define CPER_ARM_INFO_VALID_VIRT_ADDR BIT(3)
	254	#define CPER_ARM_INFO_VALID_PHYSICAL_ADDR BIT(4)
	255
	256	#define CPER_ARM_INFO_FLAGS_FIRST BIT(0)
	257	#define CPER_ARM_INFO_FLAGS_LAST BIT(1)
	258	#define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2)
	259	#define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3)
	260
301f55b1 TB	261	#define CPER_ARM_CACHE_ERROR 0
	262	#define CPER_ARM_TLB_ERROR 1
	263	#define CPER_ARM_BUS_ERROR 2
	264	#define CPER_ARM_VENDOR_ERROR 3
	265	#define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR
	266
	267	#define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0)
	268	#define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1)
	269	#define CPER_ARM_ERR_VALID_LEVEL BIT(2)
	270	#define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3)
	271	#define CPER_ARM_ERR_VALID_CORRECTED BIT(4)
	272	#define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5)
	273	#define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6)
	274	#define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7)
	275	#define CPER_ARM_ERR_VALID_TIME_OUT BIT(8)
	276	#define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9)
	277	#define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10)
	278	#define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11)
	279
	280	#define CPER_ARM_ERR_TRANSACTION_SHIFT 16
	281	#define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0)
	282	#define CPER_ARM_ERR_OPERATION_SHIFT 18
	283	#define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0)
	284	#define CPER_ARM_ERR_LEVEL_SHIFT 22
	285	#define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0)
	286	#define CPER_ARM_ERR_PC_CORRUPT_SHIFT 25
	287	#define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0)
	288	#define CPER_ARM_ERR_CORRECTED_SHIFT 26
	289	#define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0)
	290	#define CPER_ARM_ERR_PRECISE_PC_SHIFT 27
	291	#define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0)
	292	#define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT 28
	293	#define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0)
	294	#define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT 29
	295	#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0)
	296	#define CPER_ARM_ERR_TIME_OUT_SHIFT 31
	297	#define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0)
	298	#define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT 32
	299	#define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0)
	300	#define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT 34
	301	#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0)
	302	#define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43
	303	#define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0)
	304
06d65dea HY	305	/*
	306	* All tables and structs must be byte-packed to match CPER
	307	* specification, since the tables are provided by the system BIOS
	308	*/
	309	#pragma pack(1)
	310
12fa4f47	311	/* Record Header, UEFI v2.7 sec N.2.1 */
06d65dea HY	312	struct cper_record_header {
06d65dea HY	313	char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */
113fb03e BH	314	u16 revision; /* must be CPER_RECORD_REV */
	315	u32 signature_end; /* must be CPER_SIG_END */
	316	u16 section_count;
	317	u32 error_severity;
	318	u32 validation_bits;
	319	u32 record_length;
	320	u64 timestamp;
c0020756 AS	321	guid_t platform_id;
	322	guid_t partition_id;
	323	guid_t creator_id;
	324	guid_t notification_type;
113fb03e BH	325	u64 record_id;
	326	u32 flags;
	327	u64 persistence_information;
	328	u8 reserved[12]; /* must be zero */
06d65dea HY	329	};
06d65dea HY	330
12fa4f47	331	/* Section Descriptor, UEFI v2.7 sec N.2.2 */
06d65dea	332	struct cper_section_descriptor {
113fb03e	333	u32 section_offset; /* Offset in bytes of the
06d65dea HY	334	* section body from the base
06d65dea HY	335	* of the record header */
113fb03e BH	336	u32 section_length;
	337	u16 revision; /* must be CPER_RECORD_REV */
	338	u8 validation_bits;
	339	u8 reserved; /* must be zero */
	340	u32 flags;
c0020756 AS	341	guid_t section_type;
c0020756 AS	342	guid_t fru_id;
113fb03e BH	343	u32 section_severity;
113fb03e BH	344	u8 fru_text[20];
06d65dea HY	345	};
06d65dea HY	346
12fa4f47	347	/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
06d65dea	348	struct cper_sec_proc_generic {
113fb03e BH	349	u64 validation_bits;
	350	u8 proc_type;
	351	u8 proc_isa;
	352	u8 proc_error_type;
	353	u8 operation;
	354	u8 flags;
	355	u8 level;
	356	u16 reserved;
	357	u64 cpu_version;
06d65dea	358	char cpu_brand[128];
113fb03e BH	359	u64 proc_id;
	360	u64 target_addr;
	361	u64 requestor_id;
	362	u64 responder_id;
	363	u64 ip;
06d65dea HY	364	};
06d65dea HY	365
12fa4f47	366	/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
06d65dea	367	struct cper_sec_proc_ia {
113fb03e BH	368	u64 validation_bits;
	369	u64 lapic_id;
	370	u8 cpuid[48];
06d65dea HY	371	};
06d65dea HY	372
12fa4f47	373	/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
06d65dea	374	struct cper_ia_err_info {
c0020756	375	guid_t err_type;
113fb03e BH	376	u64 validation_bits;
	377	u64 check_info;
	378	u64 target_id;
	379	u64 requestor_id;
	380	u64 responder_id;
	381	u64 ip;
06d65dea HY	382	};
06d65dea HY	383
12fa4f47	384	/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
06d65dea	385	struct cper_ia_proc_ctx {
113fb03e BH	386	u16 reg_ctx_type;
	387	u16 reg_arr_size;
	388	u32 msr_addr;
	389	u64 mm_reg_addr;
06d65dea HY	390	};
06d65dea HY	391
12fa4f47	392	/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
2f74f09b	393	struct cper_sec_proc_arm {
113fb03e BH	394	u32 validation_bits;
	395	u16 err_info_num; /* Number of Processor Error Info */
	396	u16 context_info_num; /* Number of Processor Context Info Records*/
	397	u32 section_length;
	398	u8 affinity_level;
	399	u8 reserved[3]; /* must be zero */
	400	u64 mpidr;
	401	u64 midr;
	402	u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */
	403	u32 psci_state;
2f74f09b TB	404	};
2f74f09b TB	405
12fa4f47	406	/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
2f74f09b	407	struct cper_arm_err_info {
113fb03e BH	408	u8 version;
	409	u8 length;
	410	u16 validation_bits;
	411	u8 type;
	412	u16 multiple_error;
	413	u8 flags;
	414	u64 error_info;
	415	u64 virt_fault_addr;
	416	u64 physical_fault_addr;
2f74f09b TB	417	};
2f74f09b TB	418
12fa4f47	419	/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
2f74f09b	420	struct cper_arm_ctx_info {
113fb03e BH	421	u16 version;
	422	u16 type;
	423	u32 size;
2f74f09b TB	424	};
2f74f09b TB	425
12fa4f47	426	/* Old Memory Error Section, UEFI v2.1, v2.2 */
4c62360d	427	struct cper_sec_mem_err_old {
113fb03e BH	428	u64 validation_bits;
	429	u64 error_status;
	430	u64 physical_addr;
	431	u64 physical_addr_mask;
	432	u16 node;
	433	u16 card;
	434	u16 module;
	435	u16 bank;
	436	u16 device;
	437	u16 row;
	438	u16 column;
	439	u16 bit_pos;
	440	u64 requestor_id;
	441	u64 responder_id;
	442	u64 target_id;
	443	u8 error_type;
4c62360d TL	444	};
4c62360d TL	445
12fa4f47	446	/* Memory Error Section (UEFI >= v2.3), UEFI v2.7 sec N.2.5 */
06d65dea	447	struct cper_sec_mem_err {
113fb03e BH	448	u64 validation_bits;
	449	u64 error_status;
	450	u64 physical_addr;
	451	u64 physical_addr_mask;
	452	u16 node;
	453	u16 card;
	454	u16 module;
	455	u16 bank;
	456	u16 device;
	457	u16 row;
	458	u16 column;
	459	u16 bit_pos;
	460	u64 requestor_id;
	461	u64 responder_id;
	462	u64 target_id;
	463	u8 error_type;
	464	u8 reserved;
	465	u16 rank;
	466	u16 mem_array_handle; /* "card handle" in UEFI 2.4 */
	467	u16 mem_dev_handle; /* "module handle" in UEFI 2.4 */
06d65dea HY	468	};
06d65dea HY	469
2dfb7d51	470	struct cper_mem_err_compact {
113fb03e BH	471	u64 validation_bits;
	472	u16 node;
	473	u16 card;
	474	u16 module;
	475	u16 bank;
	476	u16 device;
	477	u16 row;
	478	u16 column;
	479	u16 bit_pos;
	480	u64 requestor_id;
	481	u64 responder_id;
	482	u64 target_id;
	483	u16 rank;
	484	u16 mem_array_handle;
	485	u16 mem_dev_handle;
2dfb7d51 CG	486	};
2dfb7d51 CG	487
12fa4f47	488	/* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
c9aa308f	489	struct cper_sec_pcie {
113fb03e BH	490	u64 validation_bits;
113fb03e BH	491	u32 port_type;
c9aa308f	492	struct {
113fb03e BH	493	u8 minor;
	494	u8 major;
	495	u8 reserved[2];
c9aa308f	496	} version;
113fb03e BH	497	u16 command;
	498	u16 status;
	499	u32 reserved;
c9aa308f	500	struct {
113fb03e BH	501	u16 vendor_id;
	502	u16 device_id;
	503	u8 class_code[3];
	504	u8 function;
	505	u8 device;
	506	u16 segment;
	507	u8 bus;
	508	u8 secondary_bus;
	509	u16 slot;
	510	u8 reserved;
c9aa308f HY	511	} device_id;
c9aa308f HY	512	struct {
113fb03e BH	513	u32 lower;
113fb03e BH	514	u32 upper;
c9aa308f HY	515	} serial_number;
c9aa308f HY	516	struct {
113fb03e BH	517	u16 secondary_status;
113fb03e BH	518	u16 control;
c9aa308f	519	} bridge;
113fb03e BH	520	u8 capability[60];
113fb03e BH	521	u8 aer_info[96];
c9aa308f HY	522	};
c9aa308f HY	523
3d8c11ef PA	524	/* Firmware Error Record Reference, UEFI v2.7 sec N.2.10 */
	525	struct cper_sec_fw_err_rec_ref {
	526	u8 record_type;
	527	u8 revision;
	528	u8 reserved[6];
	529	u64 record_identifier;
	530	guid_t record_identifier_guid;
	531	};
	532
06d65dea HY	533	/* Reset to default packing */
	534	#pragma pack()
	535
12fa4f47	536	extern const char *const cper_proc_error_type_strs[4];
c6d8c8ef	537
06d65dea	538	u64 cper_next_record_id(void);
3760cd20 CG	539	const char *cper_severity_str(unsigned int);
3760cd20 CG	540	const char *cper_mem_err_type_str(unsigned int);
c413d768	541	void cper_print_bits(const char *prefix, unsigned int bits,
88f074f4	542	const char * const strs[], unsigned int strs_size);
2dfb7d51 CG	543	void cper_mem_err_pack(const struct cper_sec_mem_err *,
	544	struct cper_mem_err_compact *);
	545	const char cper_mem_err_unpack(struct trace_seq ,
	546	struct cper_mem_err_compact *);
c6d8c8ef TB	547	void cper_print_proc_arm(const char *pfx,
c6d8c8ef TB	548	const struct cper_sec_proc_arm *proc);
f9e1bdb9 YG	549	void cper_print_proc_ia(const char *pfx,
f9e1bdb9 YG	550	const struct cper_sec_proc_ia *proc);
06d65dea HY	551
06d65dea HY	552	#endif