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23892e49 DL |
1 | /* |
2 | * QUICC Engine (QE) Internal Memory Map. | |
3 | * The Internal Memory Map for devices with QE on them. This | |
4 | * is the superset of all QE devices (8360, etc.). | |
5 | * | |
fdb4dad3 | 6 | * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc. |
23892e49 DL |
7 | * Author: Shlomi Gridih <gridish@freescale.com> |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
23892e49 DL |
10 | */ |
11 | ||
12 | #ifndef __IMMAP_QE_H__ | |
13 | #define __IMMAP_QE_H__ | |
14 | ||
fdb4dad3 KG |
15 | #ifdef CONFIG_MPC83xx |
16 | #if defined(CONFIG_MPC8360) | |
17 | #define QE_MURAM_SIZE 0xc000UL | |
18 | #define MAX_QE_RISC 2 | |
19 | #define QE_NUM_OF_SNUM 28 | |
a88731a6 | 20 | #elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309) |
fdb4dad3 KG |
21 | #define QE_MURAM_SIZE 0x4000UL |
22 | #define MAX_QE_RISC 1 | |
23 | #define QE_NUM_OF_SNUM 28 | |
24 | #endif | |
25 | #endif | |
26 | ||
73fb5838 | 27 | #ifdef CONFIG_ARCH_LS1021A |
ae42eb03 ZQ |
28 | #define QE_MURAM_SIZE 0x6000UL |
29 | #define MAX_QE_RISC 1 | |
30 | #define QE_NUM_OF_SNUM 28 | |
31 | #endif | |
32 | ||
33 | #ifdef CONFIG_PPC | |
34 | #define QE_IMMR_OFFSET 0x00140000 | |
35 | #else | |
36 | #define QE_IMMR_OFFSET 0x01400000 | |
37 | #endif | |
38 | ||
fdb4dad3 | 39 | /* QE I-RAM */ |
23892e49 DL |
40 | typedef struct qe_iram { |
41 | u32 iadd; /* I-RAM Address Register */ | |
42 | u32 idata; /* I-RAM Data Register */ | |
22b6dbc1 HW |
43 | u8 res0[0x4]; |
44 | u32 iready; | |
45 | u8 res1[0x70]; | |
23892e49 DL |
46 | } __attribute__ ((packed)) qe_iram_t; |
47 | ||
fdb4dad3 | 48 | /* QE Interrupt Controller */ |
23892e49 DL |
49 | typedef struct qe_ic { |
50 | u32 qicr; | |
51 | u32 qivec; | |
52 | u32 qripnr; | |
53 | u32 qipnr; | |
54 | u32 qipxcc; | |
55 | u32 qipycc; | |
56 | u32 qipwcc; | |
57 | u32 qipzcc; | |
58 | u32 qimr; | |
59 | u32 qrimr; | |
60 | u32 qicnr; | |
61 | u8 res0[0x4]; | |
62 | u32 qiprta; | |
63 | u32 qiprtb; | |
64 | u8 res1[0x4]; | |
65 | u32 qricr; | |
66 | u8 res2[0x20]; | |
67 | u32 qhivec; | |
68 | u8 res3[0x1C]; | |
69 | } __attribute__ ((packed)) qe_ic_t; | |
70 | ||
fdb4dad3 | 71 | /* Communications Processor */ |
23892e49 DL |
72 | typedef struct cp_qe { |
73 | u32 cecr; /* QE command register */ | |
74 | u32 ceccr; /* QE controller configuration register */ | |
75 | u32 cecdr; /* QE command data register */ | |
76 | u8 res0[0xA]; | |
77 | u16 ceter; /* QE timer event register */ | |
78 | u8 res1[0x2]; | |
79 | u16 cetmr; /* QE timers mask register */ | |
80 | u32 cetscr; /* QE time-stamp timer control register */ | |
81 | u32 cetsr1; /* QE time-stamp register 1 */ | |
82 | u32 cetsr2; /* QE time-stamp register 2 */ | |
83 | u8 res2[0x8]; | |
84 | u32 cevter; /* QE virtual tasks event register */ | |
85 | u32 cevtmr; /* QE virtual tasks mask register */ | |
86 | u16 cercr; /* QE RAM control register */ | |
87 | u8 res3[0x2]; | |
88 | u8 res4[0x24]; | |
89 | u16 ceexe1; /* QE external request 1 event register */ | |
90 | u8 res5[0x2]; | |
91 | u16 ceexm1; /* QE external request 1 mask register */ | |
92 | u8 res6[0x2]; | |
93 | u16 ceexe2; /* QE external request 2 event register */ | |
94 | u8 res7[0x2]; | |
95 | u16 ceexm2; /* QE external request 2 mask register */ | |
96 | u8 res8[0x2]; | |
97 | u16 ceexe3; /* QE external request 3 event register */ | |
98 | u8 res9[0x2]; | |
99 | u16 ceexm3; /* QE external request 3 mask register */ | |
100 | u8 res10[0x2]; | |
101 | u16 ceexe4; /* QE external request 4 event register */ | |
102 | u8 res11[0x2]; | |
103 | u16 ceexm4; /* QE external request 4 mask register */ | |
104 | u8 res12[0x2]; | |
105 | u8 res13[0x280]; | |
106 | } __attribute__ ((packed)) cp_qe_t; | |
107 | ||
fdb4dad3 | 108 | /* QE Multiplexer */ |
23892e49 DL |
109 | typedef struct qe_mux { |
110 | u32 cmxgcr; /* CMX general clock route register */ | |
111 | u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ | |
112 | u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ | |
113 | u32 cmxsi1syr; /* CMX SI1 SYNC route register */ | |
114 | u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ | |
115 | u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ | |
116 | u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ | |
117 | u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ | |
118 | u32 cmxupcr; /* CMX UPC clock route register */ | |
119 | u8 res0[0x1C]; | |
120 | } __attribute__ ((packed)) qe_mux_t; | |
121 | ||
fdb4dad3 | 122 | /* QE Timers */ |
23892e49 DL |
123 | typedef struct qe_timers { |
124 | u8 gtcfr1; /* Timer 1 2 global configuration register */ | |
125 | u8 res0[0x3]; | |
126 | u8 gtcfr2; /* Timer 3 4 global configuration register */ | |
127 | u8 res1[0xB]; | |
128 | u16 gtmdr1; /* Timer 1 mode register */ | |
129 | u16 gtmdr2; /* Timer 2 mode register */ | |
130 | u16 gtrfr1; /* Timer 1 reference register */ | |
131 | u16 gtrfr2; /* Timer 2 reference register */ | |
132 | u16 gtcpr1; /* Timer 1 capture register */ | |
133 | u16 gtcpr2; /* Timer 2 capture register */ | |
134 | u16 gtcnr1; /* Timer 1 counter */ | |
135 | u16 gtcnr2; /* Timer 2 counter */ | |
136 | u16 gtmdr3; /* Timer 3 mode register */ | |
137 | u16 gtmdr4; /* Timer 4 mode register */ | |
138 | u16 gtrfr3; /* Timer 3 reference register */ | |
139 | u16 gtrfr4; /* Timer 4 reference register */ | |
140 | u16 gtcpr3; /* Timer 3 capture register */ | |
141 | u16 gtcpr4; /* Timer 4 capture register */ | |
142 | u16 gtcnr3; /* Timer 3 counter */ | |
143 | u16 gtcnr4; /* Timer 4 counter */ | |
144 | u16 gtevr1; /* Timer 1 event register */ | |
145 | u16 gtevr2; /* Timer 2 event register */ | |
146 | u16 gtevr3; /* Timer 3 event register */ | |
147 | u16 gtevr4; /* Timer 4 event register */ | |
148 | u16 gtps; /* Timer 1 prescale register */ | |
149 | u8 res2[0x46]; | |
150 | } __attribute__ ((packed)) qe_timers_t; | |
151 | ||
fdb4dad3 | 152 | /* BRG */ |
23892e49 DL |
153 | typedef struct qe_brg { |
154 | u32 brgc1; /* BRG1 configuration register */ | |
155 | u32 brgc2; /* BRG2 configuration register */ | |
156 | u32 brgc3; /* BRG3 configuration register */ | |
157 | u32 brgc4; /* BRG4 configuration register */ | |
158 | u32 brgc5; /* BRG5 configuration register */ | |
159 | u32 brgc6; /* BRG6 configuration register */ | |
160 | u32 brgc7; /* BRG7 configuration register */ | |
161 | u32 brgc8; /* BRG8 configuration register */ | |
162 | u32 brgc9; /* BRG9 configuration register */ | |
163 | u32 brgc10; /* BRG10 configuration register */ | |
164 | u32 brgc11; /* BRG11 configuration register */ | |
165 | u32 brgc12; /* BRG12 configuration register */ | |
166 | u32 brgc13; /* BRG13 configuration register */ | |
167 | u32 brgc14; /* BRG14 configuration register */ | |
168 | u32 brgc15; /* BRG15 configuration register */ | |
169 | u32 brgc16; /* BRG16 configuration register */ | |
170 | u8 res0[0x40]; | |
171 | } __attribute__ ((packed)) qe_brg_t; | |
172 | ||
fdb4dad3 | 173 | /* SPI */ |
23892e49 DL |
174 | typedef struct spi { |
175 | u8 res0[0x20]; | |
176 | u32 spmode; /* SPI mode register */ | |
177 | u8 res1[0x2]; | |
178 | u8 spie; /* SPI event register */ | |
179 | u8 res2[0x1]; | |
180 | u8 res3[0x2]; | |
181 | u8 spim; /* SPI mask register */ | |
182 | u8 res4[0x1]; | |
183 | u8 res5[0x1]; | |
184 | u8 spcom; /* SPI command register */ | |
185 | u8 res6[0x2]; | |
186 | u32 spitd; /* SPI transmit data register (cpu mode) */ | |
187 | u32 spird; /* SPI receive data register (cpu mode) */ | |
188 | u8 res7[0x8]; | |
189 | } __attribute__ ((packed)) spi_t; | |
190 | ||
fdb4dad3 | 191 | /* SI */ |
23892e49 DL |
192 | typedef struct si1 { |
193 | u16 siamr1; /* SI1 TDMA mode register */ | |
194 | u16 sibmr1; /* SI1 TDMB mode register */ | |
195 | u16 sicmr1; /* SI1 TDMC mode register */ | |
196 | u16 sidmr1; /* SI1 TDMD mode register */ | |
197 | u8 siglmr1_h; /* SI1 global mode register high */ | |
198 | u8 res0[0x1]; | |
199 | u8 sicmdr1_h; /* SI1 command register high */ | |
200 | u8 res2[0x1]; | |
201 | u8 sistr1_h; /* SI1 status register high */ | |
202 | u8 res3[0x1]; | |
203 | u16 sirsr1_h; /* SI1 RAM shadow address register high */ | |
204 | u8 sitarc1; /* SI1 RAM counter Tx TDMA */ | |
205 | u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ | |
206 | u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ | |
207 | u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ | |
208 | u8 sirarc1; /* SI1 RAM counter Rx TDMA */ | |
209 | u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ | |
210 | u8 sircrc1; /* SI1 RAM counter Rx TDMC */ | |
211 | u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ | |
212 | u8 res4[0x8]; | |
213 | u16 siemr1; /* SI1 TDME mode register 16 bits */ | |
214 | u16 sifmr1; /* SI1 TDMF mode register 16 bits */ | |
215 | u16 sigmr1; /* SI1 TDMG mode register 16 bits */ | |
216 | u16 sihmr1; /* SI1 TDMH mode register 16 bits */ | |
217 | u8 siglmg1_l; /* SI1 global mode register low 8 bits */ | |
218 | u8 res5[0x1]; | |
219 | u8 sicmdr1_l; /* SI1 command register low 8 bits */ | |
220 | u8 res6[0x1]; | |
221 | u8 sistr1_l; /* SI1 status register low 8 bits */ | |
222 | u8 res7[0x1]; | |
223 | u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ | |
224 | u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ | |
225 | u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ | |
226 | u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ | |
227 | u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ | |
228 | u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ | |
229 | u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ | |
230 | u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ | |
231 | u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ | |
232 | u8 res8[0x8]; | |
233 | u32 siml1; /* SI1 multiframe limit register */ | |
234 | u8 siedm1; /* SI1 extended diagnostic mode register */ | |
235 | u8 res9[0xBB]; | |
236 | } __attribute__ ((packed)) si1_t; | |
237 | ||
fdb4dad3 | 238 | /* SI Routing Tables */ |
23892e49 DL |
239 | typedef struct sir { |
240 | u8 tx[0x400]; | |
241 | u8 rx[0x400]; | |
242 | u8 res0[0x800]; | |
243 | } __attribute__ ((packed)) sir_t; | |
244 | ||
fdb4dad3 | 245 | /* USB Controller. */ |
23892e49 DL |
246 | typedef struct usb_ctlr { |
247 | u8 usb_usmod; | |
248 | u8 usb_usadr; | |
249 | u8 usb_uscom; | |
250 | u8 res1[1]; | |
251 | u16 usb_usep1; | |
252 | u16 usb_usep2; | |
253 | u16 usb_usep3; | |
254 | u16 usb_usep4; | |
255 | u8 res2[4]; | |
256 | u16 usb_usber; | |
257 | u8 res3[2]; | |
258 | u16 usb_usbmr; | |
259 | u8 res4[1]; | |
260 | u8 usb_usbs; | |
261 | u16 usb_ussft; | |
262 | u8 res5[2]; | |
263 | u16 usb_usfrn; | |
264 | u8 res6[0x22]; | |
265 | } __attribute__ ((packed)) usb_t; | |
266 | ||
fdb4dad3 | 267 | /* MCC */ |
23892e49 DL |
268 | typedef struct mcc { |
269 | u32 mcce; /* MCC event register */ | |
270 | u32 mccm; /* MCC mask register */ | |
271 | u32 mccf; /* MCC configuration register */ | |
272 | u32 merl; /* MCC emergency request level register */ | |
273 | u8 res0[0xF0]; | |
274 | } __attribute__ ((packed)) mcc_t; | |
275 | ||
fdb4dad3 | 276 | /* QE UCC Slow */ |
23892e49 DL |
277 | typedef struct ucc_slow { |
278 | u32 gumr_l; /* UCCx general mode register (low) */ | |
279 | u32 gumr_h; /* UCCx general mode register (high) */ | |
280 | u16 upsmr; /* UCCx protocol-specific mode register */ | |
281 | u8 res0[0x2]; | |
282 | u16 utodr; /* UCCx transmit on demand register */ | |
283 | u16 udsr; /* UCCx data synchronization register */ | |
284 | u16 ucce; /* UCCx event register */ | |
285 | u8 res1[0x2]; | |
286 | u16 uccm; /* UCCx mask register */ | |
287 | u8 res2[0x1]; | |
288 | u8 uccs; /* UCCx status register */ | |
289 | u8 res3[0x24]; | |
290 | u16 utpt; | |
291 | u8 guemr; /* UCC general extended mode register */ | |
292 | u8 res4[0x200 - 0x091]; | |
293 | } __attribute__ ((packed)) ucc_slow_t; | |
294 | ||
da9d4610 AF |
295 | typedef struct ucc_mii_mng { |
296 | u32 miimcfg; /* MII management configuration reg */ | |
297 | u32 miimcom; /* MII management command reg */ | |
298 | u32 miimadd; /* MII management address reg */ | |
299 | u32 miimcon; /* MII management control reg */ | |
300 | u32 miimstat; /* MII management status reg */ | |
301 | u32 miimind; /* MII management indication reg */ | |
302 | u32 ifctl; /* interface control reg */ | |
303 | u32 ifstat; /* interface statux reg */ | |
304 | } __attribute__ ((packed))uec_mii_t; | |
305 | ||
23892e49 DL |
306 | typedef struct ucc_ethernet { |
307 | u32 maccfg1; /* mac configuration reg. 1 */ | |
308 | u32 maccfg2; /* mac configuration reg. 2 */ | |
309 | u32 ipgifg; /* interframe gap reg. */ | |
310 | u32 hafdup; /* half-duplex reg. */ | |
311 | u8 res1[0x10]; | |
312 | u32 miimcfg; /* MII management configuration reg */ | |
313 | u32 miimcom; /* MII management command reg */ | |
314 | u32 miimadd; /* MII management address reg */ | |
315 | u32 miimcon; /* MII management control reg */ | |
316 | u32 miimstat; /* MII management status reg */ | |
317 | u32 miimind; /* MII management indication reg */ | |
318 | u32 ifctl; /* interface control reg */ | |
319 | u32 ifstat; /* interface statux reg */ | |
320 | u32 macstnaddr1; /* mac station address part 1 reg */ | |
321 | u32 macstnaddr2; /* mac station address part 2 reg */ | |
322 | u8 res2[0x8]; | |
323 | u32 uempr; /* UCC Ethernet Mac parameter reg */ | |
324 | u32 utbipar; /* UCC tbi address reg */ | |
325 | u16 uescr; /* UCC Ethernet statistics control reg */ | |
326 | u8 res3[0x180 - 0x15A]; | |
327 | u32 tx64; /* Total number of frames (including bad | |
328 | * frames) transmitted that were exactly | |
329 | * of the minimal length (64 for un tagged, | |
330 | * 68 for tagged, or with length exactly | |
331 | * equal to the parameter MINLength */ | |
332 | u32 tx127; /* Total number of frames (including bad | |
333 | * frames) transmitted that were between | |
334 | * MINLength (Including FCS length==4) | |
335 | * and 127 octets */ | |
336 | u32 tx255; /* Total number of frames (including bad | |
337 | * frames) transmitted that were between | |
338 | * 128 (Including FCS length==4) and 255 | |
339 | * octets */ | |
340 | u32 rx64; /* Total number of frames received including | |
341 | * bad frames that were exactly of the | |
342 | * mninimal length (64 bytes) */ | |
343 | u32 rx127; /* Total number of frames (including bad | |
344 | * frames) received that were between | |
345 | * MINLength (Including FCS length==4) | |
346 | * and 127 octets */ | |
347 | u32 rx255; /* Total number of frames (including | |
348 | * bad frames) received that were between | |
349 | * 128 (Including FCS length==4) and 255 | |
350 | * octets */ | |
351 | u32 txok; /* Total number of octets residing in frames | |
352 | * that where involved in succesfull | |
353 | * transmission */ | |
354 | u16 txcf; /* Total number of PAUSE control frames | |
355 | * transmitted by this MAC */ | |
356 | u8 res4[0x2]; | |
357 | u32 tmca; /* Total number of frames that were transmitted | |
358 | * succesfully with the group address bit set | |
359 | * that are not broadcast frames */ | |
360 | u32 tbca; /* Total number of frames transmitted | |
361 | * succesfully that had destination address | |
362 | * field equal to the broadcast address */ | |
363 | u32 rxfok; /* Total number of frames received OK */ | |
364 | u32 rxbok; /* Total number of octets received OK */ | |
365 | u32 rbyt; /* Total number of octets received including | |
366 | * octets in bad frames. Must be implemented | |
367 | * in HW because it includes octets in frames | |
368 | * that never even reach the UCC */ | |
369 | u32 rmca; /* Total number of frames that were received | |
370 | * succesfully with the group address bit set | |
371 | * that are not broadcast frames */ | |
372 | u32 rbca; /* Total number of frames received succesfully | |
373 | * that had destination address equal to the | |
374 | * broadcast address */ | |
375 | u32 scar; /* Statistics carry register */ | |
376 | u32 scam; /* Statistics caryy mask register */ | |
377 | u8 res5[0x200 - 0x1c4]; | |
378 | } __attribute__ ((packed)) uec_t; | |
379 | ||
fdb4dad3 | 380 | /* QE UCC Fast */ |
23892e49 DL |
381 | typedef struct ucc_fast { |
382 | u32 gumr; /* UCCx general mode register */ | |
383 | u32 upsmr; /* UCCx protocol-specific mode register */ | |
384 | u16 utodr; /* UCCx transmit on demand register */ | |
385 | u8 res0[0x2]; | |
386 | u16 udsr; /* UCCx data synchronization register */ | |
387 | u8 res1[0x2]; | |
388 | u32 ucce; /* UCCx event register */ | |
389 | u32 uccm; /* UCCx mask register. */ | |
390 | u8 uccs; /* UCCx status register */ | |
391 | u8 res2[0x7]; | |
392 | u32 urfb; /* UCC receive FIFO base */ | |
393 | u16 urfs; /* UCC receive FIFO size */ | |
394 | u8 res3[0x2]; | |
395 | u16 urfet; /* UCC receive FIFO emergency threshold */ | |
396 | u16 urfset; /* UCC receive FIFO special emergency | |
397 | * threshold */ | |
398 | u32 utfb; /* UCC transmit FIFO base */ | |
399 | u16 utfs; /* UCC transmit FIFO size */ | |
400 | u8 res4[0x2]; | |
401 | u16 utfet; /* UCC transmit FIFO emergency threshold */ | |
402 | u8 res5[0x2]; | |
403 | u16 utftt; /* UCC transmit FIFO transmit threshold */ | |
404 | u8 res6[0x2]; | |
405 | u16 utpt; /* UCC transmit polling timer */ | |
406 | u8 res7[0x2]; | |
407 | u32 urtry; /* UCC retry counter register */ | |
408 | u8 res8[0x4C]; | |
409 | u8 guemr; /* UCC general extended mode register */ | |
410 | u8 res9[0x100 - 0x091]; | |
411 | uec_t ucc_eth; | |
412 | } __attribute__ ((packed)) ucc_fast_t; | |
413 | ||
fdb4dad3 | 414 | /* QE UCC */ |
23892e49 DL |
415 | typedef struct ucc_common { |
416 | u8 res1[0x90]; | |
417 | u8 guemr; | |
418 | u8 res2[0x200 - 0x091]; | |
419 | } __attribute__ ((packed)) ucc_common_t; | |
420 | ||
421 | typedef struct ucc { | |
422 | union { | |
423 | ucc_slow_t slow; | |
424 | ucc_fast_t fast; | |
425 | ucc_common_t common; | |
426 | }; | |
427 | } __attribute__ ((packed)) ucc_t; | |
428 | ||
fdb4dad3 | 429 | /* MultiPHY UTOPIA POS Controllers (UPC) */ |
23892e49 DL |
430 | typedef struct upc { |
431 | u32 upgcr; /* UTOPIA/POS general configuration register */ | |
432 | u32 uplpa; /* UTOPIA/POS last PHY address */ | |
433 | u32 uphec; /* ATM HEC register */ | |
434 | u32 upuc; /* UTOPIA/POS UCC configuration */ | |
435 | u32 updc1; /* UTOPIA/POS device 1 configuration */ | |
436 | u32 updc2; /* UTOPIA/POS device 2 configuration */ | |
437 | u32 updc3; /* UTOPIA/POS device 3 configuration */ | |
438 | u32 updc4; /* UTOPIA/POS device 4 configuration */ | |
439 | u32 upstpa; /* UTOPIA/POS STPA threshold */ | |
440 | u8 res0[0xC]; | |
441 | u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ | |
442 | u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ | |
443 | u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ | |
444 | u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ | |
445 | u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ | |
446 | u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ | |
447 | u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ | |
448 | u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ | |
449 | u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ | |
450 | u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ | |
451 | u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ | |
452 | u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ | |
453 | u32 upde1; /* UTOPIA/POS device 1 event */ | |
454 | u32 upde2; /* UTOPIA/POS device 2 event */ | |
455 | u32 upde3; /* UTOPIA/POS device 3 event */ | |
456 | u32 upde4; /* UTOPIA/POS device 4 event */ | |
457 | u16 uprp1; | |
458 | u16 uprp2; | |
459 | u16 uprp3; | |
460 | u16 uprp4; | |
461 | u8 res1[0x8]; | |
462 | u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ | |
463 | u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ | |
464 | u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ | |
465 | u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ | |
466 | u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ | |
467 | u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ | |
468 | u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ | |
469 | u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ | |
470 | u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ | |
471 | u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ | |
472 | u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ | |
473 | u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ | |
474 | u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ | |
475 | u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ | |
476 | u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ | |
477 | u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ | |
478 | u32 uper1; /* Device 1 port enable register */ | |
479 | u32 uper2; /* Device 2 port enable register */ | |
480 | u32 uper3; /* Device 3 port enable register */ | |
481 | u32 uper4; /* Device 4 port enable register */ | |
482 | u8 res2[0x150]; | |
483 | } __attribute__ ((packed)) upc_t; | |
484 | ||
fdb4dad3 | 485 | /* SDMA */ |
23892e49 DL |
486 | typedef struct sdma { |
487 | u32 sdsr; /* Serial DMA status register */ | |
488 | u32 sdmr; /* Serial DMA mode register */ | |
489 | u32 sdtr1; /* SDMA system bus threshold register */ | |
490 | u32 sdtr2; /* SDMA secondary bus threshold register */ | |
491 | u32 sdhy1; /* SDMA system bus hysteresis register */ | |
492 | u32 sdhy2; /* SDMA secondary bus hysteresis register */ | |
493 | u32 sdta1; /* SDMA system bus address register */ | |
494 | u32 sdta2; /* SDMA secondary bus address register */ | |
495 | u32 sdtm1; /* SDMA system bus MSNUM register */ | |
496 | u32 sdtm2; /* SDMA secondary bus MSNUM register */ | |
497 | u8 res0[0x10]; | |
498 | u32 sdaqr; /* SDMA address bus qualify register */ | |
499 | u32 sdaqmr; /* SDMA address bus qualify mask register */ | |
500 | u8 res1[0x4]; | |
501 | u32 sdwbcr; /* SDMA CAM entries base register */ | |
502 | u8 res2[0x38]; | |
503 | } __attribute__ ((packed)) sdma_t; | |
504 | ||
fdb4dad3 | 505 | /* Debug Space */ |
23892e49 DL |
506 | typedef struct dbg { |
507 | u32 bpdcr; /* Breakpoint debug command register */ | |
508 | u32 bpdsr; /* Breakpoint debug status register */ | |
509 | u32 bpdmr; /* Breakpoint debug mask register */ | |
510 | u32 bprmrr0; /* Breakpoint request mode risc register 0 */ | |
511 | u32 bprmrr1; /* Breakpoint request mode risc register 1 */ | |
512 | u8 res0[0x8]; | |
513 | u32 bprmtr0; /* Breakpoint request mode trb register 0 */ | |
514 | u32 bprmtr1; /* Breakpoint request mode trb register 1 */ | |
515 | u8 res1[0x8]; | |
516 | u32 bprmir; /* Breakpoint request mode immediate register */ | |
517 | u32 bprmsr; /* Breakpoint request mode serial register */ | |
518 | u32 bpemr; /* Breakpoint exit mode register */ | |
519 | u8 res2[0x48]; | |
520 | } __attribute__ ((packed)) dbg_t; | |
521 | ||
b8ec2385 TT |
522 | /* |
523 | * RISC Special Registers (Trap and Breakpoint). These are described in | |
524 | * the QE Developer's Handbook. | |
23892e49 DL |
525 | */ |
526 | typedef struct rsp { | |
b8ec2385 TT |
527 | u32 tibcr[16]; /* Trap/instruction breakpoint control regs */ |
528 | u8 res0[64]; | |
529 | u32 ibcr0; | |
530 | u32 ibs0; | |
531 | u32 ibcnr0; | |
532 | u8 res1[4]; | |
533 | u32 ibcr1; | |
534 | u32 ibs1; | |
535 | u32 ibcnr1; | |
536 | u32 npcr; | |
537 | u32 dbcr; | |
538 | u32 dbar; | |
539 | u32 dbamr; | |
540 | u32 dbsr; | |
541 | u32 dbcnr; | |
542 | u8 res2[12]; | |
543 | u32 dbdr_h; | |
544 | u32 dbdr_l; | |
545 | u32 dbdmr_h; | |
546 | u32 dbdmr_l; | |
547 | u32 bsr; | |
548 | u32 bor; | |
549 | u32 bior; | |
550 | u8 res3[4]; | |
551 | u32 iatr[4]; | |
552 | u32 eccr; /* Exception control configuration register */ | |
553 | u32 eicr; | |
554 | u8 res4[0x100-0xf8]; | |
23892e49 DL |
555 | } __attribute__ ((packed)) rsp_t; |
556 | ||
557 | typedef struct qe_immap { | |
558 | qe_iram_t iram; /* I-RAM */ | |
559 | qe_ic_t ic; /* Interrupt Controller */ | |
560 | cp_qe_t cp; /* Communications Processor */ | |
561 | qe_mux_t qmx; /* QE Multiplexer */ | |
562 | qe_timers_t qet; /* QE Timers */ | |
563 | spi_t spi[0x2]; /* spi */ | |
564 | mcc_t mcc; /* mcc */ | |
565 | qe_brg_t brg; /* brg */ | |
566 | usb_t usb; /* USB */ | |
567 | si1_t si1; /* SI */ | |
568 | u8 res11[0x800]; | |
569 | sir_t sir; /* SI Routing Tables */ | |
570 | ucc_t ucc1; /* ucc1 */ | |
571 | ucc_t ucc3; /* ucc3 */ | |
572 | ucc_t ucc5; /* ucc5 */ | |
573 | ucc_t ucc7; /* ucc7 */ | |
574 | u8 res12[0x600]; | |
575 | upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ | |
576 | ucc_t ucc2; /* ucc2 */ | |
577 | ucc_t ucc4; /* ucc4 */ | |
578 | ucc_t ucc6; /* ucc6 */ | |
579 | ucc_t ucc8; /* ucc8 */ | |
580 | u8 res13[0x600]; | |
581 | upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ | |
582 | sdma_t sdma; /* SDMA */ | |
583 | dbg_t dbg; /* Debug Space */ | |
584 | rsp_t rsp[0x2]; /* RISC Special Registers | |
585 | * (Trap and Breakpoint) */ | |
586 | u8 res14[0x300]; | |
587 | u8 res15[0x3A00]; | |
588 | u8 res16[0x8000]; /* 0x108000 - 0x110000 */ | |
fdb4dad3 | 589 | u8 muram[QE_MURAM_SIZE]; |
23892e49 DL |
590 | } __attribute__ ((packed)) qe_map_t; |
591 | ||
592 | extern qe_map_t *qe_immr; | |
593 | ||
594 | #endif /* __IMMAP_QE_H__ */ |