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4a77a6cf JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_IOMMU_H | |
20 | #define __LINUX_IOMMU_H | |
21 | ||
74315ccc | 22 | #include <linux/errno.h> |
9a08d376 | 23 | #include <linux/err.h> |
d0f60a44 | 24 | #include <linux/of.h> |
76582d0a | 25 | #include <linux/types.h> |
315786eb | 26 | #include <linux/scatterlist.h> |
56fa4849 | 27 | #include <trace/events/iommu.h> |
74315ccc | 28 | |
ca13bb3d WD |
29 | #define IOMMU_READ (1 << 0) |
30 | #define IOMMU_WRITE (1 << 1) | |
31 | #define IOMMU_CACHE (1 << 2) /* DMA cache coherency */ | |
a720b41c | 32 | #define IOMMU_NOEXEC (1 << 3) |
31e6850e | 33 | #define IOMMU_MMIO (1 << 4) /* e.g. things like MSI doorbells */ |
579b2a65 MH |
34 | /* |
35 | * This is to make the IOMMU API setup privileged | |
36 | * mapppings accessible by the master only at higher | |
37 | * privileged execution level and inaccessible at | |
38 | * less privileged levels. | |
39 | */ | |
40 | #define IOMMU_PRIV (1 << 5) | |
4a77a6cf | 41 | |
905d66c1 | 42 | struct iommu_ops; |
d72e31c9 | 43 | struct iommu_group; |
ff21776d | 44 | struct bus_type; |
4a77a6cf | 45 | struct device; |
4f3f8d9d | 46 | struct iommu_domain; |
ba1eabfa | 47 | struct notifier_block; |
4f3f8d9d OBC |
48 | |
49 | /* iommu fault flags */ | |
50 | #define IOMMU_FAULT_READ 0x0 | |
51 | #define IOMMU_FAULT_WRITE 0x1 | |
52 | ||
53 | typedef int (*iommu_fault_handler_t)(struct iommu_domain *, | |
77ca2332 | 54 | struct device *, unsigned long, int, void *); |
4a77a6cf | 55 | |
0ff64f80 JR |
56 | struct iommu_domain_geometry { |
57 | dma_addr_t aperture_start; /* First address that can be mapped */ | |
58 | dma_addr_t aperture_end; /* Last address that can be mapped */ | |
59 | bool force_aperture; /* DMA only allowed in mappable range? */ | |
60 | }; | |
61 | ||
8539c7c1 JR |
62 | /* Domain feature flags */ |
63 | #define __IOMMU_DOMAIN_PAGING (1U << 0) /* Support for iommu_map/unmap */ | |
64 | #define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API | |
65 | implementation */ | |
66 | #define __IOMMU_DOMAIN_PT (1U << 2) /* Domain is identity mapped */ | |
67 | ||
68 | /* | |
69 | * This are the possible domain-types | |
70 | * | |
71 | * IOMMU_DOMAIN_BLOCKED - All DMA is blocked, can be used to isolate | |
72 | * devices | |
73 | * IOMMU_DOMAIN_IDENTITY - DMA addresses are system physical addresses | |
74 | * IOMMU_DOMAIN_UNMANAGED - DMA mappings managed by IOMMU-API user, used | |
75 | * for VMs | |
76 | * IOMMU_DOMAIN_DMA - Internally used for DMA-API implementations. | |
77 | * This flag allows IOMMU drivers to implement | |
78 | * certain optimizations for these domains | |
79 | */ | |
80 | #define IOMMU_DOMAIN_BLOCKED (0U) | |
81 | #define IOMMU_DOMAIN_IDENTITY (__IOMMU_DOMAIN_PT) | |
82 | #define IOMMU_DOMAIN_UNMANAGED (__IOMMU_DOMAIN_PAGING) | |
83 | #define IOMMU_DOMAIN_DMA (__IOMMU_DOMAIN_PAGING | \ | |
84 | __IOMMU_DOMAIN_DMA_API) | |
85 | ||
4a77a6cf | 86 | struct iommu_domain { |
8539c7c1 | 87 | unsigned type; |
b22f6434 | 88 | const struct iommu_ops *ops; |
d16e0faa | 89 | unsigned long pgsize_bitmap; /* Bitmap of page sizes in use */ |
4f3f8d9d | 90 | iommu_fault_handler_t handler; |
77ca2332 | 91 | void *handler_token; |
0ff64f80 | 92 | struct iommu_domain_geometry geometry; |
0db2e5d1 | 93 | void *iova_cookie; |
4a77a6cf JR |
94 | }; |
95 | ||
1aed0748 JR |
96 | enum iommu_cap { |
97 | IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA | |
98 | transactions */ | |
99 | IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */ | |
c4986649 | 100 | IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */ |
1aed0748 | 101 | }; |
dbb9fd86 | 102 | |
7cabf491 VS |
103 | /* |
104 | * Following constraints are specifc to FSL_PAMUV1: | |
105 | * -aperture must be power of 2, and naturally aligned | |
106 | * -number of windows must be power of 2, and address space size | |
107 | * of each window is determined by aperture size / # of windows | |
108 | * -the actual size of the mapped region of a window must be power | |
109 | * of 2 starting with 4KB and physical address must be naturally | |
110 | * aligned. | |
111 | * DOMAIN_ATTR_FSL_PAMUV1 corresponds to the above mentioned contraints. | |
112 | * The caller can invoke iommu_domain_get_attr to check if the underlying | |
113 | * iommu implementation supports these constraints. | |
114 | */ | |
115 | ||
0cd76dd1 | 116 | enum iommu_attr { |
0ff64f80 | 117 | DOMAIN_ATTR_GEOMETRY, |
d2e12160 | 118 | DOMAIN_ATTR_PAGING, |
69356712 | 119 | DOMAIN_ATTR_WINDOWS, |
7cabf491 VS |
120 | DOMAIN_ATTR_FSL_PAMU_STASH, |
121 | DOMAIN_ATTR_FSL_PAMU_ENABLE, | |
122 | DOMAIN_ATTR_FSL_PAMUV1, | |
c02607aa | 123 | DOMAIN_ATTR_NESTING, /* two stages of translation */ |
a8b8a88a | 124 | DOMAIN_ATTR_MAX, |
0cd76dd1 JR |
125 | }; |
126 | ||
d30ddcaa | 127 | /* These are the possible reserved region types */ |
9d3a4de4 RM |
128 | enum iommu_resv_type { |
129 | /* Memory regions which must be mapped 1:1 at all times */ | |
130 | IOMMU_RESV_DIRECT, | |
131 | /* Arbitrary "never map this or give it to a device" address ranges */ | |
132 | IOMMU_RESV_RESERVED, | |
133 | /* Hardware MSI region (untranslated) */ | |
134 | IOMMU_RESV_MSI, | |
135 | /* Software-managed MSI translation window */ | |
136 | IOMMU_RESV_SW_MSI, | |
137 | }; | |
d30ddcaa | 138 | |
a1015c2b | 139 | /** |
e5b5234a | 140 | * struct iommu_resv_region - descriptor for a reserved memory region |
a1015c2b JR |
141 | * @list: Linked list pointers |
142 | * @start: System physical start address of the region | |
143 | * @length: Length of the region in bytes | |
144 | * @prot: IOMMU Protection flags (READ/WRITE/...) | |
d30ddcaa | 145 | * @type: Type of the reserved region |
a1015c2b | 146 | */ |
e5b5234a | 147 | struct iommu_resv_region { |
a1015c2b JR |
148 | struct list_head list; |
149 | phys_addr_t start; | |
150 | size_t length; | |
151 | int prot; | |
9d3a4de4 | 152 | enum iommu_resv_type type; |
a1015c2b JR |
153 | }; |
154 | ||
39d4ebb9 JR |
155 | #ifdef CONFIG_IOMMU_API |
156 | ||
7d3002cc OBC |
157 | /** |
158 | * struct iommu_ops - iommu ops and capabilities | |
0d9bacb6 MD |
159 | * @capable: check capability |
160 | * @domain_alloc: allocate iommu domain | |
161 | * @domain_free: free iommu domain | |
7d3002cc OBC |
162 | * @attach_dev: attach device to an iommu domain |
163 | * @detach_dev: detach device from an iommu domain | |
164 | * @map: map a physically contiguous memory region to an iommu domain | |
165 | * @unmap: unmap a physically contiguous memory region from an iommu domain | |
315786eb OH |
166 | * @map_sg: map a scatter-gather list of physically contiguous memory chunks |
167 | * to an iommu domain | |
7d3002cc | 168 | * @iova_to_phys: translate iova to physical address |
d72e31c9 AW |
169 | * @add_device: add device to iommu grouping |
170 | * @remove_device: remove device from iommu grouping | |
0d9bacb6 | 171 | * @device_group: find iommu group for a particular device |
0cd76dd1 JR |
172 | * @domain_get_attr: Query domain attributes |
173 | * @domain_set_attr: Change domain attributes | |
e5b5234a EA |
174 | * @get_resv_regions: Request list of reserved regions for a device |
175 | * @put_resv_regions: Free list of reserved regions for a device | |
176 | * @apply_resv_region: Temporary helper call-back for iova reserved ranges | |
0d9bacb6 MD |
177 | * @domain_window_enable: Configure and enable a particular window for a domain |
178 | * @domain_window_disable: Disable a particular window for a domain | |
179 | * @domain_set_windows: Set the number of windows for a domain | |
180 | * @domain_get_windows: Return the number of windows for a domain | |
d0f60a44 | 181 | * @of_xlate: add OF master IDs to iommu grouping |
d16e0faa | 182 | * @pgsize_bitmap: bitmap of all possible supported page sizes |
7d3002cc | 183 | */ |
4a77a6cf | 184 | struct iommu_ops { |
3c0e0ca0 | 185 | bool (*capable)(enum iommu_cap); |
938c4709 JR |
186 | |
187 | /* Domain allocation and freeing by the iommu driver */ | |
8539c7c1 | 188 | struct iommu_domain *(*domain_alloc)(unsigned iommu_domain_type); |
938c4709 JR |
189 | void (*domain_free)(struct iommu_domain *); |
190 | ||
4a77a6cf JR |
191 | int (*attach_dev)(struct iommu_domain *domain, struct device *dev); |
192 | void (*detach_dev)(struct iommu_domain *domain, struct device *dev); | |
67651786 | 193 | int (*map)(struct iommu_domain *domain, unsigned long iova, |
5009065d OBC |
194 | phys_addr_t paddr, size_t size, int prot); |
195 | size_t (*unmap)(struct iommu_domain *domain, unsigned long iova, | |
196 | size_t size); | |
315786eb OH |
197 | size_t (*map_sg)(struct iommu_domain *domain, unsigned long iova, |
198 | struct scatterlist *sg, unsigned int nents, int prot); | |
bb5547ac | 199 | phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova); |
d72e31c9 AW |
200 | int (*add_device)(struct device *dev); |
201 | void (*remove_device)(struct device *dev); | |
46c6b2bc | 202 | struct iommu_group *(*device_group)(struct device *dev); |
0cd76dd1 JR |
203 | int (*domain_get_attr)(struct iommu_domain *domain, |
204 | enum iommu_attr attr, void *data); | |
205 | int (*domain_set_attr)(struct iommu_domain *domain, | |
206 | enum iommu_attr attr, void *data); | |
d7787d57 | 207 | |
e5b5234a EA |
208 | /* Request/Free a list of reserved regions for a device */ |
209 | void (*get_resv_regions)(struct device *dev, struct list_head *list); | |
210 | void (*put_resv_regions)(struct device *dev, struct list_head *list); | |
211 | void (*apply_resv_region)(struct device *dev, | |
212 | struct iommu_domain *domain, | |
213 | struct iommu_resv_region *region); | |
a1015c2b | 214 | |
d7787d57 JR |
215 | /* Window handling functions */ |
216 | int (*domain_window_enable)(struct iommu_domain *domain, u32 wnd_nr, | |
80f97f0f | 217 | phys_addr_t paddr, u64 size, int prot); |
d7787d57 | 218 | void (*domain_window_disable)(struct iommu_domain *domain, u32 wnd_nr); |
0d9bacb6 | 219 | /* Set the number of windows per domain */ |
69356712 | 220 | int (*domain_set_windows)(struct iommu_domain *domain, u32 w_count); |
0d9bacb6 | 221 | /* Get the number of windows per domain */ |
69356712 | 222 | u32 (*domain_get_windows)(struct iommu_domain *domain); |
d7787d57 | 223 | |
d0f60a44 | 224 | int (*of_xlate)(struct device *dev, struct of_phandle_args *args); |
d0f60a44 | 225 | |
7d3002cc | 226 | unsigned long pgsize_bitmap; |
4a77a6cf JR |
227 | }; |
228 | ||
b0119e87 JR |
229 | /** |
230 | * struct iommu_device - IOMMU core representation of one IOMMU hardware | |
231 | * instance | |
232 | * @list: Used by the iommu-core to keep a list of registered iommus | |
233 | * @ops: iommu-ops for talking to this iommu | |
39ab9555 | 234 | * @dev: struct device for sysfs handling |
b0119e87 JR |
235 | */ |
236 | struct iommu_device { | |
237 | struct list_head list; | |
238 | const struct iommu_ops *ops; | |
c73e1ac8 | 239 | struct fwnode_handle *fwnode; |
39ab9555 | 240 | struct device dev; |
b0119e87 JR |
241 | }; |
242 | ||
243 | int iommu_device_register(struct iommu_device *iommu); | |
244 | void iommu_device_unregister(struct iommu_device *iommu); | |
39ab9555 JR |
245 | int iommu_device_sysfs_add(struct iommu_device *iommu, |
246 | struct device *parent, | |
247 | const struct attribute_group **groups, | |
248 | const char *fmt, ...) __printf(4, 5); | |
249 | void iommu_device_sysfs_remove(struct iommu_device *iommu); | |
e3d10af1 JR |
250 | int iommu_device_link(struct iommu_device *iommu, struct device *link); |
251 | void iommu_device_unlink(struct iommu_device *iommu, struct device *link); | |
b0119e87 JR |
252 | |
253 | static inline void iommu_device_set_ops(struct iommu_device *iommu, | |
254 | const struct iommu_ops *ops) | |
255 | { | |
256 | iommu->ops = ops; | |
257 | } | |
258 | ||
c73e1ac8 JR |
259 | static inline void iommu_device_set_fwnode(struct iommu_device *iommu, |
260 | struct fwnode_handle *fwnode) | |
261 | { | |
262 | iommu->fwnode = fwnode; | |
263 | } | |
264 | ||
d72e31c9 AW |
265 | #define IOMMU_GROUP_NOTIFY_ADD_DEVICE 1 /* Device added */ |
266 | #define IOMMU_GROUP_NOTIFY_DEL_DEVICE 2 /* Pre Device removed */ | |
267 | #define IOMMU_GROUP_NOTIFY_BIND_DRIVER 3 /* Pre Driver bind */ | |
268 | #define IOMMU_GROUP_NOTIFY_BOUND_DRIVER 4 /* Post Driver bind */ | |
269 | #define IOMMU_GROUP_NOTIFY_UNBIND_DRIVER 5 /* Pre Driver unbind */ | |
270 | #define IOMMU_GROUP_NOTIFY_UNBOUND_DRIVER 6 /* Post Driver unbind */ | |
271 | ||
b22f6434 | 272 | extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops); |
a1b60c1c | 273 | extern bool iommu_present(struct bus_type *bus); |
3c0e0ca0 | 274 | extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap); |
905d66c1 | 275 | extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus); |
aa16bea9 | 276 | extern struct iommu_group *iommu_group_get_by_id(int id); |
4a77a6cf JR |
277 | extern void iommu_domain_free(struct iommu_domain *domain); |
278 | extern int iommu_attach_device(struct iommu_domain *domain, | |
279 | struct device *dev); | |
280 | extern void iommu_detach_device(struct iommu_domain *domain, | |
281 | struct device *dev); | |
2c1296d9 | 282 | extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev); |
cefc53c7 | 283 | extern int iommu_map(struct iommu_domain *domain, unsigned long iova, |
7d3002cc OBC |
284 | phys_addr_t paddr, size_t size, int prot); |
285 | extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, | |
286 | size_t size); | |
315786eb OH |
287 | extern size_t default_iommu_map_sg(struct iommu_domain *domain, unsigned long iova, |
288 | struct scatterlist *sg,unsigned int nents, | |
289 | int prot); | |
bb5547ac | 290 | extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova); |
4f3f8d9d | 291 | extern void iommu_set_fault_handler(struct iommu_domain *domain, |
77ca2332 | 292 | iommu_fault_handler_t handler, void *token); |
d72e31c9 | 293 | |
e5b5234a EA |
294 | extern void iommu_get_resv_regions(struct device *dev, struct list_head *list); |
295 | extern void iommu_put_resv_regions(struct device *dev, struct list_head *list); | |
d290f1e7 | 296 | extern int iommu_request_dm_for_dev(struct device *dev); |
2b20cbba | 297 | extern struct iommu_resv_region * |
9d3a4de4 RM |
298 | iommu_alloc_resv_region(phys_addr_t start, size_t length, int prot, |
299 | enum iommu_resv_type type); | |
6c65fb31 EA |
300 | extern int iommu_get_group_resv_regions(struct iommu_group *group, |
301 | struct list_head *head); | |
a1015c2b | 302 | |
d72e31c9 AW |
303 | extern int iommu_attach_group(struct iommu_domain *domain, |
304 | struct iommu_group *group); | |
305 | extern void iommu_detach_group(struct iommu_domain *domain, | |
306 | struct iommu_group *group); | |
307 | extern struct iommu_group *iommu_group_alloc(void); | |
308 | extern void *iommu_group_get_iommudata(struct iommu_group *group); | |
309 | extern void iommu_group_set_iommudata(struct iommu_group *group, | |
310 | void *iommu_data, | |
311 | void (*release)(void *iommu_data)); | |
312 | extern int iommu_group_set_name(struct iommu_group *group, const char *name); | |
313 | extern int iommu_group_add_device(struct iommu_group *group, | |
314 | struct device *dev); | |
315 | extern void iommu_group_remove_device(struct device *dev); | |
316 | extern int iommu_group_for_each_dev(struct iommu_group *group, void *data, | |
317 | int (*fn)(struct device *, void *)); | |
318 | extern struct iommu_group *iommu_group_get(struct device *dev); | |
13f59a78 | 319 | extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group); |
d72e31c9 AW |
320 | extern void iommu_group_put(struct iommu_group *group); |
321 | extern int iommu_group_register_notifier(struct iommu_group *group, | |
322 | struct notifier_block *nb); | |
323 | extern int iommu_group_unregister_notifier(struct iommu_group *group, | |
324 | struct notifier_block *nb); | |
325 | extern int iommu_group_id(struct iommu_group *group); | |
104a1c13 | 326 | extern struct iommu_group *iommu_group_get_for_dev(struct device *dev); |
6827ca83 | 327 | extern struct iommu_domain *iommu_group_default_domain(struct iommu_group *); |
4f3f8d9d | 328 | |
0cd76dd1 JR |
329 | extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr, |
330 | void *data); | |
331 | extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr, | |
332 | void *data); | |
4f3f8d9d | 333 | |
d7787d57 JR |
334 | /* Window handling function prototypes */ |
335 | extern int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr, | |
80f97f0f VS |
336 | phys_addr_t offset, u64 size, |
337 | int prot); | |
d7787d57 | 338 | extern void iommu_domain_window_disable(struct iommu_domain *domain, u32 wnd_nr); |
4f3f8d9d OBC |
339 | /** |
340 | * report_iommu_fault() - report about an IOMMU fault to the IOMMU framework | |
341 | * @domain: the iommu domain where the fault has happened | |
342 | * @dev: the device where the fault has happened | |
343 | * @iova: the faulting address | |
344 | * @flags: mmu fault flags (e.g. IOMMU_FAULT_READ/IOMMU_FAULT_WRITE/...) | |
345 | * | |
346 | * This function should be called by the low-level IOMMU implementations | |
347 | * whenever IOMMU faults happen, to allow high-level users, that are | |
348 | * interested in such events, to know about them. | |
349 | * | |
350 | * This event may be useful for several possible use cases: | |
351 | * - mere logging of the event | |
352 | * - dynamic TLB/PTE loading | |
353 | * - if restarting of the faulting device is required | |
354 | * | |
355 | * Returns 0 on success and an appropriate error code otherwise (if dynamic | |
356 | * PTE/TLB loading will one day be supported, implementations will be able | |
357 | * to tell whether it succeeded or not according to this return value). | |
0ed6d2d2 OBC |
358 | * |
359 | * Specifically, -ENOSYS is returned if a fault handler isn't installed | |
360 | * (though fault handlers can also return -ENOSYS, in case they want to | |
361 | * elicit the default behavior of the IOMMU drivers). | |
4f3f8d9d OBC |
362 | */ |
363 | static inline int report_iommu_fault(struct iommu_domain *domain, | |
364 | struct device *dev, unsigned long iova, int flags) | |
365 | { | |
0ed6d2d2 | 366 | int ret = -ENOSYS; |
4a77a6cf | 367 | |
4f3f8d9d OBC |
368 | /* |
369 | * if upper layers showed interest and installed a fault handler, | |
370 | * invoke it. | |
371 | */ | |
372 | if (domain->handler) | |
77ca2332 OBC |
373 | ret = domain->handler(domain, dev, iova, flags, |
374 | domain->handler_token); | |
4a77a6cf | 375 | |
56fa4849 | 376 | trace_io_page_fault(dev, iova, flags); |
4f3f8d9d | 377 | return ret; |
4a77a6cf JR |
378 | } |
379 | ||
315786eb OH |
380 | static inline size_t iommu_map_sg(struct iommu_domain *domain, |
381 | unsigned long iova, struct scatterlist *sg, | |
382 | unsigned int nents, int prot) | |
383 | { | |
384 | return domain->ops->map_sg(domain, iova, sg, nents, prot); | |
385 | } | |
386 | ||
5e62292b JR |
387 | /* PCI device grouping function */ |
388 | extern struct iommu_group *pci_device_group(struct device *dev); | |
6eab556a JR |
389 | /* Generic device grouping function */ |
390 | extern struct iommu_group *generic_device_group(struct device *dev); | |
5e62292b | 391 | |
57f98d2f RM |
392 | /** |
393 | * struct iommu_fwspec - per-device IOMMU instance data | |
394 | * @ops: ops for this device's IOMMU | |
395 | * @iommu_fwnode: firmware handle for this device's IOMMU | |
396 | * @iommu_priv: IOMMU driver private data for this device | |
397 | * @num_ids: number of associated device IDs | |
398 | * @ids: IDs which this device may present to the IOMMU | |
399 | */ | |
400 | struct iommu_fwspec { | |
401 | const struct iommu_ops *ops; | |
402 | struct fwnode_handle *iommu_fwnode; | |
403 | void *iommu_priv; | |
404 | unsigned int num_ids; | |
405 | u32 ids[1]; | |
406 | }; | |
407 | ||
408 | int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, | |
409 | const struct iommu_ops *ops); | |
410 | void iommu_fwspec_free(struct device *dev); | |
411 | int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids); | |
534766df | 412 | const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode); |
57f98d2f | 413 | |
4a77a6cf JR |
414 | #else /* CONFIG_IOMMU_API */ |
415 | ||
39d4ebb9 | 416 | struct iommu_ops {}; |
d72e31c9 | 417 | struct iommu_group {}; |
57f98d2f | 418 | struct iommu_fwspec {}; |
b0119e87 | 419 | struct iommu_device {}; |
4a77a6cf | 420 | |
a1b60c1c | 421 | static inline bool iommu_present(struct bus_type *bus) |
4a77a6cf JR |
422 | { |
423 | return false; | |
424 | } | |
425 | ||
3c0e0ca0 JR |
426 | static inline bool iommu_capable(struct bus_type *bus, enum iommu_cap cap) |
427 | { | |
428 | return false; | |
429 | } | |
430 | ||
905d66c1 | 431 | static inline struct iommu_domain *iommu_domain_alloc(struct bus_type *bus) |
4a77a6cf JR |
432 | { |
433 | return NULL; | |
434 | } | |
435 | ||
b62dfd29 AK |
436 | static inline struct iommu_group *iommu_group_get_by_id(int id) |
437 | { | |
438 | return NULL; | |
439 | } | |
440 | ||
4a77a6cf JR |
441 | static inline void iommu_domain_free(struct iommu_domain *domain) |
442 | { | |
443 | } | |
444 | ||
445 | static inline int iommu_attach_device(struct iommu_domain *domain, | |
446 | struct device *dev) | |
447 | { | |
448 | return -ENODEV; | |
449 | } | |
450 | ||
451 | static inline void iommu_detach_device(struct iommu_domain *domain, | |
452 | struct device *dev) | |
453 | { | |
454 | } | |
455 | ||
2c1296d9 JR |
456 | static inline struct iommu_domain *iommu_get_domain_for_dev(struct device *dev) |
457 | { | |
458 | return NULL; | |
459 | } | |
460 | ||
cefc53c7 JR |
461 | static inline int iommu_map(struct iommu_domain *domain, unsigned long iova, |
462 | phys_addr_t paddr, int gfp_order, int prot) | |
463 | { | |
464 | return -ENODEV; | |
465 | } | |
466 | ||
467 | static inline int iommu_unmap(struct iommu_domain *domain, unsigned long iova, | |
468 | int gfp_order) | |
469 | { | |
470 | return -ENODEV; | |
471 | } | |
472 | ||
315786eb OH |
473 | static inline size_t iommu_map_sg(struct iommu_domain *domain, |
474 | unsigned long iova, struct scatterlist *sg, | |
475 | unsigned int nents, int prot) | |
476 | { | |
477 | return -ENODEV; | |
478 | } | |
479 | ||
d7787d57 JR |
480 | static inline int iommu_domain_window_enable(struct iommu_domain *domain, |
481 | u32 wnd_nr, phys_addr_t paddr, | |
80f97f0f | 482 | u64 size, int prot) |
d7787d57 JR |
483 | { |
484 | return -ENODEV; | |
485 | } | |
486 | ||
487 | static inline void iommu_domain_window_disable(struct iommu_domain *domain, | |
488 | u32 wnd_nr) | |
489 | { | |
490 | } | |
491 | ||
bb5547ac | 492 | static inline phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) |
4a77a6cf JR |
493 | { |
494 | return 0; | |
495 | } | |
496 | ||
4f3f8d9d | 497 | static inline void iommu_set_fault_handler(struct iommu_domain *domain, |
77ca2332 | 498 | iommu_fault_handler_t handler, void *token) |
4f3f8d9d OBC |
499 | { |
500 | } | |
501 | ||
e5b5234a | 502 | static inline void iommu_get_resv_regions(struct device *dev, |
a1015c2b JR |
503 | struct list_head *list) |
504 | { | |
505 | } | |
506 | ||
e5b5234a | 507 | static inline void iommu_put_resv_regions(struct device *dev, |
a1015c2b JR |
508 | struct list_head *list) |
509 | { | |
510 | } | |
511 | ||
6c65fb31 EA |
512 | static inline int iommu_get_group_resv_regions(struct iommu_group *group, |
513 | struct list_head *head) | |
514 | { | |
515 | return -ENODEV; | |
516 | } | |
517 | ||
d290f1e7 JR |
518 | static inline int iommu_request_dm_for_dev(struct device *dev) |
519 | { | |
520 | return -ENODEV; | |
521 | } | |
522 | ||
bef83de5 AW |
523 | static inline int iommu_attach_group(struct iommu_domain *domain, |
524 | struct iommu_group *group) | |
d72e31c9 AW |
525 | { |
526 | return -ENODEV; | |
527 | } | |
528 | ||
bef83de5 AW |
529 | static inline void iommu_detach_group(struct iommu_domain *domain, |
530 | struct iommu_group *group) | |
d72e31c9 AW |
531 | { |
532 | } | |
533 | ||
bef83de5 | 534 | static inline struct iommu_group *iommu_group_alloc(void) |
d72e31c9 AW |
535 | { |
536 | return ERR_PTR(-ENODEV); | |
537 | } | |
538 | ||
bef83de5 | 539 | static inline void *iommu_group_get_iommudata(struct iommu_group *group) |
d72e31c9 AW |
540 | { |
541 | return NULL; | |
542 | } | |
543 | ||
bef83de5 AW |
544 | static inline void iommu_group_set_iommudata(struct iommu_group *group, |
545 | void *iommu_data, | |
546 | void (*release)(void *iommu_data)) | |
d72e31c9 AW |
547 | { |
548 | } | |
549 | ||
bef83de5 AW |
550 | static inline int iommu_group_set_name(struct iommu_group *group, |
551 | const char *name) | |
d72e31c9 AW |
552 | { |
553 | return -ENODEV; | |
554 | } | |
555 | ||
bef83de5 AW |
556 | static inline int iommu_group_add_device(struct iommu_group *group, |
557 | struct device *dev) | |
d72e31c9 AW |
558 | { |
559 | return -ENODEV; | |
560 | } | |
561 | ||
bef83de5 | 562 | static inline void iommu_group_remove_device(struct device *dev) |
d72e31c9 AW |
563 | { |
564 | } | |
565 | ||
bef83de5 AW |
566 | static inline int iommu_group_for_each_dev(struct iommu_group *group, |
567 | void *data, | |
568 | int (*fn)(struct device *, void *)) | |
d72e31c9 AW |
569 | { |
570 | return -ENODEV; | |
571 | } | |
572 | ||
bef83de5 | 573 | static inline struct iommu_group *iommu_group_get(struct device *dev) |
d72e31c9 AW |
574 | { |
575 | return NULL; | |
576 | } | |
577 | ||
bef83de5 | 578 | static inline void iommu_group_put(struct iommu_group *group) |
d72e31c9 AW |
579 | { |
580 | } | |
581 | ||
bef83de5 AW |
582 | static inline int iommu_group_register_notifier(struct iommu_group *group, |
583 | struct notifier_block *nb) | |
1460432c AW |
584 | { |
585 | return -ENODEV; | |
586 | } | |
587 | ||
bef83de5 AW |
588 | static inline int iommu_group_unregister_notifier(struct iommu_group *group, |
589 | struct notifier_block *nb) | |
d72e31c9 AW |
590 | { |
591 | return 0; | |
592 | } | |
593 | ||
bef83de5 | 594 | static inline int iommu_group_id(struct iommu_group *group) |
d72e31c9 AW |
595 | { |
596 | return -ENODEV; | |
597 | } | |
1460432c | 598 | |
0cd76dd1 JR |
599 | static inline int iommu_domain_get_attr(struct iommu_domain *domain, |
600 | enum iommu_attr attr, void *data) | |
601 | { | |
602 | return -EINVAL; | |
603 | } | |
604 | ||
605 | static inline int iommu_domain_set_attr(struct iommu_domain *domain, | |
606 | enum iommu_attr attr, void *data) | |
607 | { | |
608 | return -EINVAL; | |
609 | } | |
610 | ||
39ab9555 | 611 | static inline int iommu_device_register(struct iommu_device *iommu) |
c61959ec | 612 | { |
39ab9555 | 613 | return -ENODEV; |
c61959ec AW |
614 | } |
615 | ||
39ab9555 JR |
616 | static inline void iommu_device_set_ops(struct iommu_device *iommu, |
617 | const struct iommu_ops *ops) | |
c61959ec | 618 | { |
c61959ec AW |
619 | } |
620 | ||
c73e1ac8 JR |
621 | static inline void iommu_device_set_fwnode(struct iommu_device *iommu, |
622 | struct fwnode_handle *fwnode) | |
c61959ec | 623 | { |
c61959ec AW |
624 | } |
625 | ||
39ab9555 | 626 | static inline void iommu_device_unregister(struct iommu_device *iommu) |
c61959ec | 627 | { |
c61959ec AW |
628 | } |
629 | ||
39ab9555 JR |
630 | static inline int iommu_device_sysfs_add(struct iommu_device *iommu, |
631 | struct device *parent, | |
632 | const struct attribute_group **groups, | |
633 | const char *fmt, ...) | |
b0119e87 | 634 | { |
39ab9555 | 635 | return -ENODEV; |
b0119e87 JR |
636 | } |
637 | ||
39ab9555 | 638 | static inline void iommu_device_sysfs_remove(struct iommu_device *iommu) |
c61959ec AW |
639 | { |
640 | } | |
641 | ||
e09f8ea5 | 642 | static inline int iommu_device_link(struct device *dev, struct device *link) |
c61959ec AW |
643 | { |
644 | return -EINVAL; | |
645 | } | |
646 | ||
e09f8ea5 | 647 | static inline void iommu_device_unlink(struct device *dev, struct device *link) |
c61959ec AW |
648 | { |
649 | } | |
650 | ||
57f98d2f RM |
651 | static inline int iommu_fwspec_init(struct device *dev, |
652 | struct fwnode_handle *iommu_fwnode, | |
653 | const struct iommu_ops *ops) | |
654 | { | |
655 | return -ENODEV; | |
656 | } | |
657 | ||
658 | static inline void iommu_fwspec_free(struct device *dev) | |
659 | { | |
660 | } | |
661 | ||
662 | static inline int iommu_fwspec_add_ids(struct device *dev, u32 *ids, | |
663 | int num_ids) | |
664 | { | |
665 | return -ENODEV; | |
666 | } | |
667 | ||
e4f10ffe | 668 | static inline |
534766df | 669 | const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) |
e4f10ffe LP |
670 | { |
671 | return NULL; | |
672 | } | |
673 | ||
4a77a6cf JR |
674 | #endif /* CONFIG_IOMMU_API */ |
675 | ||
676 | #endif /* __LINUX_IOMMU_H */ |