]>
Commit | Line | Data |
---|---|---|
5b497af4 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
b94d5230 DW |
2 | /* |
3 | * libnvdimm - Non-volatile-memory Devices Subsystem | |
4 | * | |
5 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. | |
b94d5230 DW |
6 | */ |
7 | #ifndef __LIBNVDIMM_H__ | |
8 | #define __LIBNVDIMM_H__ | |
047fc8a1 | 9 | #include <linux/kernel.h> |
62232e45 DW |
10 | #include <linux/sizes.h> |
11 | #include <linux/types.h> | |
faec6f8a | 12 | #include <linux/uuid.h> |
aa9ad44a DJ |
13 | #include <linux/spinlock.h> |
14 | ||
15 | struct badrange_entry { | |
16 | u64 start; | |
17 | u64 length; | |
18 | struct list_head list; | |
19 | }; | |
20 | ||
21 | struct badrange { | |
22 | struct list_head list; | |
23 | spinlock_t lock; | |
24 | }; | |
e6dfb2de DW |
25 | |
26 | enum { | |
27 | /* when a dimm supports both PMEM and BLK access a label is required */ | |
8f078b38 | 28 | NDD_ALIASING = 0, |
58138820 | 29 | /* unarmed memory devices may not persist writes */ |
8f078b38 DW |
30 | NDD_UNARMED = 1, |
31 | /* locked memory devices should not be accessed */ | |
32 | NDD_LOCKED = 2, | |
7d988097 DJ |
33 | /* memory under security wipes should not be accessed */ |
34 | NDD_SECURITY_OVERWRITE = 3, | |
35 | /* tracking whether or not there is a pending device reference */ | |
36 | NDD_WORK_PENDING = 4, | |
d5d30d5a DW |
37 | /* ignore / filter NSLABEL_FLAG_LOCAL for this DIMM, i.e. no aliasing */ |
38 | NDD_NOBLK = 5, | |
62232e45 DW |
39 | |
40 | /* need to set a limit somewhere, but yes, this is likely overkill */ | |
41 | ND_IOCTL_MAX_BUFLEN = SZ_4M, | |
4577b066 | 42 | ND_CMD_MAX_ELEM = 5, |
40abf9be | 43 | ND_CMD_MAX_ENVELOPE = 256, |
1f7df6f8 | 44 | ND_MAX_MAPPINGS = 32, |
1b40e09a | 45 | |
004f1afb DW |
46 | /* region flag indicating to direct-map persistent memory by default */ |
47 | ND_REGION_PAGEMAP = 0, | |
06e8ccda DJ |
48 | /* |
49 | * Platform ensures entire CPU store data path is flushed to pmem on | |
50 | * system power loss. | |
51 | */ | |
52 | ND_REGION_PERSIST_CACHE = 1, | |
30e6d7bf DJ |
53 | /* |
54 | * Platform provides mechanisms to automatically flush outstanding | |
55 | * write data from memory controler to pmem on system power loss. | |
56 | * (ADR) | |
57 | */ | |
58 | ND_REGION_PERSIST_MEMCTRL = 2, | |
004f1afb | 59 | |
1b40e09a DW |
60 | /* mark newly adjusted resources as requiring a label update */ |
61 | DPA_RESOURCE_ADJUSTED = 1 << 0, | |
e6dfb2de DW |
62 | }; |
63 | ||
45def22c | 64 | extern struct attribute_group nvdimm_bus_attribute_group; |
62232e45 | 65 | extern struct attribute_group nvdimm_attribute_group; |
4d88a97a | 66 | extern struct attribute_group nd_device_attribute_group; |
74ae66c3 | 67 | extern struct attribute_group nd_numa_attribute_group; |
1f7df6f8 DW |
68 | extern struct attribute_group nd_region_attribute_group; |
69 | extern struct attribute_group nd_mapping_attribute_group; | |
45def22c | 70 | |
b94d5230 DW |
71 | struct nvdimm; |
72 | struct nvdimm_bus_descriptor; | |
73 | typedef int (*ndctl_fn)(struct nvdimm_bus_descriptor *nd_desc, | |
74 | struct nvdimm *nvdimm, unsigned int cmd, void *buf, | |
aef25338 | 75 | unsigned int buf_len, int *cmd_rc); |
b94d5230 | 76 | |
1ff19f48 | 77 | struct device_node; |
b94d5230 | 78 | struct nvdimm_bus_descriptor { |
45def22c | 79 | const struct attribute_group **attr_groups; |
7db5bb33 | 80 | unsigned long bus_dsm_mask; |
e3654eca | 81 | unsigned long cmd_mask; |
bc9775d8 | 82 | struct module *module; |
b94d5230 | 83 | char *provider_name; |
1ff19f48 | 84 | struct device_node *of_node; |
b94d5230 | 85 | ndctl_fn ndctl; |
7ae0fa43 | 86 | int (*flush_probe)(struct nvdimm_bus_descriptor *nd_desc); |
87bf572e | 87 | int (*clear_to_send)(struct nvdimm_bus_descriptor *nd_desc, |
b3ed2ce0 | 88 | struct nvdimm *nvdimm, unsigned int cmd, void *data); |
b94d5230 DW |
89 | }; |
90 | ||
62232e45 DW |
91 | struct nd_cmd_desc { |
92 | int in_num; | |
93 | int out_num; | |
94 | u32 in_sizes[ND_CMD_MAX_ELEM]; | |
95 | int out_sizes[ND_CMD_MAX_ELEM]; | |
96 | }; | |
97 | ||
eaf96153 | 98 | struct nd_interleave_set { |
c12c48ce DW |
99 | /* v1.1 definition of the interleave-set-cookie algorithm */ |
100 | u64 cookie1; | |
101 | /* v1.2 definition of the interleave-set-cookie algorithm */ | |
102 | u64 cookie2; | |
86ef58a4 DW |
103 | /* compatibility with initial buggy Linux implementation */ |
104 | u64 altcookie; | |
faec6f8a DW |
105 | |
106 | guid_t type_guid; | |
eaf96153 DW |
107 | }; |
108 | ||
44c462eb DW |
109 | struct nd_mapping_desc { |
110 | struct nvdimm *nvdimm; | |
111 | u64 start; | |
112 | u64 size; | |
401c0a19 | 113 | int position; |
44c462eb DW |
114 | }; |
115 | ||
1f7df6f8 DW |
116 | struct nd_region_desc { |
117 | struct resource *res; | |
44c462eb | 118 | struct nd_mapping_desc *mapping; |
1f7df6f8 DW |
119 | u16 num_mappings; |
120 | const struct attribute_group **attr_groups; | |
eaf96153 | 121 | struct nd_interleave_set *nd_set; |
1f7df6f8 | 122 | void *provider_data; |
5212e11f | 123 | int num_lanes; |
41d7a6d6 | 124 | int numa_node; |
8fc5c735 | 125 | int target_node; |
004f1afb | 126 | unsigned long flags; |
1ff19f48 | 127 | struct device_node *of_node; |
1f7df6f8 DW |
128 | }; |
129 | ||
29b9aa0a DW |
130 | struct device; |
131 | void *devm_nvdimm_memremap(struct device *dev, resource_size_t offset, | |
132 | size_t size, unsigned long flags); | |
133 | static inline void __iomem *devm_nvdimm_ioremap(struct device *dev, | |
134 | resource_size_t offset, size_t size) | |
135 | { | |
136 | return (void __iomem *) devm_nvdimm_memremap(dev, offset, size, 0); | |
137 | } | |
138 | ||
62232e45 | 139 | struct nvdimm_bus; |
3d88002e | 140 | struct module; |
047fc8a1 RZ |
141 | struct device; |
142 | struct nd_blk_region; | |
143 | struct nd_blk_region_desc { | |
144 | int (*enable)(struct nvdimm_bus *nvdimm_bus, struct device *dev); | |
047fc8a1 RZ |
145 | int (*do_io)(struct nd_blk_region *ndbr, resource_size_t dpa, |
146 | void *iobuf, u64 len, int rw); | |
147 | struct nd_region_desc ndr_desc; | |
148 | }; | |
149 | ||
150 | static inline struct nd_blk_region_desc *to_blk_region_desc( | |
151 | struct nd_region_desc *ndr_desc) | |
152 | { | |
153 | return container_of(ndr_desc, struct nd_blk_region_desc, ndr_desc); | |
154 | ||
155 | } | |
156 | ||
f2989396 | 157 | enum nvdimm_security_state { |
1cb95e07 | 158 | NVDIMM_SECURITY_ERROR = -1, |
f2989396 DJ |
159 | NVDIMM_SECURITY_DISABLED, |
160 | NVDIMM_SECURITY_UNLOCKED, | |
161 | NVDIMM_SECURITY_LOCKED, | |
162 | NVDIMM_SECURITY_FROZEN, | |
163 | NVDIMM_SECURITY_OVERWRITE, | |
164 | }; | |
165 | ||
4c6926a2 DJ |
166 | #define NVDIMM_PASSPHRASE_LEN 32 |
167 | #define NVDIMM_KEY_DESC_LEN 22 | |
168 | ||
169 | struct nvdimm_key_data { | |
170 | u8 data[NVDIMM_PASSPHRASE_LEN]; | |
171 | }; | |
172 | ||
89fa9d8e DJ |
173 | enum nvdimm_passphrase_type { |
174 | NVDIMM_USER, | |
175 | NVDIMM_MASTER, | |
176 | }; | |
177 | ||
f2989396 | 178 | struct nvdimm_security_ops { |
89fa9d8e DJ |
179 | enum nvdimm_security_state (*state)(struct nvdimm *nvdimm, |
180 | enum nvdimm_passphrase_type pass_type); | |
37833fb7 | 181 | int (*freeze)(struct nvdimm *nvdimm); |
4c6926a2 DJ |
182 | int (*change_key)(struct nvdimm *nvdimm, |
183 | const struct nvdimm_key_data *old_data, | |
89fa9d8e DJ |
184 | const struct nvdimm_key_data *new_data, |
185 | enum nvdimm_passphrase_type pass_type); | |
4c6926a2 DJ |
186 | int (*unlock)(struct nvdimm *nvdimm, |
187 | const struct nvdimm_key_data *key_data); | |
03b65b22 DJ |
188 | int (*disable)(struct nvdimm *nvdimm, |
189 | const struct nvdimm_key_data *key_data); | |
64e77c8c | 190 | int (*erase)(struct nvdimm *nvdimm, |
89fa9d8e DJ |
191 | const struct nvdimm_key_data *key_data, |
192 | enum nvdimm_passphrase_type pass_type); | |
7d988097 DJ |
193 | int (*overwrite)(struct nvdimm *nvdimm, |
194 | const struct nvdimm_key_data *key_data); | |
195 | int (*query_overwrite)(struct nvdimm *nvdimm); | |
f2989396 DJ |
196 | }; |
197 | ||
aa9ad44a DJ |
198 | void badrange_init(struct badrange *badrange); |
199 | int badrange_add(struct badrange *badrange, u64 addr, u64 length); | |
200 | void badrange_forget(struct badrange *badrange, phys_addr_t start, | |
201 | unsigned int len); | |
202 | int nvdimm_bus_add_badrange(struct nvdimm_bus *nvdimm_bus, u64 addr, | |
203 | u64 length); | |
bc9775d8 DW |
204 | struct nvdimm_bus *nvdimm_bus_register(struct device *parent, |
205 | struct nvdimm_bus_descriptor *nfit_desc); | |
b94d5230 | 206 | void nvdimm_bus_unregister(struct nvdimm_bus *nvdimm_bus); |
45def22c | 207 | struct nvdimm_bus *to_nvdimm_bus(struct device *dev); |
f2989396 | 208 | struct nvdimm_bus *nvdimm_to_bus(struct nvdimm *nvdimm); |
e6dfb2de | 209 | struct nvdimm *to_nvdimm(struct device *dev); |
1f7df6f8 | 210 | struct nd_region *to_nd_region(struct device *dev); |
243f29fe | 211 | struct device *nd_region_dev(struct nd_region *nd_region); |
047fc8a1 | 212 | struct nd_blk_region *to_nd_blk_region(struct device *dev); |
45def22c | 213 | struct nvdimm_bus_descriptor *to_nd_desc(struct nvdimm_bus *nvdimm_bus); |
37b137ff | 214 | struct device *to_nvdimm_bus_dev(struct nvdimm_bus *nvdimm_bus); |
e6dfb2de | 215 | const char *nvdimm_name(struct nvdimm *nvdimm); |
ba9c8dd3 | 216 | struct kobject *nvdimm_kobj(struct nvdimm *nvdimm); |
e3654eca | 217 | unsigned long nvdimm_cmd_mask(struct nvdimm *nvdimm); |
e6dfb2de | 218 | void *nvdimm_provider_data(struct nvdimm *nvdimm); |
d6548ae4 DJ |
219 | struct nvdimm *__nvdimm_create(struct nvdimm_bus *nvdimm_bus, |
220 | void *provider_data, const struct attribute_group **groups, | |
221 | unsigned long flags, unsigned long cmd_mask, int num_flush, | |
f2989396 DJ |
222 | struct resource *flush_wpq, const char *dimm_id, |
223 | const struct nvdimm_security_ops *sec_ops); | |
d6548ae4 DJ |
224 | static inline struct nvdimm *nvdimm_create(struct nvdimm_bus *nvdimm_bus, |
225 | void *provider_data, const struct attribute_group **groups, | |
226 | unsigned long flags, unsigned long cmd_mask, int num_flush, | |
227 | struct resource *flush_wpq) | |
228 | { | |
229 | return __nvdimm_create(nvdimm_bus, provider_data, groups, flags, | |
f2989396 | 230 | cmd_mask, num_flush, flush_wpq, NULL, NULL); |
d6548ae4 DJ |
231 | } |
232 | ||
62232e45 DW |
233 | const struct nd_cmd_desc *nd_cmd_dimm_desc(int cmd); |
234 | const struct nd_cmd_desc *nd_cmd_bus_desc(int cmd); | |
235 | u32 nd_cmd_in_size(struct nvdimm *nvdimm, int cmd, | |
236 | const struct nd_cmd_desc *desc, int idx, void *buf); | |
237 | u32 nd_cmd_out_size(struct nvdimm *nvdimm, int cmd, | |
238 | const struct nd_cmd_desc *desc, int idx, const u32 *in_field, | |
efda1b5d | 239 | const u32 *out_field, unsigned long remainder); |
4d88a97a | 240 | int nvdimm_bus_check_dimm_count(struct nvdimm_bus *nvdimm_bus, int dimm_count); |
1f7df6f8 DW |
241 | struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus, |
242 | struct nd_region_desc *ndr_desc); | |
243 | struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus, | |
244 | struct nd_region_desc *ndr_desc); | |
245 | struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus, | |
246 | struct nd_region_desc *ndr_desc); | |
047fc8a1 RZ |
247 | void *nd_region_provider_data(struct nd_region *nd_region); |
248 | void *nd_blk_region_provider_data(struct nd_blk_region *ndbr); | |
249 | void nd_blk_region_set_provider_data(struct nd_blk_region *ndbr, void *data); | |
250 | struct nvdimm *nd_blk_region_to_dimm(struct nd_blk_region *ndbr); | |
ca6a4657 | 251 | unsigned long nd_blk_memremap_flags(struct nd_blk_region *ndbr); |
047fc8a1 RZ |
252 | unsigned int nd_region_acquire_lane(struct nd_region *nd_region); |
253 | void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane); | |
eaf96153 | 254 | u64 nd_fletcher64(void *addr, size_t len, bool le); |
f284a4f2 DW |
255 | void nvdimm_flush(struct nd_region *nd_region); |
256 | int nvdimm_has_flush(struct nd_region *nd_region); | |
0b277961 | 257 | int nvdimm_has_cache(struct nd_region *nd_region); |
7d988097 | 258 | int nvdimm_in_overwrite(struct nvdimm *nvdimm); |
5deb67f7 | 259 | |
f2989396 DJ |
260 | static inline int nvdimm_ctl(struct nvdimm *nvdimm, unsigned int cmd, void *buf, |
261 | unsigned int buf_len, int *cmd_rc) | |
262 | { | |
263 | struct nvdimm_bus *nvdimm_bus = nvdimm_to_bus(nvdimm); | |
264 | struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus); | |
265 | ||
266 | return nd_desc->ndctl(nd_desc, nvdimm, cmd, buf, buf_len, cmd_rc); | |
267 | } | |
268 | ||
5deb67f7 RM |
269 | #ifdef CONFIG_ARCH_HAS_PMEM_API |
270 | #define ARCH_MEMREMAP_PMEM MEMREMAP_WB | |
271 | void arch_wb_cache_pmem(void *addr, size_t size); | |
272 | void arch_invalidate_pmem(void *addr, size_t size); | |
273 | #else | |
274 | #define ARCH_MEMREMAP_PMEM MEMREMAP_WT | |
275 | static inline void arch_wb_cache_pmem(void *addr, size_t size) | |
276 | { | |
277 | } | |
278 | static inline void arch_invalidate_pmem(void *addr, size_t size) | |
279 | { | |
280 | } | |
281 | #endif | |
282 | ||
b94d5230 | 283 | #endif /* __LIBNVDIMM_H__ */ |