[people/ms/linux.git] / include / linux / mlx4 / device.h

/*
 * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *	- Redistributions of source code must retain the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer.
 *
 *	- Redistributions in binary form must reproduce the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer in the documentation and/or other materials
 *	  provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_DEVICE_H
#define MLX4_DEVICE_H

#include <linux/pci.h>
#include <linux/completion.h>
#include <linux/radix-tree.h>

#include <asm/atomic.h>

enum {
	MLX4_FLAG_MSI_X		= 1 << 0,
	MLX4_FLAG_OLD_PORT_CMDS	= 1 << 1,
};

enum {
	MLX4_MAX_PORTS		= 2
};

enum {
	MLX4_BOARD_ID_LEN = 64
};

enum {
	MLX4_DEV_CAP_FLAG_RC		= 1 <<  0,
	MLX4_DEV_CAP_FLAG_UC		= 1 <<  1,
	MLX4_DEV_CAP_FLAG_UD		= 1 <<  2,
	MLX4_DEV_CAP_FLAG_SRQ		= 1 <<  6,
	MLX4_DEV_CAP_FLAG_IPOIB_CSUM	= 1 <<  7,
	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR	= 1 <<  8,
	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR	= 1 <<  9,
	MLX4_DEV_CAP_FLAG_MEM_WINDOW	= 1 << 16,
	MLX4_DEV_CAP_FLAG_APM		= 1 << 17,
	MLX4_DEV_CAP_FLAG_ATOMIC	= 1 << 18,
	MLX4_DEV_CAP_FLAG_RAW_MCAST	= 1 << 19,
	MLX4_DEV_CAP_FLAG_UD_AV_PORT	= 1 << 20,
	MLX4_DEV_CAP_FLAG_UD_MCAST	= 1 << 21
};

enum mlx4_event {
	MLX4_EVENT_TYPE_COMP		   = 0x00,
	MLX4_EVENT_TYPE_PATH_MIG	   = 0x01,
	MLX4_EVENT_TYPE_COMM_EST	   = 0x02,
	MLX4_EVENT_TYPE_SQ_DRAINED	   = 0x03,
	MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE	   = 0x13,
	MLX4_EVENT_TYPE_SRQ_LIMIT	   = 0x14,
	MLX4_EVENT_TYPE_CQ_ERROR	   = 0x04,
	MLX4_EVENT_TYPE_WQ_CATAS_ERROR	   = 0x05,
	MLX4_EVENT_TYPE_EEC_CATAS_ERROR	   = 0x06,
	MLX4_EVENT_TYPE_PATH_MIG_FAILED	   = 0x07,
	MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
	MLX4_EVENT_TYPE_WQ_ACCESS_ERROR	   = 0x11,
	MLX4_EVENT_TYPE_SRQ_CATAS_ERROR	   = 0x12,
	MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
	MLX4_EVENT_TYPE_PORT_CHANGE	   = 0x09,
	MLX4_EVENT_TYPE_EQ_OVERFLOW	   = 0x0f,
	MLX4_EVENT_TYPE_ECC_DETECT	   = 0x0e,
	MLX4_EVENT_TYPE_CMD		   = 0x0a
};

enum {
	MLX4_PORT_CHANGE_SUBTYPE_DOWN	= 1,
	MLX4_PORT_CHANGE_SUBTYPE_ACTIVE	= 4
};

enum {
	MLX4_PERM_LOCAL_READ	= 1 << 10,
	MLX4_PERM_LOCAL_WRITE	= 1 << 11,
	MLX4_PERM_REMOTE_READ	= 1 << 12,
	MLX4_PERM_REMOTE_WRITE	= 1 << 13,
	MLX4_PERM_ATOMIC	= 1 << 14
};

enum {
	MLX4_OPCODE_NOP			= 0x00,
	MLX4_OPCODE_SEND_INVAL		= 0x01,
	MLX4_OPCODE_RDMA_WRITE		= 0x08,
	MLX4_OPCODE_RDMA_WRITE_IMM	= 0x09,
	MLX4_OPCODE_SEND		= 0x0a,
	MLX4_OPCODE_SEND_IMM		= 0x0b,
	MLX4_OPCODE_LSO			= 0x0e,
	MLX4_OPCODE_RDMA_READ		= 0x10,
	MLX4_OPCODE_ATOMIC_CS		= 0x11,
	MLX4_OPCODE_ATOMIC_FA		= 0x12,
	MLX4_OPCODE_ATOMIC_MASK_CS	= 0x14,
	MLX4_OPCODE_ATOMIC_MASK_FA	= 0x15,
	MLX4_OPCODE_BIND_MW		= 0x18,
	MLX4_OPCODE_FMR			= 0x19,
	MLX4_OPCODE_LOCAL_INVAL		= 0x1b,
	MLX4_OPCODE_CONFIG_CMD		= 0x1f,

	MLX4_RECV_OPCODE_RDMA_WRITE_IMM	= 0x00,
	MLX4_RECV_OPCODE_SEND		= 0x01,
	MLX4_RECV_OPCODE_SEND_IMM	= 0x02,
	MLX4_RECV_OPCODE_SEND_INVAL	= 0x03,

	MLX4_CQE_OPCODE_ERROR		= 0x1e,
	MLX4_CQE_OPCODE_RESIZE		= 0x16,
};

enum {
	MLX4_STAT_RATE_OFFSET	= 5
};

struct mlx4_caps {
	u64			fw_ver;
	int			num_ports;
	int			vl_cap[MLX4_MAX_PORTS + 1];
	int			mtu_cap[MLX4_MAX_PORTS + 1];
	int			gid_table_len[MLX4_MAX_PORTS + 1];
	int			pkey_table_len[MLX4_MAX_PORTS + 1];
	int			local_ca_ack_delay;
	int			num_uars;
	int			bf_reg_size;
	int			bf_regs_per_page;
	int			max_sq_sg;
	int			max_rq_sg;
	int			num_qps;
	int			max_wqes;
	int			max_sq_desc_sz;
	int			max_rq_desc_sz;
	int			max_qp_init_rdma;
	int			max_qp_dest_rdma;
	int			reserved_qps;
	int			sqp_start;
	int			num_srqs;
	int			max_srq_wqes;
	int			max_srq_sge;
	int			reserved_srqs;
	int			num_cqs;
	int			max_cqes;
	int			reserved_cqs;
	int			num_eqs;
	int			reserved_eqs;
	int			num_mpts;
	int			num_mtt_segs;
	int			fmr_reserved_mtts;
	int			reserved_mtts;
	int			reserved_mrws;
	int			reserved_uars;
	int			num_mgms;
	int			num_amgms;
	int			reserved_mcgs;
	int			num_qp_per_mgm;
	int			num_pds;
	int			reserved_pds;
	int			mtt_entry_sz;
	u32			max_msg_sz;
	u32			page_size_cap;
	u32			flags;
	u16			stat_rate_support;
	u8			port_width_cap[MLX4_MAX_PORTS + 1];
};

struct mlx4_buf_list {
	void		       *buf;
	dma_addr_t		map;
};

struct mlx4_buf {
	union {
		struct mlx4_buf_list	direct;
		struct mlx4_buf_list   *page_list;
	} u;
	int			nbufs;
	int			npages;
	int			page_shift;
};

struct mlx4_mtt {
	u32			first_seg;
	int			order;
	int			page_shift;
};

struct mlx4_mr {
	struct mlx4_mtt		mtt;
	u64			iova;
	u64			size;
	u32			key;
	u32			pd;
	u32			access;
	int			enabled;
};

struct mlx4_uar {
	unsigned long		pfn;
	int			index;
};

struct mlx4_cq {
	void (*comp)		(struct mlx4_cq *);
	void (*event)		(struct mlx4_cq *, enum mlx4_event);

	struct mlx4_uar	       *uar;

	u32			cons_index;

	__be32		       *set_ci_db;
	__be32		       *arm_db;
	int			arm_sn;

	int			cqn;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_qp {
	void (*event)		(struct mlx4_qp *, enum mlx4_event);

	int			qpn;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_srq {
	void (*event)		(struct mlx4_srq *, enum mlx4_event);

	int			srqn;
	int			max;
	int			max_gs;
	int			wqe_shift;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_av {
	__be32			port_pd;
	u8			reserved1;
	u8			g_slid;
	__be16			dlid;
	u8			reserved2;
	u8			gid_index;
	u8			stat_rate;
	u8			hop_limit;
	__be32			sl_tclass_flowlabel;
	u8			dgid[16];
};

struct mlx4_dev {
	struct pci_dev	       *pdev;
	unsigned long		flags;
	struct mlx4_caps	caps;
	struct radix_tree_root	qp_table_tree;
	u32			rev_id;
	char			board_id[MLX4_BOARD_ID_LEN];
};

struct mlx4_init_port_param {
	int			set_guid0;
	int			set_node_guid;
	int			set_si_guid;
	u16			mtu;
	int			port_width_cap;
	u16			vl_cap;
	u16			max_gid;
	u16			max_pkey;
	u64			guid0;
	u64			node_guid;
	u64			si_guid;
};

int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
		   struct mlx4_buf *buf);
void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);

int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);

int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);

int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
		  struct mlx4_mtt *mtt);
void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);

int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
		  int npages, int page_shift, struct mlx4_mr *mr);
void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		   int start_index, int npages, u64 *page_list);
int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		       struct mlx4_buf *buf);

int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
		  struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq);
void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);

int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp);
void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);

int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
		   u64 db_rec, struct mlx4_srq *srq);
void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);

int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);

int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);

#endif /* MLX4_DEVICE_H */
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef MLX4_DEVICE_H
	34	#define MLX4_DEVICE_H
	35
	36	#include <linux/pci.h>
	37	#include <linux/completion.h>
	38	#include <linux/radix-tree.h>
	39
	40	#include <asm/atomic.h>
	41
	42	enum {
	43	MLX4_FLAG_MSI_X = 1 << 0,
5ae2a7a8	44	MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
225c7b1f RD	45	};
	46
	47	enum {
	48	MLX4_MAX_PORTS = 2
	49	};
	50
cd9281d8 JM	51	enum {
	52	MLX4_BOARD_ID_LEN = 64
	53	};
	54
225c7b1f RD	55	enum {
	56	MLX4_DEV_CAP_FLAG_RC = 1 << 0,
	57	MLX4_DEV_CAP_FLAG_UC = 1 << 1,
	58	MLX4_DEV_CAP_FLAG_UD = 1 << 2,
	59	MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
	60	MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
	61	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
	62	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
	63	MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
	64	MLX4_DEV_CAP_FLAG_APM = 1 << 17,
	65	MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
	66	MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
	67	MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
	68	MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
	69	};
	70
	71	enum mlx4_event {
	72	MLX4_EVENT_TYPE_COMP = 0x00,
	73	MLX4_EVENT_TYPE_PATH_MIG = 0x01,
	74	MLX4_EVENT_TYPE_COMM_EST = 0x02,
	75	MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
	76	MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
	77	MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
	78	MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
	79	MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
	80	MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
	81	MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
	82	MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
	83	MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
	84	MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
	85	MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
	86	MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
	87	MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
	88	MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
	89	MLX4_EVENT_TYPE_CMD = 0x0a
	90	};
	91
	92	enum {
	93	MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
	94	MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
	95	};
	96
	97	enum {
	98	MLX4_PERM_LOCAL_READ = 1 << 10,
	99	MLX4_PERM_LOCAL_WRITE = 1 << 11,
	100	MLX4_PERM_REMOTE_READ = 1 << 12,
	101	MLX4_PERM_REMOTE_WRITE = 1 << 13,
	102	MLX4_PERM_ATOMIC = 1 << 14
	103	};
	104
	105	enum {
	106	MLX4_OPCODE_NOP = 0x00,
	107	MLX4_OPCODE_SEND_INVAL = 0x01,
	108	MLX4_OPCODE_RDMA_WRITE = 0x08,
	109	MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
	110	MLX4_OPCODE_SEND = 0x0a,
	111	MLX4_OPCODE_SEND_IMM = 0x0b,
	112	MLX4_OPCODE_LSO = 0x0e,
	113	MLX4_OPCODE_RDMA_READ = 0x10,
	114	MLX4_OPCODE_ATOMIC_CS = 0x11,
	115	MLX4_OPCODE_ATOMIC_FA = 0x12,
	116	MLX4_OPCODE_ATOMIC_MASK_CS = 0x14,
	117	MLX4_OPCODE_ATOMIC_MASK_FA = 0x15,
	118	MLX4_OPCODE_BIND_MW = 0x18,
119	MLX4_OPCODE_FMR = 0x19,
120	MLX4_OPCODE_LOCAL_INVAL = 0x1b,
121	MLX4_OPCODE_CONFIG_CMD = 0x1f,
122
123	MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
124	MLX4_RECV_OPCODE_SEND = 0x01,
125	MLX4_RECV_OPCODE_SEND_IMM = 0x02,
126	MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
127
128	MLX4_CQE_OPCODE_ERROR = 0x1e,
129	MLX4_CQE_OPCODE_RESIZE = 0x16,
130	};
131
132	enum {
133	MLX4_STAT_RATE_OFFSET = 5
134	};
135
136	struct mlx4_caps {
137	u64 fw_ver;
138	int num_ports;
5ae2a7a8 RD	139	int vl_cap[MLX4_MAX_PORTS + 1];
	140	int mtu_cap[MLX4_MAX_PORTS + 1];
	141	int gid_table_len[MLX4_MAX_PORTS + 1];
	142	int pkey_table_len[MLX4_MAX_PORTS + 1];
225c7b1f RD	143	int local_ca_ack_delay;
	144	int num_uars;
	145	int bf_reg_size;
	146	int bf_regs_per_page;
	147	int max_sq_sg;
	148	int max_rq_sg;
	149	int num_qps;
	150	int max_wqes;
	151	int max_sq_desc_sz;
	152	int max_rq_desc_sz;
	153	int max_qp_init_rdma;
	154	int max_qp_dest_rdma;
	155	int reserved_qps;
	156	int sqp_start;
	157	int num_srqs;
	158	int max_srq_wqes;
	159	int max_srq_sge;
	160	int reserved_srqs;
	161	int num_cqs;
	162	int max_cqes;
	163	int reserved_cqs;
	164	int num_eqs;
	165	int reserved_eqs;
	166	int num_mpts;
	167	int num_mtt_segs;
	168	int fmr_reserved_mtts;
	169	int reserved_mtts;
	170	int reserved_mrws;
	171	int reserved_uars;
	172	int num_mgms;
	173	int num_amgms;
	174	int reserved_mcgs;
	175	int num_qp_per_mgm;
	176	int num_pds;
	177	int reserved_pds;
	178	int mtt_entry_sz;
149983af	179	u32 max_msg_sz;
225c7b1f RD	180	u32 page_size_cap;
	181	u32 flags;
	182	u16 stat_rate_support;
5ae2a7a8	183	u8 port_width_cap[MLX4_MAX_PORTS + 1];
225c7b1f RD	184	};
	185
	186	struct mlx4_buf_list {
	187	void *buf;
	188	dma_addr_t map;
	189	};
	190
	191	struct mlx4_buf {
	192	union {
	193	struct mlx4_buf_list direct;
	194	struct mlx4_buf_list *page_list;
	195	} u;
	196	int nbufs;
	197	int npages;
	198	int page_shift;
	199	};
	200
	201	struct mlx4_mtt {
	202	u32 first_seg;
	203	int order;
	204	int page_shift;
	205	};
	206
	207	struct mlx4_mr {
	208	struct mlx4_mtt mtt;
	209	u64 iova;
	210	u64 size;
	211	u32 key;
	212	u32 pd;
	213	u32 access;
	214	int enabled;
	215	};
	216
	217	struct mlx4_uar {
	218	unsigned long pfn;
	219	int index;
	220	};
	221
	222	struct mlx4_cq {
	223	void (comp) (struct mlx4_cq );
	224	void (event) (struct mlx4_cq , enum mlx4_event);
	225
	226	struct mlx4_uar *uar;
	227
	228	u32 cons_index;
	229
	230	__be32 *set_ci_db;
	231	__be32 *arm_db;
	232	int arm_sn;
	233
	234	int cqn;
	235
	236	atomic_t refcount;
	237	struct completion free;
	238	};
	239
	240	struct mlx4_qp {
	241	void (event) (struct mlx4_qp , enum mlx4_event);
	242
	243	int qpn;
	244
	245	atomic_t refcount;
	246	struct completion free;
	247	};
248
249	struct mlx4_srq {
250	void (event) (struct mlx4_srq , enum mlx4_event);
251
252	int srqn;
253	int max;
254	int max_gs;
255	int wqe_shift;
256
257	atomic_t refcount;
258	struct completion free;
259	};
260
261	struct mlx4_av {
262	__be32 port_pd;
263	u8 reserved1;
264	u8 g_slid;
265	__be16 dlid;
266	u8 reserved2;
267	u8 gid_index;
268	u8 stat_rate;
269	u8 hop_limit;
270	__be32 sl_tclass_flowlabel;
271	u8 dgid[16];
272	};
273
274	struct mlx4_dev {
275	struct pci_dev *pdev;
276	unsigned long flags;
277	struct mlx4_caps caps;
278	struct radix_tree_root qp_table_tree;
cd9281d8 JM	279	u32 rev_id;
cd9281d8 JM	280	char board_id[MLX4_BOARD_ID_LEN];
225c7b1f RD	281	};
	282
	283	struct mlx4_init_port_param {
	284	int set_guid0;
	285	int set_node_guid;
	286	int set_si_guid;
	287	u16 mtu;
	288	int port_width_cap;
	289	u16 vl_cap;
	290	u16 max_gid;
	291	u16 max_pkey;
	292	u64 guid0;
	293	u64 node_guid;
	294	u64 si_guid;
	295	};
	296
	297	int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
	298	struct mlx4_buf *buf);
	299	void mlx4_buf_free(struct mlx4_dev dev, int size, struct mlx4_buf buf);
	300
	301	int mlx4_pd_alloc(struct mlx4_dev dev, u32 pdn);
	302	void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
	303
	304	int mlx4_uar_alloc(struct mlx4_dev dev, struct mlx4_uar uar);
	305	void mlx4_uar_free(struct mlx4_dev dev, struct mlx4_uar uar);
	306
	307	int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
	308	struct mlx4_mtt *mtt);
	309	void mlx4_mtt_cleanup(struct mlx4_dev dev, struct mlx4_mtt mtt);
	310	u64 mlx4_mtt_addr(struct mlx4_dev dev, struct mlx4_mtt mtt);
	311
	312	int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
	313	int npages, int page_shift, struct mlx4_mr *mr);
	314	void mlx4_mr_free(struct mlx4_dev dev, struct mlx4_mr mr);
	315	int mlx4_mr_enable(struct mlx4_dev dev, struct mlx4_mr mr);
	316	int mlx4_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	317	int start_index, int npages, u64 *page_list);
	318	int mlx4_buf_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	319	struct mlx4_buf *buf);
	320
	321	int mlx4_cq_alloc(struct mlx4_dev dev, int nent, struct mlx4_mtt mtt,
	322	struct mlx4_uar uar, u64 db_rec, struct mlx4_cq cq);
	323	void mlx4_cq_free(struct mlx4_dev dev, struct mlx4_cq cq);
	324
	325	int mlx4_qp_alloc(struct mlx4_dev dev, int sqpn, struct mlx4_qp qp);
	326	void mlx4_qp_free(struct mlx4_dev dev, struct mlx4_qp qp);
	327
	328	int mlx4_srq_alloc(struct mlx4_dev dev, u32 pdn, struct mlx4_mtt mtt,
	329	u64 db_rec, struct mlx4_srq *srq);
	330	void mlx4_srq_free(struct mlx4_dev dev, struct mlx4_srq srq);
	331	int mlx4_srq_arm(struct mlx4_dev dev, struct mlx4_srq srq, int limit_watermark);
65541cb7	332	int mlx4_srq_query(struct mlx4_dev dev, struct mlx4_srq srq, int *limit_watermark);
225c7b1f	333
5ae2a7a8	334	int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
225c7b1f RD	335	int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
	336
	337	int mlx4_multicast_attach(struct mlx4_dev dev, struct mlx4_qp qp, u8 gid[16]);
	338	int mlx4_multicast_detach(struct mlx4_dev dev, struct mlx4_qp qp, u8 gid[16]);
	339
	340	#endif /* MLX4_DEVICE_H */