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PCI: rename pci_host_bridge() to find_pci_root_bridge()
[thirdparty/linux.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
f46753c5 20#include <linux/pci_regs.h> /* The pci register defines */
1da177e4 21
1da177e4
LT		 22/*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
05cca6e5 30#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
1da177e4
LT		 31#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32#define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34/* Ioctls for /proc/bus/pci/X/Y nodes. */
35#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41#ifdef __KERNEL__
42
778382e0
DW		 43#include <linux/mod_devicetable.h>
44
1da177e4 45#include <linux/types.h>
98db6f19 46#include <linux/init.h>
1da177e4
LT		 47#include <linux/ioport.h>
48#include <linux/list.h>
4a7fb636 49#include <linux/compiler.h>
1da177e4 50#include <linux/errno.h>
f46753c5 51#include <linux/kobject.h>
60063497 52#include <linux/atomic.h>
1da177e4 53#include <linux/device.h>
1388cc96 54#include <linux/io.h>
74bb1bcc 55#include <linux/irqreturn.h>
1da177e4 56
7e7a43c3
AB		 57/* Include the ID list */
58#include <linux/pci_ids.h>
59
f46753c5
AC		 60/* pci_slot represents a physical slot */
61struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67};
68
0ad772ec
AC		 69static inline const char *pci_slot_name(const struct pci_slot *slot)
70{
71 return kobject_name(&slot->kobj);
72}
73
1da177e4
LT		 74/* File state for mmap()s on /proc/bus/pci/X/Y */
75enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78};
79
80/* This defines the direction arg to the DMA mapping routines. */
81#define PCI_DMA_BIDIRECTIONAL 0
82#define PCI_DMA_TODEVICE 1
83#define PCI_DMA_FROMDEVICE 2
84#define PCI_DMA_NONE 3
85
fde09c6d
YZ		 86/*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
d1b054da
YZ		 97 /* device specific resources */
98#ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101#endif
102
fde09c6d
YZ		 103 /* resources assigned to buses behind the bridge */
104#define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
cda57bf9 114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 115};
1da177e4
LT		 116
117typedef int __bitwise pci_power_t;
118
4352dfd5
GKH		 119#define PCI_D0 ((pci_power_t __force) 0)
120#define PCI_D1 ((pci_power_t __force) 1)
121#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 122#define PCI_D3hot ((pci_power_t __force) 3)
123#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 124#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 125#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 126
00240c38
AS		 127/* Remember to update this when the list above changes! */
128extern const char *pci_power_names[];
129
130static inline const char *pci_power_name(pci_power_t state)
131{
132 return pci_power_names[1 + (int) state];
133}
134
aa8c6c93
RW		 135#define PCI_PM_D2_DELAY 200
136#define PCI_PM_D3_WAIT 10
137#define PCI_PM_BUS_WAIT 50
138
392a1ce7
LV		 139/** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143typedef unsigned int __bitwise pci_channel_state_t;
144
145enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154};
155
f7bdd12d
BK		 156typedef unsigned int __bitwise pcie_reset_state_t;
157
158enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167};
168
ba698ad4
DM		 169typedef unsigned short __bitwise pci_dev_flags_t;
170enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
979b1791
AC		 175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
6777829c
GR		 177 /* Provide indication device is assigned by a Virtual Machine Manager */
178 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
ba698ad4
DM		 179};
180
e1d3a908
SA		 181enum pci_irq_reroute_variant {
182 INTEL_IRQ_REROUTE_VARIANT = 1,
183 MAX_IRQ_REROUTE_VARIANTS = 3
184};
185
6e325a62
MT		 186typedef unsigned short __bitwise pci_bus_flags_t;
187enum pci_bus_flags {
d556ad4b
PO		 188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
6e325a62
MT		 190};
191
536c8cb4
MW		 192/* Based on the PCI Hotplug Spec, but some values are made up by us */
193enum pci_bus_speed {
194 PCI_SPEED_33MHz = 0x00,
195 PCI_SPEED_66MHz = 0x01,
196 PCI_SPEED_66MHz_PCIX = 0x02,
197 PCI_SPEED_100MHz_PCIX = 0x03,
198 PCI_SPEED_133MHz_PCIX = 0x04,
199 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
200 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
201 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
202 PCI_SPEED_66MHz_PCIX_266 = 0x09,
203 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
204 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 205 AGP_UNKNOWN = 0x0c,
206 AGP_1X = 0x0d,
207 AGP_2X = 0x0e,
208 AGP_4X = 0x0f,
209 AGP_8X = 0x10,
536c8cb4
MW		 210 PCI_SPEED_66MHz_PCIX_533 = 0x11,
211 PCI_SPEED_100MHz_PCIX_533 = 0x12,
212 PCI_SPEED_133MHz_PCIX_533 = 0x13,
213 PCIE_SPEED_2_5GT = 0x14,
214 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 215 PCIE_SPEED_8_0GT = 0x16,
536c8cb4
MW		 216 PCI_SPEED_UNKNOWN = 0xff,
217};
218
24a4742f 219struct pci_cap_saved_data {
41017f0c 220 char cap_nr;
24a4742f 221 unsigned int size;
41017f0c
SL		 222 u32 data[0];
223};
224
24a4742f
AW		 225struct pci_cap_saved_state {
226 struct hlist_node next;
227 struct pci_cap_saved_data cap;
228};
229
7d715a6c 230struct pcie_link_state;
ee69439c 231struct pci_vpd;
d1b054da 232struct pci_sriov;
302b4215 233struct pci_ats;
ee69439c 234
1da177e4
LT		 235/*
236 * The pci_dev structure is used to describe PCI devices.
237 */
238struct pci_dev {
1da177e4
LT		 239 struct list_head bus_list; /* node in per-bus list */
240 struct pci_bus *bus; /* bus this device is on */
241 struct pci_bus *subordinate; /* bus this device bridges to */
242
243 void *sysdata; /* hook for sys-specific extension */
244 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
f46753c5 245 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4
LT		 246
247 unsigned int devfn; /* encoded device & function index */
248 unsigned short vendor;
249 unsigned short device;
250 unsigned short subsystem_vendor;
251 unsigned short subsystem_device;
252 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 253 u8 revision; /* PCI revision, low byte of class word */
1da177e4 254 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
0efea000 255 u8 pcie_cap; /* PCI-E capability offset */
b03e7495
JM		 256 u8 pcie_type:4; /* PCI-E device/port type */
257 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
1da177e4 258 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 259 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 260
261 struct pci_driver *driver; /* which driver has allocated this device */
262 u64 dma_mask; /* Mask of the bits of bus address this
263 device implements. Normally this is
264 0xffffffff. You only need to change
265 this if your device has broken DMA
266 or supports 64-bit transfers. */
267
4d57cdfa
FT		 268 struct device_dma_parameters dma_parms;
269
1da177e4
LT		 270 pci_power_t current_state; /* Current operating state. In ACPI-speak,
271 this is D0-D3, D0 being fully functional,
272 and D3 being off. */
337001b6
RW		 273 int pm_cap; /* PM capability offset in the
274 configuration space */
275 unsigned int pme_support:5; /* Bitmask of states from which PME#
276 can be generated */
c7f48656 277 unsigned int pme_interrupt:1;
379021d5 278 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 279 unsigned int d1_support:1; /* Low power state D1 is supported */
280 unsigned int d2_support:1; /* Low power state D2 is supported */
281 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
253d2e54
JP		 282 unsigned int mmio_always_on:1; /* disallow turning off io/mem
283 decoding during bar sizing */
e80bb09d 284 unsigned int wakeup_prepared:1;
1ae861e6 285 unsigned int d3_delay; /* D3->D0 transition time in ms */
1da177e4 286
7d715a6c
SL		 287#ifdef CONFIG_PCIEASPM
288 struct pcie_link_state *link_state; /* ASPM link state. */
289#endif
290
392a1ce7 291 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 292 struct device dev; /* Generic device interface */
293
1da177e4
LT		 294 int cfg_size; /* Size of configuration space */
295
296 /*
297 * Instead of touching interrupt line and base address registers
298 * directly, use the values stored here. They might be different!
299 */
300 unsigned int irq;
301 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
302
303 /* These fields are used by common fixups */
304 unsigned int transparent:1; /* Transparent PCI bridge */
305 unsigned int multifunction:1;/* Part of multi-function device */
306 /* keep track of device state */
8a1bc901 307 unsigned int is_added:1;
1da177e4 308 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 309 unsigned int no_msi:1; /* device may not use msi */
fb51ccbf 310 unsigned int block_cfg_access:1; /* config space access is blocked */
bd8481e1 311 unsigned int broken_parity_status:1; /* Device generates false positive parity */
e1d3a908 312 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
99dc804d
SL		 313 unsigned int msi_enabled:1;
314 unsigned int msix_enabled:1;
58c3a727 315 unsigned int ari_enabled:1; /* ARI forwarding */
9ac7849e 316 unsigned int is_managed:1;
6d3be84a
KK		 317 unsigned int is_pcie:1; /* Obsolete. Will be removed.
318 Use pci_is_pcie() instead */
260d703a 319 unsigned int needs_freset:1; /* Dev requires fundamental reset */
aa8c6c93 320 unsigned int state_saved:1;
d1b054da 321 unsigned int is_physfn:1;
dd7cc44d 322 unsigned int is_virtfn:1;
711d5779 323 unsigned int reset_fn:1;
28760489 324 unsigned int is_hotplug_bridge:1;
affb72c3
HY		 325 unsigned int __aer_firmware_first_valid:1;
326 unsigned int __aer_firmware_first:1;
ba698ad4 327 pci_dev_flags_t dev_flags;
bae94d02 328 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 329
1da177e4 330 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 331 struct hlist_head saved_cap_space;
1da177e4
LT		 332 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
333 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
334 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 335 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
ded86d8d 336#ifdef CONFIG_PCI_MSI
4aa9bc95 337 struct list_head msi_list;
da8d1c8b 338 struct kset *msi_kset;
ded86d8d 339#endif
94e61088 340 struct pci_vpd *vpd;
466b3ddf 341#ifdef CONFIG_PCI_ATS
dd7cc44d
YZ		 342 union {
343 struct pci_sriov *sriov; /* SR-IOV capability related */
344 struct pci_dev *physfn; /* the PF this VF is associated with */
345 };
302b4215 346 struct pci_ats *ats; /* Address Translation Service */
d1b054da 347#endif
1da177e4
LT		 348};
349
dda56549
Y		 350static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
351{
352#ifdef CONFIG_PCI_IOV
353 if (dev->is_virtfn)
354 dev = dev->physfn;
355#endif
356
357 return dev;
358}
359
65891215
ME		 360extern struct pci_dev *alloc_pci_dev(void);
361
1da177e4
LT		 362#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
363#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
364#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
365
a7369f1f
LV		 366static inline int pci_channel_offline(struct pci_dev *pdev)
367{
368 return (pdev->error_state != pci_channel_io_normal);
369}
370
0efd5aab
BH		 371struct pci_host_bridge_window {
372 struct list_head list;
373 struct resource *res; /* host bridge aperture (CPU address) */
374 resource_size_t offset; /* bus address + offset = CPU address */
375};
41017f0c 376
5a21d70d
BH		 377struct pci_host_bridge {
378 struct list_head list;
379 struct pci_bus *bus; /* root bus */
0efd5aab 380 struct list_head windows; /* pci_host_bridge_windows */
5a21d70d 381};
41017f0c 382
2fe2abf8
BH		 383/*
384 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
385 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
386 * buses below host bridges or subtractive decode bridges) go in the list.
387 * Use pci_bus_for_each_resource() to iterate through all the resources.
388 */
389
390/*
391 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
392 * and there's no way to program the bridge with the details of the window.
393 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
394 * decode bit set, because they are explicit and can be programmed with _SRS.
395 */
396#define PCI_SUBTRACTIVE_DECODE 0x1
397
398struct pci_bus_resource {
399 struct list_head list;
400 struct resource *res;
401 unsigned int flags;
402};
4352dfd5
GKH		 403
404#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 405
406struct pci_bus {
407 struct list_head node; /* node in list of buses */
408 struct pci_bus *parent; /* parent bus this bridge is on */
409 struct list_head children; /* list of child buses */
410 struct list_head devices; /* list of devices on this bus */
411 struct pci_dev *self; /* bridge device as seen by parent */
f46753c5 412 struct list_head slots; /* list of slots on this bus */
2fe2abf8
BH		 413 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
414 struct list_head resources; /* address space routed to this bus */
1da177e4
LT		 415
416 struct pci_ops *ops; /* configuration access functions */
417 void *sysdata; /* hook for sys-specific extension */
418 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
419
420 unsigned char number; /* bus number */
421 unsigned char primary; /* number of primary bridge */
422 unsigned char secondary; /* number of secondary bridge */
423 unsigned char subordinate; /* max number of subordinate buses */
3749c51a
MW		 424 unsigned char max_bus_speed; /* enum pci_bus_speed */
425 unsigned char cur_bus_speed; /* enum pci_bus_speed */
1da177e4
LT		 426
427 char name[48];
428
429 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 430 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4 431 struct device *bridge;
fd7d1ced 432 struct device dev;
1da177e4
LT		 433 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
434 struct bin_attribute *legacy_mem; /* legacy mem */
cc74d96f 435 unsigned int is_added:1;
1da177e4
LT		 436};
437
438#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
fd7d1ced 439#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 440
79af72d7
KK		 441/*
442 * Returns true if the pci bus is root (behind host-pci bridge),
443 * false otherwise
444 */
445static inline bool pci_is_root_bus(struct pci_bus *pbus)
446{
447 return !(pbus->parent);
448}
449
16cf0ebc
RW		 450#ifdef CONFIG_PCI_MSI
451static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
452{
453 return pci_dev->msi_enabled || pci_dev->msix_enabled;
454}
455#else
456static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
457#endif
458
1da177e4
LT		 459/*
460 * Error values that may be returned by PCI functions.
461 */
462#define PCIBIOS_SUCCESSFUL 0x00
463#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
464#define PCIBIOS_BAD_VENDOR_ID 0x83
465#define PCIBIOS_DEVICE_NOT_FOUND 0x86
466#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
467#define PCIBIOS_SET_FAILED 0x88
468#define PCIBIOS_BUFFER_TOO_SMALL 0x89
469
470/* Low-level architecture-dependent routines */
471
472struct pci_ops {
473 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
474 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
475};
476
b6ce068a
MW		 477/*
478 * ACPI needs to be able to access PCI config space before we've done a
479 * PCI bus scan and created pci_bus structures.
480 */
481extern int raw_pci_read(unsigned int domain, unsigned int bus,
482 unsigned int devfn, int reg, int len, u32 *val);
483extern int raw_pci_write(unsigned int domain, unsigned int bus,
484 unsigned int devfn, int reg, int len, u32 val);
1da177e4
LT		 485
486struct pci_bus_region {
c40a22e0
BH		 487 resource_size_t start;
488 resource_size_t end;
1da177e4
LT		 489};
490
491struct pci_dynids {
492 spinlock_t lock; /* protects list, index */
493 struct list_head list; /* for IDs added at runtime */
1da177e4
LT		 494};
495
392a1ce7
LV		 496/* ---------------------------------------------------------------- */
497/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
579082df 498 * a set of callbacks in struct pci_error_handlers, then that device driver
392a1ce7
LV		 499 * will be notified of PCI bus errors, and will be driven to recovery
500 * when an error occurs.
501 */
502
503typedef unsigned int __bitwise pci_ers_result_t;
504
505enum pci_ers_result {
506 /* no result/none/not supported in device driver */
507 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
508
509 /* Device driver can recover without slot reset */
510 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
511
512 /* Device driver wants slot to be reset. */
513 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
514
515 /* Device has completely failed, is unrecoverable */
516 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
517
518 /* Device driver is fully recovered and operational */
519 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
520};
521
522/* PCI bus error event callbacks */
05cca6e5 523struct pci_error_handlers {
392a1ce7
LV		 524 /* PCI bus error detected on this device */
525 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 526 enum pci_channel_state error);
392a1ce7
LV		 527
528 /* MMIO has been re-enabled, but not DMA */
529 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
530
531 /* PCI Express link has been reset */
532 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
533
534 /* PCI slot has been reset */
535 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
536
537 /* Device driver may resume normal operations */
538 void (*resume)(struct pci_dev *dev);
539};
540
541/* ---------------------------------------------------------------- */
542
1da177e4
LT		 543struct module;
544struct pci_driver {
545 struct list_head node;
42b21932 546 const char *name;
1da177e4
LT		 547 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
548 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
549 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
550 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 551 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
552 int (*resume_early) (struct pci_dev *dev);
1da177e4 553 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 554 void (*shutdown) (struct pci_dev *dev);
392a1ce7 555 struct pci_error_handlers *err_handler;
1da177e4
LT		 556 struct device_driver driver;
557 struct pci_dynids dynids;
558};
559
05cca6e5 560#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4 561
90a1ba0c 562/**
9f9351bb 563 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
90a1ba0c
JB		 564 * @_table: device table name
565 *
566 * This macro is used to create a struct pci_device_id array (a device table)
567 * in a generic manner.
568 */
9f9351bb 569#define DEFINE_PCI_DEVICE_TABLE(_table) \
90a1ba0c
JB		 570 const struct pci_device_id _table[] __devinitconst
571
1da177e4
LT		 572/**
573 * PCI_DEVICE - macro used to describe a specific pci device
574 * @vend: the 16 bit PCI Vendor ID
575 * @dev: the 16 bit PCI Device ID
576 *
577 * This macro is used to create a struct pci_device_id that matches a
578 * specific device. The subvendor and subdevice fields will be set to
579 * PCI_ANY_ID.
580 */
581#define PCI_DEVICE(vend,dev) \
582 .vendor = (vend), .device = (dev), \
583 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
584
585/**
586 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
587 * @dev_class: the class, subclass, prog-if triple for this device
588 * @dev_class_mask: the class mask for this device
589 *
590 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 591 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 592 * fields will be set to PCI_ANY_ID.
593 */
594#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
595 .class = (dev_class), .class_mask = (dev_class_mask), \
596 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
597 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
598
1597cacb
AC		 599/**
600 * PCI_VDEVICE - macro used to describe a specific pci device in short form
c322b28a
ZY		 601 * @vendor: the vendor name
602 * @device: the 16 bit PCI Device ID
1597cacb
AC		 603 *
604 * This macro is used to create a struct pci_device_id that matches a
605 * specific PCI device. The subvendor, and subdevice fields will be set
606 * to PCI_ANY_ID. The macro allows the next field to follow as the device
607 * private data.
608 */
609
610#define PCI_VDEVICE(vendor, device) \
611 PCI_VENDOR_ID_##vendor, (device), \
612 PCI_ANY_ID, PCI_ANY_ID, 0, 0
613
1da177e4
LT		 614/* these external functions are only available when PCI support is enabled */
615#ifdef CONFIG_PCI
616
b03e7495
JM		 617extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
618
619enum pcie_bus_config_types {
5f39e670 620 PCIE_BUS_TUNE_OFF,
b03e7495 621 PCIE_BUS_SAFE,
5f39e670 622 PCIE_BUS_PERFORMANCE,
b03e7495
JM		 623 PCIE_BUS_PEER2PEER,
624};
625
626extern enum pcie_bus_config_types pcie_bus_config;
627
1da177e4
LT		 628extern struct bus_type pci_bus_type;
629
630/* Do NOT directly access these two variables, unless you are arch specific pci
631 * code, or pci core code. */
632extern struct list_head pci_root_buses; /* list of all known PCI buses */
ed4aaadb
ZY		 633/* Some device drivers need know if pci is initiated */
634extern int no_pci_devices(void);
1da177e4
LT		 635
636void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 637int __must_check pcibios_enable_device(struct pci_dev *, int mask);
05cca6e5 638char *pcibios_setup(char *str);
1da177e4
LT		 639
640/* Used only when drivers/pci/setup.c is used */
3b7a17fc 641resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 642 resource_size_t,
e31dd6e4 643 resource_size_t);
1da177e4
LT		 644void pcibios_update_irq(struct pci_dev *, int irq);
645
2d1c8618
BH		 646/* Weak but can be overriden by arch */
647void pci_fixup_cardbus(struct pci_bus *);
648
1da177e4
LT		 649/* Generic PCI functions used internally */
650
36a66cd6
BH		 651void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
652 struct resource *res);
653void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
654 struct pci_bus_region *region);
d1fd4fb6 655void pcibios_scan_specific_bus(int busn);
1da177e4 656extern struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 657void pci_bus_add_devices(const struct pci_bus *bus);
05cca6e5
GKH		 658struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
659 struct pci_ops *ops, void *sysdata);
de4b2f76 660struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 661struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
662 struct pci_ops *ops, void *sysdata,
663 struct list_head *resources);
a2ebb827
BH		 664struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
665 struct pci_ops *ops, void *sysdata,
666 struct list_head *resources);
05cca6e5
GKH		 667struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
668 int busnr);
3749c51a 669void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 670struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 671 const char *name,
672 struct hotplug_slot *hotplug);
f46753c5 673void pci_destroy_slot(struct pci_slot *slot);
d25b7c8d 674void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
1da177e4 675int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 676struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 677void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 678unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 679int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4 680void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 681struct resource *pci_find_parent_resource(const struct pci_dev *dev,
682 struct resource *res);
57c2cf71 683u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
1da177e4 684int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 685u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1da177e4
LT		 686extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
687extern void pci_dev_put(struct pci_dev *dev);
688extern void pci_remove_bus(struct pci_bus *b);
6b22cf3f 689extern void __pci_remove_bus_device(struct pci_dev *dev);
210647af 690extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
24f8aa9b 691extern void pci_stop_bus_device(struct pci_dev *dev);
b3743fa4 692void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 693extern void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 694#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
695#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
696#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
1da177e4
LT		 697
698/* Generic PCI functions exported to card drivers */
699
388c8c16
JB		 700enum pci_lost_interrupt_reason {
701 PCI_LOST_IRQ_NO_INFORMATION = 0,
702 PCI_LOST_IRQ_DISABLE_MSI,
703 PCI_LOST_IRQ_DISABLE_MSIX,
704 PCI_LOST_IRQ_DISABLE_ACPI,
705};
706enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 707int pci_find_capability(struct pci_dev *dev, int cap);
708int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
709int pci_find_ext_capability(struct pci_dev *dev, int cap);
cf4c43dd
JB		 710int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
711 int cap);
05cca6e5
GKH		 712int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
713int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 714struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 715
d42552c3
AM		 716struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
717 struct pci_dev *from);
05cca6e5 718struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1da177e4 719 unsigned int ss_vendor, unsigned int ss_device,
b08508c4 720 struct pci_dev *from);
05cca6e5 721struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 722struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
723 unsigned int devfn);
724static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
725 unsigned int devfn)
726{
727 return pci_get_domain_bus_and_slot(0, bus, devfn);
728}
05cca6e5 729struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 730int pci_dev_present(const struct pci_device_id *ids);
731
05cca6e5
GKH		 732int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
733 int where, u8 *val);
734int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
735 int where, u16 *val);
736int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
737 int where, u32 *val);
738int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
739 int where, u8 val);
740int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
741 int where, u16 val);
742int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
743 int where, u32 val);
a72b46c3 744struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 745
bf362f75 746static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
1da177e4 747{
05cca6e5 748 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 749}
bf362f75 750static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
1da177e4 751{
05cca6e5 752 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
1da177e4 753}
bf362f75 754static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
05cca6e5 755 u32 *val)
1da177e4 756{
05cca6e5 757 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
1da177e4 758}
bf362f75 759static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
1da177e4 760{
05cca6e5 761 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 762}
bf362f75 763static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
1da177e4 764{
05cca6e5 765 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
1da177e4 766}
bf362f75 767static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
05cca6e5 768 u32 val)
1da177e4 769{
05cca6e5 770 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
1da177e4
LT		 771}
772
4a7fb636 773int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 774int __must_check pci_enable_device_io(struct pci_dev *dev);
775int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 776int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 777int __must_check pcim_enable_device(struct pci_dev *pdev);
778void pcim_pin_device(struct pci_dev *pdev);
779
296ccb08
YS		 780static inline int pci_is_enabled(struct pci_dev *pdev)
781{
782 return (atomic_read(&pdev->enable_cnt) > 0);
783}
784
9ac7849e
TH		 785static inline int pci_is_managed(struct pci_dev *pdev)
786{
787 return pdev->is_managed;
788}
789
1da177e4 790void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 791
792extern unsigned int pcibios_max_latency;
1da177e4 793void pci_set_master(struct pci_dev *dev);
6a479079 794void pci_clear_master(struct pci_dev *dev);
96c55900 795
f7bdd12d 796int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 797int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 798#define HAVE_PCI_SET_MWI
4a7fb636 799int __must_check pci_set_mwi(struct pci_dev *dev);
694625c0 800int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 801void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 802void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 803bool pci_intx_mask_supported(struct pci_dev *dev);
804bool pci_check_and_mask_intx(struct pci_dev *dev);
805bool pci_check_and_unmask_intx(struct pci_dev *dev);
f5f2b131 806void pci_msi_off(struct pci_dev *dev);
4d57cdfa 807int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
59fc67de 808int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
d556ad4b
PO		 809int pcix_get_max_mmrbc(struct pci_dev *dev);
810int pcix_get_mmrbc(struct pci_dev *dev);
811int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 812int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 813int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 814int pcie_get_mps(struct pci_dev *dev);
815int pcie_set_mps(struct pci_dev *dev, int mps);
8c1c699f 816int __pci_reset_function(struct pci_dev *dev);
a96d627a 817int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 818int pci_reset_function(struct pci_dev *dev);
14add80b 819void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 820int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 821int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
c87deff7 822int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1da177e4
LT		 823
824/* ROM control related routines */
e416de5e
AC		 825int pci_enable_rom(struct pci_dev *pdev);
826void pci_disable_rom(struct pci_dev *pdev);
144a50ea 827void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 828void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 829size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1da177e4
LT		 830
831/* Power management related routines */
832int pci_save_state(struct pci_dev *dev);
1d3c16a8 833void pci_restore_state(struct pci_dev *dev);
ffbdd3f7
AW		 834struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
835int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
836int pci_load_and_free_saved_state(struct pci_dev *dev,
837 struct pci_saved_state **state);
0e5dd46b 838int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 839int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
840pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 841bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 842void pci_pme_active(struct pci_dev *dev, bool enable);
6cbf8214
RW		 843int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
844 bool runtime, bool enable);
0235c4fc 845int pci_wake_from_d3(struct pci_dev *dev, bool enable);
e5899e1b 846pci_power_t pci_target_state(struct pci_dev *dev);
404cc2d8
RW		 847int pci_prepare_to_sleep(struct pci_dev *dev);
848int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 849bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 850bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 851void pci_pme_wakeup_bus(struct pci_bus *bus);
1da177e4 852
6cbf8214
RW		 853static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
854 bool enable)
855{
856 return __pci_enable_wake(dev, state, false, enable);
857}
1da177e4 858
b48d4425
JB		 859#define PCI_EXP_IDO_REQUEST (1<<0)
860#define PCI_EXP_IDO_COMPLETION (1<<1)
861void pci_enable_ido(struct pci_dev *dev, unsigned long type);
862void pci_disable_ido(struct pci_dev *dev, unsigned long type);
863
48a92a81 864enum pci_obff_signal_type {
688398bb
MS		 865 PCI_EXP_OBFF_SIGNAL_L0 = 0,
866 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
48a92a81
JB		 867};
868int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
869void pci_disable_obff(struct pci_dev *dev);
870
51c2e0a7
JB		 871bool pci_ltr_supported(struct pci_dev *dev);
872int pci_enable_ltr(struct pci_dev *dev);
873void pci_disable_ltr(struct pci_dev *dev);
874int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
875
bb209c82
BH		 876/* For use by arch with custom probe code */
877void set_pcie_port_type(struct pci_dev *pdev);
878void set_pcie_hotplug_bridge(struct pci_dev *pdev);
879
ce5ccdef 880/* Functions for PCI Hotplug drivers to use */
05cca6e5 881int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
3ed4fd96 882#ifdef CONFIG_HOTPLUG
2f320521 883unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96
AC		 884unsigned int pci_rescan_bus(struct pci_bus *bus);
885#endif
ce5ccdef 886
287d19ce
SH		 887/* Vital product data routines */
888ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
889ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
db567943 890int pci_vpd_truncate(struct pci_dev *dev, size_t size);
287d19ce 891
1da177e4 892/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 893resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 894void pci_bus_assign_resources(const struct pci_bus *bus);
1da177e4
LT		 895void pci_bus_size_bridges(struct pci_bus *bus);
896int pci_claim_resource(struct pci_dev *, int);
897void pci_assign_unassigned_resources(void);
6841ec68 898void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1da177e4 899void pdev_enable_device(struct pci_dev *);
842de40d 900int pci_enable_resources(struct pci_dev *, int mask);
1da177e4 901void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
d5341942 902 int (*)(const struct pci_dev *, u8, u8));
1da177e4 903#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 904int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 905int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 906void pci_release_regions(struct pci_dev *);
4a7fb636 907int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 908int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 909void pci_release_region(struct pci_dev *, int);
c87deff7 910int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 911int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 912void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 913
914/* drivers/pci/bus.c */
45ca9e97 915void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 916void pci_add_resource_offset(struct list_head *resources, struct resource *res,
917 resource_size_t offset);
45ca9e97 918void pci_free_resource_list(struct list_head *resources);
2fe2abf8
BH		 919void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
920struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
921void pci_bus_remove_resources(struct pci_bus *bus);
922
89a74ecc 923#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 924 for (i = 0; \
925 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
926 i++)
89a74ecc 927
4a7fb636
AM		 928int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
929 struct resource *res, resource_size_t size,
930 resource_size_t align, resource_size_t min,
931 unsigned int type_mask,
3b7a17fc
DB		 932 resource_size_t (*alignf)(void *,
933 const struct resource *,
b26b2d49
DB		 934 resource_size_t,
935 resource_size_t),
4a7fb636 936 void *alignf_data);
1da177e4
LT		 937void pci_enable_bridges(struct pci_bus *bus);
938
863b18f4 939/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 940int __must_check __pci_register_driver(struct pci_driver *, struct module *,
941 const char *mod_name);
bba81165
AM		 942
943/*
944 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
945 */
946#define pci_register_driver(driver) \
947 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 948
05cca6e5 949void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 950
951/**
952 * module_pci_driver() - Helper macro for registering a PCI driver
953 * @__pci_driver: pci_driver struct
954 *
955 * Helper macro for PCI drivers which do not do anything special in module
956 * init/exit. This eliminates a lot of boilerplate. Each module may only
957 * use this macro once, and calling it replaces module_init() and module_exit()
958 */
959#define module_pci_driver(__pci_driver) \
960 module_driver(__pci_driver, pci_register_driver, \
961 pci_unregister_driver)
962
6754b9e9 963void pci_stop_and_remove_behind_bridge(struct pci_dev *dev);
05cca6e5 964struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 965int pci_add_dynid(struct pci_driver *drv,
966 unsigned int vendor, unsigned int device,
967 unsigned int subvendor, unsigned int subdevice,
968 unsigned int class, unsigned int class_mask,
969 unsigned long driver_data);
05cca6e5
GKH		 970const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
971 struct pci_dev *dev);
972int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
973 int pass);
1da177e4 974
70298c6e 975void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 976 void *userdata);
70b9f7dc 977int pci_cfg_space_size_ext(struct pci_dev *dev);
ac7dc65a 978int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 979unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 980void pci_setup_bridge(struct pci_bus *bus);
cecf4864 981
3448a19d
DA		 982#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
983#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
984
deb2d2ec 985int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 986 unsigned int command_bits, u32 flags);
1da177e4
LT		 987/* kmem_cache style wrapper around pci_alloc_consistent() */
988
f41b1771 989#include <linux/pci-dma.h>
1da177e4
LT		 990#include <linux/dmapool.h>
991
992#define pci_pool dma_pool
993#define pci_pool_create(name, pdev, size, align, allocation) \
994 dma_pool_create(name, &pdev->dev, size, align, allocation)
995#define pci_pool_destroy(pool) dma_pool_destroy(pool)
996#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
997#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
998
e24c2d96
DM		 999enum pci_dma_burst_strategy {
1000 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1001 strategy_parameter is N/A */
1002 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1003 byte boundaries */
1004 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1005 strategy_parameter byte boundaries */
1006};
1007
1da177e4 1008struct msix_entry {
16dbef4a 1009 u32 vector; /* kernel uses to write allocated vector */
1da177e4
LT		 1010 u16 entry; /* driver uses to specify entry, OS writes */
1011};
1012
0366f8f7 1013
1da177e4 1014#ifndef CONFIG_PCI_MSI
1c8d7b0a 1015static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
05cca6e5
GKH		 1016{
1017 return -1;
1018}
1019
d52877c7
YL		 1020static inline void pci_msi_shutdown(struct pci_dev *dev)
1021{ }
05cca6e5
GKH		 1022static inline void pci_disable_msi(struct pci_dev *dev)
1023{ }
1024
a52e2e35
RW		 1025static inline int pci_msix_table_size(struct pci_dev *dev)
1026{
1027 return 0;
1028}
05cca6e5
GKH		 1029static inline int pci_enable_msix(struct pci_dev *dev,
1030 struct msix_entry *entries, int nvec)
1031{
1032 return -1;
1033}
1034
d52877c7
YL		 1035static inline void pci_msix_shutdown(struct pci_dev *dev)
1036{ }
05cca6e5
GKH		 1037static inline void pci_disable_msix(struct pci_dev *dev)
1038{ }
1039
1040static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1041{ }
1042
1043static inline void pci_restore_msi_state(struct pci_dev *dev)
1044{ }
07ae95f9
AP		 1045static inline int pci_msi_enabled(void)
1046{
1047 return 0;
1048}
1da177e4 1049#else
1c8d7b0a 1050extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
d52877c7 1051extern void pci_msi_shutdown(struct pci_dev *dev);
1da177e4 1052extern void pci_disable_msi(struct pci_dev *dev);
a52e2e35 1053extern int pci_msix_table_size(struct pci_dev *dev);
05cca6e5 1054extern int pci_enable_msix(struct pci_dev *dev,
1da177e4 1055 struct msix_entry *entries, int nvec);
d52877c7 1056extern void pci_msix_shutdown(struct pci_dev *dev);
1da177e4
LT		 1057extern void pci_disable_msix(struct pci_dev *dev);
1058extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
94688cf2 1059extern void pci_restore_msi_state(struct pci_dev *dev);
07ae95f9 1060extern int pci_msi_enabled(void);
1da177e4
LT		 1061#endif
1062
ab0724ff 1063#ifdef CONFIG_PCIEPORTBUS
415e12b2
RW		 1064extern bool pcie_ports_disabled;
1065extern bool pcie_ports_auto;
ab0724ff
MT		 1066#else
1067#define pcie_ports_disabled true
1068#define pcie_ports_auto false
1069#endif
415e12b2 1070
3e1b1600 1071#ifndef CONFIG_PCIEASPM
8b8bae90
RW		 1072static inline int pcie_aspm_enabled(void) { return 0; }
1073static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1074#else
1075extern int pcie_aspm_enabled(void);
8b8bae90 1076extern bool pcie_aspm_support_enabled(void);
3e1b1600
AP		 1077#endif
1078
415e12b2
RW		 1079#ifdef CONFIG_PCIEAER
1080void pci_no_aer(void);
1081bool pci_aer_available(void);
1082#else
1083static inline void pci_no_aer(void) { }
1084static inline bool pci_aer_available(void) { return false; }
1085#endif
1086
43c16408
AP		 1087#ifndef CONFIG_PCIE_ECRC
1088static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1089{
1090 return;
1091}
1092static inline void pcie_ecrc_get_policy(char *str) {};
1093#else
1094extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1095extern void pcie_ecrc_get_policy(char *str);
1096#endif
1097
1c8d7b0a
MW		 1098#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1099
8b955b0d 1100#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 1101/* The functions a driver should call */
1102int ht_create_irq(struct pci_dev *dev, int idx);
1103void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 1104#endif /* CONFIG_HT_IRQ */
1105
fb51ccbf
JK		 1106extern void pci_cfg_access_lock(struct pci_dev *dev);
1107extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1108extern void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1109
4352dfd5
GKH		 1110/*
1111 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1112 * a PCI domain is defined to be a set of PCI busses which share
1113 * configuration space.
1114 */
32a2eea7
JG		 1115#ifdef CONFIG_PCI_DOMAINS
1116extern int pci_domains_supported;
1117#else
1118enum { pci_domains_supported = 0 };
05cca6e5
GKH		 1119static inline int pci_domain_nr(struct pci_bus *bus)
1120{
1121 return 0;
1122}
1123
4352dfd5
GKH		 1124static inline int pci_proc_domain(struct pci_bus *bus)
1125{
1126 return 0;
1127}
32a2eea7 1128#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1129
95a8b6ef
MT		 1130/* some architectures require additional setup to direct VGA traffic */
1131typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
3448a19d 1132 unsigned int command_bits, u32 flags);
95a8b6ef
MT		 1133extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1134
4352dfd5 1135#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 1136
1137/*
1138 * If the system does not have PCI, clearly these return errors. Define
1139 * these as simple inline functions to avoid hair in drivers.
1140 */
1141
05cca6e5
GKH		 1142#define _PCI_NOP(o, s, t) \
1143 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1144 int where, t val) \
1da177e4 1145 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1146
1147#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1148 _PCI_NOP(o, word, u16 x) \
1149 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1150_PCI_NOP_ALL(read, *)
1151_PCI_NOP_ALL(write,)
1152
d42552c3 1153static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1154 unsigned int device,
1155 struct pci_dev *from)
1156{
1157 return NULL;
1158}
d42552c3 1159
05cca6e5
GKH		 1160static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1161 unsigned int device,
1162 unsigned int ss_vendor,
1163 unsigned int ss_device,
b08508c4 1164 struct pci_dev *from)
05cca6e5
GKH		 1165{
1166 return NULL;
1167}
1da177e4 1168
05cca6e5
GKH		 1169static inline struct pci_dev *pci_get_class(unsigned int class,
1170 struct pci_dev *from)
1171{
1172 return NULL;
1173}
1da177e4
LT		 1174
1175#define pci_dev_present(ids) (0)
ed4aaadb 1176#define no_pci_devices() (1)
1da177e4
LT		 1177#define pci_dev_put(dev) do { } while (0)
1178
05cca6e5
GKH		 1179static inline void pci_set_master(struct pci_dev *dev)
1180{ }
1181
1182static inline int pci_enable_device(struct pci_dev *dev)
1183{
1184 return -EIO;
1185}
1186
1187static inline void pci_disable_device(struct pci_dev *dev)
1188{ }
1189
1190static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1191{
1192 return -EIO;
1193}
1194
80be0385
RD		 1195static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1196{
1197 return -EIO;
1198}
1199
4d57cdfa
FT		 1200static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1201 unsigned int size)
1202{
1203 return -EIO;
1204}
1205
59fc67de
FT		 1206static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1207 unsigned long mask)
1208{
1209 return -EIO;
1210}
1211
05cca6e5
GKH		 1212static inline int pci_assign_resource(struct pci_dev *dev, int i)
1213{
1214 return -EBUSY;
1215}
1216
1217static inline int __pci_register_driver(struct pci_driver *drv,
1218 struct module *owner)
1219{
1220 return 0;
1221}
1222
1223static inline int pci_register_driver(struct pci_driver *drv)
1224{
1225 return 0;
1226}
1227
1228static inline void pci_unregister_driver(struct pci_driver *drv)
1229{ }
1230
1231static inline int pci_find_capability(struct pci_dev *dev, int cap)
1232{
1233 return 0;
1234}
1235
1236static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1237 int cap)
1238{
1239 return 0;
1240}
1241
1242static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1243{
1244 return 0;
1245}
1246
1da177e4 1247/* Power management related routines */
05cca6e5
GKH		 1248static inline int pci_save_state(struct pci_dev *dev)
1249{
1250 return 0;
1251}
1252
1d3c16a8
JM		 1253static inline void pci_restore_state(struct pci_dev *dev)
1254{ }
1da177e4 1255
05cca6e5
GKH		 1256static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1257{
1258 return 0;
1259}
1260
3449248c
RD		 1261static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1262{
1263 return 0;
1264}
1265
05cca6e5
GKH		 1266static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1267 pm_message_t state)
1268{
1269 return PCI_D0;
1270}
1271
1272static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1273 int enable)
1274{
1275 return 0;
1276}
1277
b48d4425
JB		 1278static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1279{
1280}
1281
1282static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1283{
1284}
1285
48a92a81
JB		 1286static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1287{
1288 return 0;
1289}
1290
1291static inline void pci_disable_obff(struct pci_dev *dev)
1292{
1293}
1294
05cca6e5
GKH		 1295static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1296{
1297 return -EIO;
1298}
1299
1300static inline void pci_release_regions(struct pci_dev *dev)
1301{ }
0da0ead9 1302
a46e8126
KG		 1303#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1304
fb51ccbf 1305static inline void pci_block_cfg_access(struct pci_dev *dev)
05cca6e5
GKH		 1306{ }
1307
fb51ccbf
JK		 1308static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1309{ return 0; }
1310
1311static inline void pci_unblock_cfg_access(struct pci_dev *dev)
05cca6e5 1312{ }
e04b0ea2 1313
d80d0217
RD		 1314static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1315{ return NULL; }
1316
1317static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1318 unsigned int devfn)
1319{ return NULL; }
1320
1321static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1322 unsigned int devfn)
1323{ return NULL; }
1324
92298e66
DA		 1325static inline int pci_domain_nr(struct pci_bus *bus)
1326{ return 0; }
1327
fb8a0d9d
WM		 1328#define dev_is_pci(d) (false)
1329#define dev_is_pf(d) (false)
1330#define dev_num_vf(d) (0)
4352dfd5 1331#endif /* CONFIG_PCI */
1da177e4 1332
4352dfd5
GKH		 1333/* Include architecture-dependent settings and functions */
1334
1335#include <asm/pci.h>
1da177e4 1336
1f82de10
YL		 1337#ifndef PCIBIOS_MAX_MEM_32
1338#define PCIBIOS_MAX_MEM_32 (-1)
1339#endif
1340
1da177e4
LT		 1341/* these helpers provide future and backwards compatibility
1342 * for accessing popular PCI BAR info */
05cca6e5
GKH		 1343#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1344#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1345#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1346#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1347 ((pci_resource_start((dev), (bar)) == 0 && \
1348 pci_resource_end((dev), (bar)) == \
1349 pci_resource_start((dev), (bar))) ? 0 : \
1350 \
1351 (pci_resource_end((dev), (bar)) - \
1352 pci_resource_start((dev), (bar)) + 1))
1da177e4
LT		 1353
1354/* Similar to the helpers above, these manipulate per-pci_dev
1355 * driver-specific data. They are really just a wrapper around
1356 * the generic device structure functions of these calls.
1357 */
05cca6e5 1358static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1359{
1360 return dev_get_drvdata(&pdev->dev);
1361}
1362
05cca6e5 1363static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1364{
1365 dev_set_drvdata(&pdev->dev, data);
1366}
1367
1368/* If you want to know what to call your pci_dev, ask this function.
1369 * Again, it's a wrapper around the generic device.
1370 */
2fc90f61 1371static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1372{
c6c4f070 1373 return dev_name(&pdev->dev);
1da177e4
LT		 1374}
1375
2311b1f2
ME		 1376
1377/* Some archs don't want to expose struct resource to userland as-is
1378 * in sysfs and /proc
1379 */
1380#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1381static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1382 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1383 resource_size_t *end)
2311b1f2
ME		 1384{
1385 *start = rsrc->start;
1386 *end = rsrc->end;
1387}
1388#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1389
1390
1da177e4
LT		 1391/*
1392 * The world is not perfect and supplies us with broken PCI devices.
1393 * For at least a part of these bugs we need a work-around, so both
1394 * generic (drivers/pci/quirks.c) and per-architecture code can define
1395 * fixup hooks to be called for particular buggy devices.
1396 */
1397
1398struct pci_fixup {
f4ca5c6a
YL		 1399 u16 vendor; /* You can use PCI_ANY_ID here of course */
1400 u16 device; /* You can use PCI_ANY_ID here of course */
1401 u32 class; /* You can use PCI_ANY_ID here too */
1402 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1403 void (*hook)(struct pci_dev *dev);
1404};
1405
1406enum pci_fixup_pass {
1407 pci_fixup_early, /* Before probing BARs */
1408 pci_fixup_header, /* After reading configuration header */
1409 pci_fixup_final, /* Final phase of device fixups */
1410 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e
RW		 1411 pci_fixup_resume, /* pci_device_resume() */
1412 pci_fixup_suspend, /* pci_device_suspend */
1413 pci_fixup_resume_early, /* pci_device_resume_early() */
1da177e4
LT		 1414};
1415
1416/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1417#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1418 class_shift, hook) \
1419 static const struct pci_fixup const __pci_fixup_##name __used \
1420 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1421 = { vendor, device, class, class_shift, hook };
1422
1423#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1424 class_shift, hook) \
1425 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1426 vendor##device##hook, vendor, device, class, class_shift, hook)
1427#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1428 class_shift, hook) \
1429 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1430 vendor##device##hook, vendor, device, class, class_shift, hook)
1431#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1432 class_shift, hook) \
1433 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1434 vendor##device##hook, vendor, device, class, class_shift, hook)
1435#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1436 class_shift, hook) \
1437 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1438 vendor##device##hook, vendor, device, class, class_shift, hook)
1439#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1440 class_shift, hook) \
1441 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1442 resume##vendor##device##hook, vendor, device, class, \
1443 class_shift, hook)
1444#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1445 class_shift, hook) \
1446 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1447 resume_early##vendor##device##hook, vendor, device, \
1448 class, class_shift, hook)
1449#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1450 class_shift, hook) \
1451 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1452 suspend##vendor##device##hook, vendor, device, class, \
1453 class_shift, hook)
1454
1da177e4
LT		 1455#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1456 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
f4ca5c6a 1457 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1458#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1459 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
f4ca5c6a 1460 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1461#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1462 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
f4ca5c6a 1463 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1464#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1465 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
f4ca5c6a 1466 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1467#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1468 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
f4ca5c6a
YL		 1469 resume##vendor##device##hook, vendor, device, \
1470 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1471#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1472 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
f4ca5c6a
YL		 1473 resume_early##vendor##device##hook, vendor, device, \
1474 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1475#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1476 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
f4ca5c6a
YL		 1477 suspend##vendor##device##hook, vendor, device, \
1478 PCI_ANY_ID, 0, hook)
1da177e4 1479
93177a74 1480#ifdef CONFIG_PCI_QUIRKS
1da177e4 1481void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
93177a74
RW		 1482#else
1483static inline void pci_fixup_device(enum pci_fixup_pass pass,
1484 struct pci_dev *dev) {}
1485#endif
1da177e4 1486
05cca6e5 1487void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1488void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1489void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1490int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1491int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1492 const char *name);
fb7ebfe4 1493void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1494
1da177e4 1495extern int pci_pci_problems;
236561e5 1496#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1497#define PCIPCI_TRITON 2
1498#define PCIPCI_NATOMA 4
1499#define PCIPCI_VIAETBF 8
1500#define PCIPCI_VSFX 16
236561e5
AC		 1501#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1502#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1503
4516a618
AN		 1504extern unsigned long pci_cardbus_io_size;
1505extern unsigned long pci_cardbus_mem_size;
491424c0 1506extern u8 __devinitdata pci_dfl_cache_line_size;
ac1aa47b 1507extern u8 pci_cache_line_size;
4516a618 1508
28760489
EB		 1509extern unsigned long pci_hotplug_io_size;
1510extern unsigned long pci_hotplug_mem_size;
1511
cfce9fb8 1512/* Architecture specific versions may override these (weak) */
19792a08
AB		 1513int pcibios_add_platform_entries(struct pci_dev *dev);
1514void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1515void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1516int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1517 enum pcie_reset_state state);
575e3348 1518
7752d5cf 1519#ifdef CONFIG_PCI_MMCONFIG
bb63b421 1520extern void __init pci_mmcfg_early_init(void);
7752d5cf
RH		 1521extern void __init pci_mmcfg_late_init(void);
1522#else
bb63b421 1523static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1524static inline void pci_mmcfg_late_init(void) { }
1525#endif
1526
0ef5f8f6
AP		 1527int pci_ext_cfg_avail(struct pci_dev *dev);
1528
1684f5dd 1529void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1530
dd7cc44d
YZ		 1531#ifdef CONFIG_PCI_IOV
1532extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1533extern void pci_disable_sriov(struct pci_dev *dev);
74bb1bcc 1534extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
fb8a0d9d 1535extern int pci_num_vf(struct pci_dev *dev);
dd7cc44d
YZ		 1536#else
1537static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1538{
1539 return -ENODEV;
1540}
1541static inline void pci_disable_sriov(struct pci_dev *dev)
1542{
1543}
74bb1bcc
YZ		 1544static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1545{
1546 return IRQ_NONE;
1547}
fb8a0d9d
WM		 1548static inline int pci_num_vf(struct pci_dev *dev)
1549{
1550 return 0;
1551}
dd7cc44d
YZ		 1552#endif
1553
c825bc94
KK		 1554#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1555extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1556extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1557#endif
1558
d7b7e605
KK		 1559/**
1560 * pci_pcie_cap - get the saved PCIe capability offset
1561 * @dev: PCI device
1562 *
1563 * PCIe capability offset is calculated at PCI device initialization
1564 * time and saved in the data structure. This function returns saved
1565 * PCIe capability offset. Using this instead of pci_find_capability()
1566 * reduces unnecessary search in the PCI configuration space. If you
1567 * need to calculate PCIe capability offset from raw device for some
1568 * reasons, please use pci_find_capability() instead.
1569 */
1570static inline int pci_pcie_cap(struct pci_dev *dev)
1571{
1572 return dev->pcie_cap;
1573}
1574
7eb776c4
KK		 1575/**
1576 * pci_is_pcie - check if the PCI device is PCI Express capable
1577 * @dev: PCI device
1578 *
1579 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1580 */
1581static inline bool pci_is_pcie(struct pci_dev *dev)
1582{
1583 return !!pci_pcie_cap(dev);
1584}
1585
5d990b62
CW		 1586void pci_request_acs(void);
1587
a2ce7662 1588
7ad506fa
MC		 1589#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1590#define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1591
1592/* Large Resource Data Type Tag Item Names */
1593#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1594#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1595#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1596
1597#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1598#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1599#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1600
1601/* Small Resource Data Type Tag Item Names */
1602#define PCI_VPD_STIN_END 0x78 /* End */
1603
1604#define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1605
1606#define PCI_VPD_SRDT_TIN_MASK 0x78
1607#define PCI_VPD_SRDT_LEN_MASK 0x07
1608
1609#define PCI_VPD_LRDT_TAG_SIZE 3
1610#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 1611
e1d5bdab
MC		 1612#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1613
4067a854
MC		 1614#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1615#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1616#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 1617#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 1618
a2ce7662
MC		 1619/**
1620 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1621 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1622 *
1623 * Returns the extracted Large Resource Data Type length.
1624 */
1625static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1626{
1627 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1628}
1629
7ad506fa
MC		 1630/**
1631 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1632 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1633 *
1634 * Returns the extracted Small Resource Data Type length.
1635 */
1636static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1637{
1638 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1639}
1640
e1d5bdab
MC		 1641/**
1642 * pci_vpd_info_field_size - Extracts the information field length
1643 * @lrdt: Pointer to the beginning of an information field header
1644 *
1645 * Returns the extracted information field length.
1646 */
1647static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1648{
1649 return info_field[2];
1650}
1651
b55ac1b2
MC		 1652/**
1653 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1654 * @buf: Pointer to buffered vpd data
1655 * @off: The offset into the buffer at which to begin the search
1656 * @len: The length of the vpd buffer
1657 * @rdt: The Resource Data Type to search for
1658 *
1659 * Returns the index where the Resource Data Type was found or
1660 * -ENOENT otherwise.
1661 */
1662int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1663
4067a854
MC		 1664/**
1665 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1666 * @buf: Pointer to buffered vpd data
1667 * @off: The offset into the buffer at which to begin the search
1668 * @len: The length of the buffer area, relative to off, in which to search
1669 * @kw: The keyword to search for
1670 *
1671 * Returns the index where the information field keyword was found or
1672 * -ENOENT otherwise.
1673 */
1674int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1675 unsigned int len, const char *kw);
1676
98d9f30c
BH		 1677/* PCI <-> OF binding helpers */
1678#ifdef CONFIG_OF
1679struct device_node;
1680extern void pci_set_of_node(struct pci_dev *dev);
1681extern void pci_release_of_node(struct pci_dev *dev);
1682extern void pci_set_bus_of_node(struct pci_bus *bus);
1683extern void pci_release_bus_of_node(struct pci_bus *bus);
1684
1685/* Arch may override this (weak) */
1686extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1687
64099d98
BH		 1688static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1689{
1690 return pdev ? pdev->dev.of_node : NULL;
1691}
1692
ef3b4f8c
BH		 1693static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1694{
1695 return bus ? bus->dev.of_node : NULL;
1696}
1697
98d9f30c
BH		 1698#else /* CONFIG_OF */
1699static inline void pci_set_of_node(struct pci_dev *dev) { }
1700static inline void pci_release_of_node(struct pci_dev *dev) { }
1701static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1702static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1703#endif /* CONFIG_OF */
1704
eb740b5f
GS		 1705#ifdef CONFIG_EEH
1706static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1707{
1708 return pdev->dev.archdata.edev;
1709}
1710#endif
1711
166e9278
OBC		 1712/**
1713 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1714 * @pdev: the PCI device
1715 *
1716 * if the device is PCIE, return NULL
1717 * if the device isn't connected to a PCIe bridge (that is its parent is a
1718 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1719 * parent
1720 */
1721struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1722
1da177e4
LT		 1723#endif /* __KERNEL__ */
1724#endif /* LINUX_PCI_H */
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