]>
Commit | Line | Data |
---|---|---|
1cfe9fa0 MY |
1 | /* |
2 | * include/linux/serial_reg.h | |
3 | * | |
4 | * Copyright (C) 1992, 1994 by Theodore Ts'o. | |
93456512 MY |
5 | * |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
1cfe9fa0 MY |
7 | * |
8 | * These are the UART port assignments, expressed as offsets from the base | |
9 | * register. These assignments should hold for any serial port based on | |
10 | * a 8250, 16450, or 16550(A). | |
11 | */ | |
12 | ||
13 | #ifndef _LINUX_SERIAL_REG_H | |
14 | #define _LINUX_SERIAL_REG_H | |
15 | ||
16 | /* | |
17 | * DLAB=0 | |
18 | */ | |
19 | #define UART_RX 0 /* In: Receive buffer */ | |
20 | #define UART_TX 0 /* Out: Transmit buffer */ | |
21 | ||
22 | #define UART_IER 1 /* Out: Interrupt Enable Register */ | |
23 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
24 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
25 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
26 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
27 | /* | |
28 | * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1 | |
29 | */ | |
30 | #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ | |
31 | ||
32 | #define UART_IIR 2 /* In: Interrupt ID Register */ | |
33 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
34 | #define UART_IIR_ID 0x0e /* Mask for the interrupt ID */ | |
35 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
36 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
37 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
38 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
39 | ||
40 | #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */ | |
41 | ||
42 | #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */ | |
43 | #define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */ | |
44 | #define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */ | |
45 | ||
46 | #define UART_FCR 2 /* Out: FIFO Control Register */ | |
47 | #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ | |
48 | #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ | |
49 | #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ | |
50 | #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ | |
51 | /* | |
52 | * Note: The FIFO trigger levels are chip specific: | |
53 | * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 | |
54 | * PC16550D: 1 4 8 14 xx xx xx xx | |
55 | * TI16C550A: 1 4 8 14 xx xx xx xx | |
56 | * TI16C550C: 1 4 8 14 xx xx xx xx | |
57 | * ST16C550: 1 4 8 14 xx xx xx xx | |
58 | * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 | |
59 | * NS16C552: 1 4 8 14 xx xx xx xx | |
60 | * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 | |
61 | * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 | |
62 | * TI16C752: 8 16 56 60 8 16 32 56 | |
63 | * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA | |
64 | */ | |
65 | #define UART_FCR_R_TRIG_00 0x00 | |
66 | #define UART_FCR_R_TRIG_01 0x40 | |
67 | #define UART_FCR_R_TRIG_10 0x80 | |
68 | #define UART_FCR_R_TRIG_11 0xc0 | |
69 | #define UART_FCR_T_TRIG_00 0x00 | |
70 | #define UART_FCR_T_TRIG_01 0x10 | |
71 | #define UART_FCR_T_TRIG_10 0x20 | |
72 | #define UART_FCR_T_TRIG_11 0x30 | |
73 | ||
74 | #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ | |
75 | #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ | |
76 | #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ | |
77 | #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ | |
78 | #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ | |
79 | /* 16650 definitions */ | |
80 | #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ | |
81 | #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ | |
82 | #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ | |
83 | #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ | |
84 | #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ | |
85 | #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ | |
86 | #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ | |
87 | #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ | |
88 | #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ | |
89 | ||
90 | #define UART_LCR 3 /* Out: Line Control Register */ | |
91 | /* | |
92 | * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting | |
93 | * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. | |
94 | */ | |
95 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
96 | #define UART_LCR_SBC 0x40 /* Set break control */ | |
97 | #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ | |
98 | #define UART_LCR_EPAR 0x10 /* Even parity select */ | |
99 | #define UART_LCR_PARITY 0x08 /* Parity Enable */ | |
100 | #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ | |
101 | #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ | |
102 | #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ | |
103 | #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ | |
104 | #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ | |
105 | ||
106 | /* | |
107 | * Access to some registers depends on register access / configuration | |
108 | * mode. | |
109 | */ | |
110 | #define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ | |
111 | #define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ | |
112 | ||
113 | #define UART_MCR 4 /* Out: Modem Control Register */ | |
114 | #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ | |
115 | #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ | |
116 | #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ | |
117 | #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ | |
118 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
119 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
120 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
121 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
122 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
123 | ||
124 | #define UART_LSR 5 /* In: Line Status Register */ | |
125 | #define UART_LSR_FIFOE 0x80 /* Fifo error */ | |
126 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
127 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
128 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
129 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
130 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
131 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
132 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
133 | #define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ | |
134 | ||
135 | #define UART_MSR 6 /* In: Modem Status Register */ | |
136 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
137 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
138 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
139 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
140 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
141 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
142 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
143 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
144 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
145 | ||
146 | #define UART_SCR 7 /* I/O: Scratch Register */ | |
147 | ||
148 | /* | |
149 | * DLAB=1 | |
150 | */ | |
151 | #define UART_DLL 0 /* Out: Divisor Latch Low */ | |
152 | #define UART_DLM 1 /* Out: Divisor Latch High */ | |
153 | ||
154 | /* | |
155 | * LCR=0xBF (or DLAB=1 for 16C660) | |
156 | */ | |
157 | #define UART_EFR 2 /* I/O: Extended Features Register */ | |
158 | #define UART_XR_EFR 9 /* I/O: Extended Features Register (XR17D15x) */ | |
159 | #define UART_EFR_CTS 0x80 /* CTS flow control */ | |
160 | #define UART_EFR_RTS 0x40 /* RTS flow control */ | |
161 | #define UART_EFR_SCD 0x20 /* Special character detect */ | |
162 | #define UART_EFR_ECB 0x10 /* Enhanced control bit */ | |
163 | /* | |
164 | * the low four bits control software flow control | |
165 | */ | |
166 | ||
167 | /* | |
168 | * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654 | |
169 | */ | |
170 | #define UART_XON1 4 /* I/O: Xon character 1 */ | |
171 | #define UART_XON2 5 /* I/O: Xon character 2 */ | |
172 | #define UART_XOFF1 6 /* I/O: Xoff character 1 */ | |
173 | #define UART_XOFF2 7 /* I/O: Xoff character 2 */ | |
174 | ||
175 | /* | |
176 | * EFR[4]=1 MCR[6]=1, TI16C752 | |
177 | */ | |
178 | #define UART_TI752_TCR 6 /* I/O: transmission control register */ | |
179 | #define UART_TI752_TLR 7 /* I/O: trigger level register */ | |
180 | ||
181 | /* | |
182 | * LCR=0xBF, XR16C85x | |
183 | */ | |
184 | #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx | |
185 | * In: Fifo count | |
186 | * Out: Fifo custom trigger levels */ | |
187 | /* | |
188 | * These are the definitions for the Programmable Trigger Register | |
189 | */ | |
190 | #define UART_TRG_1 0x01 | |
191 | #define UART_TRG_4 0x04 | |
192 | #define UART_TRG_8 0x08 | |
193 | #define UART_TRG_16 0x10 | |
194 | #define UART_TRG_32 0x20 | |
195 | #define UART_TRG_64 0x40 | |
196 | #define UART_TRG_96 0x60 | |
197 | #define UART_TRG_120 0x78 | |
198 | #define UART_TRG_128 0x80 | |
199 | ||
200 | #define UART_FCTR 1 /* Feature Control Register */ | |
201 | #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ | |
202 | #define UART_FCTR_RTS_4DELAY 0x01 | |
203 | #define UART_FCTR_RTS_6DELAY 0x02 | |
204 | #define UART_FCTR_RTS_8DELAY 0x03 | |
205 | #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ | |
206 | #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ | |
207 | #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ | |
208 | #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ | |
209 | #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ | |
210 | #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ | |
211 | #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ | |
212 | #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ | |
213 | #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ | |
214 | ||
215 | /* | |
216 | * LCR=0xBF, FCTR[6]=1 | |
217 | */ | |
218 | #define UART_EMSR 7 /* Extended Mode Select Register */ | |
219 | #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ | |
220 | #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ | |
221 | ||
222 | /* | |
223 | * The Intel XScale on-chip UARTs define these bits | |
224 | */ | |
225 | #define UART_IER_DMAE 0x80 /* DMA Requests Enable */ | |
226 | #define UART_IER_UUE 0x40 /* UART Unit Enable */ | |
227 | #define UART_IER_NRZE 0x20 /* NRZ coding Enable */ | |
228 | #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */ | |
229 | ||
230 | #define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */ | |
231 | ||
232 | #define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */ | |
233 | #define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */ | |
234 | #define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */ | |
235 | #define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */ | |
236 | ||
237 | /* | |
238 | * Intel MID on-chip HSU (High Speed UART) defined bits | |
239 | */ | |
240 | #define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */ | |
241 | #define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */ | |
242 | #define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */ | |
243 | #define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */ | |
244 | ||
245 | #define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */ | |
246 | #define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */ | |
247 | #define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */ | |
248 | #define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */ | |
249 | ||
250 | #define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */ | |
251 | #define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */ | |
252 | ||
253 | #define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */ | |
254 | #define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */ | |
255 | ||
256 | /* | |
257 | * These register definitions are for the 16C950 | |
258 | */ | |
259 | #define UART_ASR 0x01 /* Additional Status Register */ | |
260 | #define UART_RFL 0x03 /* Receiver FIFO level */ | |
261 | #define UART_TFL 0x04 /* Transmitter FIFO level */ | |
262 | #define UART_ICR 0x05 /* Index Control Register */ | |
263 | ||
264 | /* The 16950 ICR registers */ | |
265 | #define UART_ACR 0x00 /* Additional Control Register */ | |
266 | #define UART_CPR 0x01 /* Clock Prescalar Register */ | |
267 | #define UART_TCR 0x02 /* Times Clock Register */ | |
268 | #define UART_CKS 0x03 /* Clock Select Register */ | |
269 | #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ | |
270 | #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ | |
271 | #define UART_FCL 0x06 /* Flow Control Level Lower */ | |
272 | #define UART_FCH 0x07 /* Flow Control Level Higher */ | |
273 | #define UART_ID1 0x08 /* ID #1 */ | |
274 | #define UART_ID2 0x09 /* ID #2 */ | |
275 | #define UART_ID3 0x0A /* ID #3 */ | |
276 | #define UART_REV 0x0B /* Revision */ | |
277 | #define UART_CSR 0x0C /* Channel Software Reset */ | |
278 | #define UART_NMR 0x0D /* Nine-bit Mode Register */ | |
279 | #define UART_CTR 0xFF | |
280 | ||
281 | /* | |
282 | * The 16C950 Additional Control Register | |
283 | */ | |
284 | #define UART_ACR_RXDIS 0x01 /* Receiver disable */ | |
285 | #define UART_ACR_TXDIS 0x02 /* Transmitter disable */ | |
286 | #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ | |
287 | #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ | |
288 | #define UART_ACR_ICRRD 0x40 /* ICR Read enable */ | |
289 | #define UART_ACR_ASREN 0x80 /* Additional status enable */ | |
290 | ||
291 | ||
292 | ||
293 | /* | |
294 | * These definitions are for the RSA-DV II/S card, from | |
295 | * | |
296 | * Kiyokazu SUTO <suto@ks-and-ks.ne.jp> | |
297 | */ | |
298 | ||
299 | #define UART_RSA_BASE (-8) | |
300 | ||
301 | #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ | |
302 | ||
303 | #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ | |
304 | #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ | |
305 | #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ | |
306 | #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ | |
307 | ||
308 | #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ | |
309 | ||
310 | #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ | |
311 | #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ | |
312 | #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ | |
313 | #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ | |
314 | #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ | |
315 | ||
316 | #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ | |
317 | ||
318 | #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ | |
319 | #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ | |
320 | #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ | |
321 | #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ | |
322 | #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ | |
323 | #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ | |
324 | #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ | |
325 | #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ | |
326 | ||
327 | #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ | |
328 | ||
329 | #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ | |
330 | ||
331 | #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ | |
332 | ||
333 | #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ | |
334 | ||
335 | /* | |
336 | * The RSA DSV/II board has two fixed clock frequencies. One is the | |
337 | * standard rate, and the other is 8 times faster. | |
338 | */ | |
339 | #define SERIAL_RSA_BAUD_BASE (921600) | |
340 | #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) | |
341 | ||
342 | /* | |
343 | * Extra serial register definitions for the internal UARTs | |
344 | * in TI OMAP processors. | |
345 | */ | |
346 | #define UART_OMAP_MDR1 0x08 /* Mode definition register */ | |
347 | #define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ | |
348 | #define UART_OMAP_SCR 0x10 /* Supplementary control register */ | |
349 | #define UART_OMAP_SSR 0x11 /* Supplementary status register */ | |
350 | #define UART_OMAP_EBLR 0x12 /* BOF length register */ | |
351 | #define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ | |
352 | #define UART_OMAP_MVER 0x14 /* Module version register */ | |
353 | #define UART_OMAP_SYSC 0x15 /* System configuration register */ | |
354 | #define UART_OMAP_SYSS 0x16 /* System status register */ | |
355 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ | |
356 | ||
357 | /* | |
358 | * These are the definitions for the MDR1 register | |
359 | */ | |
360 | #define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ | |
361 | #define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ | |
362 | #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ | |
363 | #define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ | |
364 | #define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ | |
365 | #define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ | |
366 | #define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ | |
367 | #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ | |
368 | ||
369 | /* | |
370 | * These are definitions for the Exar XR17V35X and XR17(C|D)15X | |
371 | */ | |
372 | #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ | |
373 | #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ | |
374 | #define UART_EXAR_DVID 0x8d /* Device identification */ | |
375 | ||
376 | #define UART_EXAR_FCTR 0x08 /* Feature Control Register */ | |
377 | #define UART_FCTR_EXAR_IRDA 0x08 /* IrDa data encode select */ | |
378 | #define UART_FCTR_EXAR_485 0x10 /* Auto 485 half duplex dir ctl */ | |
379 | #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ | |
380 | #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ | |
381 | #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ | |
382 | #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ | |
383 | ||
384 | #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ | |
385 | #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ | |
386 | ||
387 | #endif /* _LINUX_SERIAL_REG_H */ | |
388 |