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[thirdparty/linux.git] / include / linux / stmmac.h
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1237a75a 1/* SPDX-License-Identifier: GPL-2.0-only */
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2/*******************************************************************************
3
4 Header file for stmmac platform data
5
6 Copyright (C) 2009 STMicroelectronics Ltd
7
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8
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10*******************************************************************************/
11
12#ifndef __STMMAC_PLATFORM_DATA
13#define __STMMAC_PLATFORM_DATA
14
57a503c6 15#include <linux/platform_device.h>
6c3282a6 16#include <linux/phylink.h>
57a503c6 17
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18#define MTL_MAX_RX_QUEUES 8
19#define MTL_MAX_TX_QUEUES 8
8fce3331 20#define STMMAC_CH_MAX 8
d976a525 21
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DS
22#define STMMAC_RX_COE_NONE 0
23#define STMMAC_RX_COE_TYPE1 1
24#define STMMAC_RX_COE_TYPE2 2
25
faeae3fa
DS
26/* Define the macros for CSR clock range parameters to be passed by
27 * platform code.
28 * This could also be configured at run time using CPU freq framework. */
29
30/* MDC Clock Selection define*/
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31#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
32#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
33#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
34#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
35#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
31cdd841 36#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/124 */
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37#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_scr_i/204 */
38#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_scr_i/324 */
faeae3fa 39
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40/* MTL algorithms identifiers */
41#define MTL_TX_ALGORITHM_WRR 0x0
42#define MTL_TX_ALGORITHM_WFQ 0x1
43#define MTL_TX_ALGORITHM_DWRR 0x2
44#define MTL_TX_ALGORITHM_SP 0x3
45#define MTL_RX_ALGORITHM_SP 0x4
46#define MTL_RX_ALGORITHM_WSP 0x5
47
19d91873 48/* RX/TX Queue Mode */
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49#define MTL_QUEUE_AVB 0x0
50#define MTL_QUEUE_DCB 0x1
d976a525 51
18f05d64 52/* The MDC clock could be set higher than the IEEE 802.3
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DS
53 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
54 * of value different than the above defined values. The resultant MDIO
55 * clock frequency of 12.5 MHz is applicable for the interfacing chips
56 * supporting higher MDC clocks.
57 * The MDC clock selection macros need to be defined for MDC clock rate
58 * of 12.5 MHz, corresponding to the following selection.
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59 */
60#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
61#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
62#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
63#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
64#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
65#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
66#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
67#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
faeae3fa 68
02582e9b 69/* AXI DMA Burst length supported */
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70#define DMA_AXI_BLEN_4 (1 << 1)
71#define DMA_AXI_BLEN_8 (1 << 2)
72#define DMA_AXI_BLEN_16 (1 << 3)
73#define DMA_AXI_BLEN_32 (1 << 4)
74#define DMA_AXI_BLEN_64 (1 << 5)
75#define DMA_AXI_BLEN_128 (1 << 6)
76#define DMA_AXI_BLEN_256 (1 << 7)
77#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
78 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
79 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
80
dea5c8ec 81struct clk;
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82struct stmmac_priv;
83
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84/* Platfrom data for platform device structure's platform_data field */
85
86struct stmmac_mdio_bus_data {
36bcfe7d 87 unsigned int phy_mask;
351066ba 88 unsigned int pcs_mask;
83f55b01 89 unsigned int default_an_inband;
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GC
90 int *irqs;
91 int probed_phy_irq;
1a981c05 92 bool needs_reset;
36bcfe7d 93};
3c9732c0 94
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95struct stmmac_dma_cfg {
96 int pbl;
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97 int txpbl;
98 int rxpbl;
4022d039 99 bool pblx8;
8327eb65 100 int fixed_burst;
b9cde0a8 101 int mixed_burst;
afea0365 102 bool aal;
968a2978 103 bool eame;
6ccf12ae 104 bool multi_msi_en;
96874c61 105 bool dche;
12dbc67c 106 bool atds;
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GC
107};
108
109#define AXI_BLEN 7
110struct stmmac_axi {
111 bool axi_lpi_en;
112 bool axi_xit_frm;
113 u32 axi_wr_osr_lmt;
114 u32 axi_rd_osr_lmt;
115 bool axi_kbbe;
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116 u32 axi_blen[AXI_BLEN];
117 bool axi_fb;
118 bool axi_mb;
119 bool axi_rb;
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120};
121
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122struct stmmac_rxq_cfg {
123 u8 mode_to_use;
e73b49eb 124 u32 chan;
abe80fdc 125 u8 pkt_route;
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126 bool use_prio;
127 u32 prio;
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128};
129
130struct stmmac_txq_cfg {
e73b49eb 131 u32 weight;
8452a05b 132 bool coe_unsupported;
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133 u8 mode_to_use;
134 /* Credit Base Shaper parameters */
135 u32 send_slope;
136 u32 idle_slope;
137 u32 high_credit;
138 u32 low_credit;
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139 bool use_prio;
140 u32 prio;
579a25a8 141 int tbs_en;
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142};
143
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144struct stmmac_safety_feature_cfg {
145 u32 tsoee;
146 u32 mrxpee;
147 u32 mestee;
148 u32 mrxee;
149 u32 mtxee;
150 u32 epsi;
151 u32 edpp;
152 u32 prtyen;
153 u32 tmouten;
154};
155
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156/* Addresses that may be customized by a platform */
157struct dwmac4_addrs {
158 u32 dma_chan;
159 u32 dma_chan_offset;
160 u32 mtl_chan;
161 u32 mtl_chan_offset;
162 u32 mtl_ets_ctrl;
163 u32 mtl_ets_ctrl_offset;
164 u32 mtl_txq_weight;
165 u32 mtl_txq_weight_offset;
166 u32 mtl_send_slp_cred;
167 u32 mtl_send_slp_cred_offset;
168 u32 mtl_high_cred;
169 u32 mtl_high_cred_offset;
170 u32 mtl_low_cred;
171 u32 mtl_low_cred_offset;
172};
173
d26979f1 174#define STMMAC_FLAG_HAS_INTEGRATED_PCS BIT(0)
309efe6e 175#define STMMAC_FLAG_SPH_DISABLE BIT(1)
fd1d62d8 176#define STMMAC_FLAG_USE_PHY_WOL BIT(2)
d8daff28 177#define STMMAC_FLAG_HAS_SUN8I BIT(3)
68861a3b 178#define STMMAC_FLAG_TSO_EN BIT(4)
efe92571 179#define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP BIT(5)
fc02152b 180#define STMMAC_FLAG_VLAN_FAIL_Q_EN BIT(6)
956c3f09 181#define STMMAC_FLAG_MULTI_MSI_EN BIT(7)
aa5513f5 182#define STMMAC_FLAG_EXT_SNAPSHOT_EN BIT(8)
621ba7ad 183#define STMMAC_FLAG_INT_SNAPSHOT_EN BIT(9)
743dd1db 184#define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI BIT(10)
9d0c0d5e 185#define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING BIT(11)
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186#define STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP BIT(12)
187#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(13)
d26979f1 188
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189struct plat_stmmacenet_data {
190 int bus_id;
36bcfe7d 191 int phy_addr;
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192 /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
193 * ^ ^
194 * mac_interface phy_interface
195 *
196 * mac_interface is the MAC-side interface, which may be the same
197 * as phy_interface if there is no intervening PCS. If there is a
198 * PCS, then mac_interface describes the interface mode between the
199 * MAC and PCS, and phy_interface describes the interface mode
200 * between the PCS and PHY.
201 */
202 phy_interface_t mac_interface;
203 /* phy_interface is the PHY-side interface - the interface used by
204 * an attached PHY.
205 */
0c65b2b9 206 phy_interface_t phy_interface;
36bcfe7d 207 struct stmmac_mdio_bus_data *mdio_bus_data;
5790cf3c 208 struct device_node *phy_node;
e80af2ac 209 struct fwnode_handle *port_node;
a7657f12 210 struct device_node *mdio_node;
8327eb65 211 struct stmmac_dma_cfg *dma_cfg;
5ac712dc 212 struct stmmac_safety_feature_cfg *safety_feat_cfg;
dfb8fb96 213 int clk_csr;
3c9732c0 214 int has_gmac;
e326e850 215 int enh_desc;
ebbb293f 216 int tx_coe;
55f9a4d6 217 int rx_coe;
ebbb293f 218 int bugged_jumbo;
543876c9 219 int pmt;
61b8013a 220 int force_sf_dma_mode;
e2a240c7 221 int force_thresh_dma_mode;
62a2ab93 222 int riwt_off;
9cbadf09 223 int max_speed;
2618abb7 224 int maxmtu;
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225 int multicast_filter_bins;
226 int unicast_filter_entries;
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227 int tx_fifo_size;
228 int rx_fifo_size;
070246e4 229 u32 host_dma_width;
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230 u32 rx_queues_to_use;
231 u32 tx_queues_to_use;
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232 u8 rx_sched_algorithm;
233 u8 tx_sched_algorithm;
234 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
235 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
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236 void (*get_interfaces)(struct stmmac_priv *priv, void *bsp_priv,
237 unsigned long *interfaces);
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238 int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i,
239 phy_interface_t interface, int speed);
ac9a8587 240 void (*fix_mac_speed)(void *priv, int speed, unsigned int mode);
10739ea3 241 int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
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242 int (*serdes_powerup)(struct net_device *ndev, void *priv);
243 void (*serdes_powerdown)(struct net_device *ndev, void *priv);
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244 int (*mac_finish)(struct net_device *ndev,
245 void *priv,
246 unsigned int mode,
247 phy_interface_t interface);
d928d14b 248 void (*ptp_clk_freq_config)(struct stmmac_priv *priv);
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249 int (*init)(struct platform_device *pdev, void *priv);
250 void (*exit)(struct platform_device *pdev, void *priv);
ec33d71d 251 struct mac_device_info *(*setup)(void *priv);
b4d45aee 252 int (*clks_config)(void *priv, bool enabled);
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253 int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
254 void *ctx);
4047b9db 255 void (*dump_debug_regs)(void *priv);
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256 int (*pcs_init)(struct stmmac_priv *priv);
257 void (*pcs_exit)(struct stmmac_priv *priv);
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258 struct phylink_pcs *(*select_pcs)(struct stmmac_priv *priv,
259 phy_interface_t interface);
3c9732c0 260 void *bsp_priv;
f573c0b9 261 struct clk *stmmac_clk;
262 struct clk *pclk;
263 struct clk *clk_ptp_ref;
dea5c8ec 264 struct clk *clk_tx_i; /* clk_tx_i to MAC core */
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JPO
265 unsigned long clk_ptp_rate;
266 unsigned long clk_ref_rate;
a045e406
S
267 struct clk_bulk_data *clks;
268 int num_clks;
e80fe71b 269 unsigned int mult_fact_100ns;
190f73ab 270 s32 ptp_max_adj;
c6d5f193 271 u32 cdc_error_adj;
f573c0b9 272 struct reset_control *stmmac_rst;
e67f325e 273 struct reset_control *stmmac_ahb_rst;
afea0365 274 struct stmmac_axi *axi;
ee2ae1ed 275 int has_gmac4;
76067459 276 int rss_en;
02e57b9d 277 int mac_port_sel_speed;
48ae5554 278 int has_xgmac;
e0f9956a 279 u8 vlan_fail_q;
20e07e2c 280 struct pci_dev *pdev;
341f67e4 281 int int_snapshot_num;
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282 int msi_mac_vec;
283 int msi_wol_vec;
284 int msi_lpi_vec;
285 int msi_sfty_ce_vec;
286 int msi_sfty_ue_vec;
287 int msi_rx_base_vec;
288 int msi_tx_base_vec;
33719b57 289 const struct dwmac4_addrs *dwmac4_addrs;
d26979f1 290 unsigned int flags;
3c9732c0 291};
3c9732c0 292#endif