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787f4f30 FE |
1 | /* |
2 | * (C) Copyright 2012 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
787f4f30 FE |
5 | */ |
6 | ||
7 | #ifndef __MC34704_H__ | |
8 | #define __MC34704_H__ | |
9 | ||
10 | enum { | |
11 | MC34704_RESERVED0_REG = 0, /* 0x00 */ | |
12 | MC34704_GENERAL1_REG, /* 0x01 */ | |
13 | MC34704_GENERAL2_REG, /* 0x02 */ | |
14 | MC34704_GENERAL3_REG, /* 0x03 */ | |
15 | MC34704_RESERVED4_REG, /* 0x04 */ | |
16 | MC34704_VGSET2_REG, /* 0x05 */ | |
17 | MC34704_REG2SET1_REG, /* 0x06 */ | |
18 | MC34704_REG2SET2_REG, /* 0x07 */ | |
19 | MC34704_REG3SET1_REG, /* 0x08 */ | |
20 | MC34704_REG3SET2_REG, /* 0x09 */ | |
21 | MC34704_REG4SET1_REG, /* 0x0a */ | |
22 | MC34704_REG4SET2_REG, /* 0x0b */ | |
23 | MC34704_REG5SET1_REG, /* 0x0c */ | |
24 | MC34704_REG5SET2_REG, /* 0x0d */ | |
25 | MC34704_REG5SET3_REG, /* 0x0e */ | |
26 | MC34704_RESERVEDF_REG, /* 0x0f */ | |
27 | MC34704_RESERVED10_REG, /* 0x10 */ | |
28 | MC34704_RESERVED11_REG, /* 0x11 */ | |
29 | MC34704_RESERVED12_REG, /* 0x12 */ | |
30 | MC34704_FSW2SET_REG, /* 0x13 */ | |
31 | MC34704_RESERVED14_REG, /* 0x14 */ | |
32 | MC34704_REG8SET1_REG, /* 0x15 */ | |
33 | MC34704_REG8SET2_REG, /* 0x16 */ | |
34 | MC34704_REG8SET3_REG, /* 0x17 */ | |
35 | MC34704_FAULTS_REG, /* 0x18 */ | |
36 | MC34704_I2CSET1, /* 0x19 */ | |
37 | MC34704_NUM_OF_REGS, | |
38 | }; | |
39 | ||
40 | /* GENERAL2 register fields */ | |
41 | #define ONOFFE (1 << 0) | |
42 | #define ONOFFD (1 << 1) | |
bcc5ea24 | 43 | #define ONOFFA (1 << 3) |
787f4f30 FE |
44 | #define ALLOFF (1 << 4) |
45 | ||
46 | #endif /* __MC34704_H__ */ |