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Commit | Line | Data |
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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
f046ccd1 | 2 | /* |
7c619ddc | 3 | * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc. |
f046ccd1 EL |
4 | */ |
5 | ||
f046ccd1 EL |
6 | #ifndef __MPC83XX_H__ |
7 | #define __MPC83XX_H__ | |
8 | ||
9 | #if defined(CONFIG_E300) | |
10 | #include <asm/e300.h> | |
11 | #endif | |
12 | ||
4e8b750c HS |
13 | /* |
14 | * System reset offset (PowerPC standard) | |
f046ccd1 | 15 | */ |
e080313c | 16 | #define EXC_OFF_SYS_RESET 0x0100 |
02032e8f | 17 | #define _START_OFFSET EXC_OFF_SYS_RESET |
f046ccd1 | 18 | |
4e8b750c HS |
19 | /* |
20 | * IMMRBAR - Internal Memory Register Base Address | |
f046ccd1 | 21 | */ |
4e8b750c HS |
22 | /* Register offset to immr */ |
23 | #define IMMRBAR 0x0000 | |
24 | #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */ | |
e080313c | 25 | #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) |
f046ccd1 | 26 | |
4e8b750c HS |
27 | /* |
28 | * LAWBAR - Local Access Window Base Address Register | |
f046ccd1 | 29 | */ |
4e8b750c HS |
30 | /* Register offset to immr */ |
31 | #define LBLAWBAR0 0x0020 | |
e080313c DL |
32 | #define LBLAWAR0 0x0024 |
33 | #define LBLAWBAR1 0x0028 | |
34 | #define LBLAWAR1 0x002C | |
35 | #define LBLAWBAR2 0x0030 | |
36 | #define LBLAWAR2 0x0034 | |
37 | #define LBLAWBAR3 0x0038 | |
38 | #define LBLAWAR3 0x003C | |
4e8b750c | 39 | #define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */ |
e080313c | 40 | |
4e8b750c HS |
41 | /* |
42 | * SPRIDR - System Part and Revision ID Register | |
e080313c | 43 | */ |
e5c4ade4 KP |
44 | #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ |
45 | #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ | |
e080313c | 46 | |
d5cfa4aa | 47 | #if defined(CONFIG_ARCH_MPC834X) |
e5c4ade4 KP |
48 | #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) |
49 | #define REVID_MINOR(spridr) (spridr & 0x000000FF) | |
50 | #else | |
51 | #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) | |
52 | #define REVID_MINOR(spridr) (spridr & 0x0000000F) | |
53 | #endif | |
03051c3d | 54 | |
e5c4ade4 | 55 | #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) |
6b70ffb9 | 56 | #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) |
e5c4ade4 | 57 | |
7c619ddc | 58 | #define SPR_8308 0x8100 |
a88731a6 | 59 | #define SPR_8309 0x8110 |
6b70ffb9 | 60 | #define SPR_831X_FAMILY 0x80B |
e5c4ade4 KP |
61 | #define SPR_8311 0x80B2 |
62 | #define SPR_8313 0x80B0 | |
63 | #define SPR_8314 0x80B6 | |
64 | #define SPR_8315 0x80B4 | |
6b70ffb9 | 65 | #define SPR_832X_FAMILY 0x806 |
e5c4ade4 KP |
66 | #define SPR_8321 0x8066 |
67 | #define SPR_8323 0x8062 | |
6b70ffb9 | 68 | #define SPR_834X_FAMILY 0x803 |
e5c4ade4 KP |
69 | #define SPR_8343 0x8036 |
70 | #define SPR_8347_TBGA_ 0x8032 | |
71 | #define SPR_8347_PBGA_ 0x8034 | |
72 | #define SPR_8349 0x8030 | |
6b70ffb9 | 73 | #define SPR_836X_FAMILY 0x804 |
e5c4ade4 KP |
74 | #define SPR_8358_TBGA_ 0x804A |
75 | #define SPR_8358_PBGA_ 0x804E | |
76 | #define SPR_8360 0x8048 | |
6b70ffb9 | 77 | #define SPR_837X_FAMILY 0x80C |
e5c4ade4 KP |
78 | #define SPR_8377 0x80C6 |
79 | #define SPR_8378 0x80C4 | |
80 | #define SPR_8379 0x80C2 | |
d87c57b2 | 81 | |
4e8b750c HS |
82 | /* |
83 | * SPCR - System Priority Configuration Register | |
e080313c | 84 | */ |
4e8b750c HS |
85 | /* PCI Highest Priority Enable */ |
86 | #define SPCR_PCIHPE 0x10000000 | |
e080313c | 87 | #define SPCR_PCIHPE_SHIFT (31-3) |
4e8b750c HS |
88 | /* PCI bridge system bus request priority */ |
89 | #define SPCR_PCIPR 0x03000000 | |
e080313c DL |
90 | #define SPCR_PCIPR_SHIFT (31-7) |
91 | #define SPCR_OPT 0x00800000 /* Optimize */ | |
5bbeea86 | 92 | #define SPCR_OPT_SHIFT (31-8) |
4e8b750c HS |
93 | /* E300 PowerPC core time base unit enable */ |
94 | #define SPCR_TBEN 0x00400000 | |
e080313c | 95 | #define SPCR_TBEN_SHIFT (31-9) |
4e8b750c HS |
96 | /* E300 PowerPC Core system bus request priority */ |
97 | #define SPCR_COREPR 0x00300000 | |
e080313c DL |
98 | #define SPCR_COREPR_SHIFT (31-11) |
99 | ||
d5cfa4aa | 100 | #if defined(CONFIG_ARCH_MPC834X) |
e080313c | 101 | /* SPCR bits - MPC8349 specific */ |
4e8b750c HS |
102 | /* TSEC1 data priority */ |
103 | #define SPCR_TSEC1DP 0x00003000 | |
e080313c | 104 | #define SPCR_TSEC1DP_SHIFT (31-19) |
4e8b750c HS |
105 | /* TSEC1 buffer descriptor priority */ |
106 | #define SPCR_TSEC1BDP 0x00000C00 | |
e080313c | 107 | #define SPCR_TSEC1BDP_SHIFT (31-21) |
4e8b750c HS |
108 | /* TSEC1 emergency priority */ |
109 | #define SPCR_TSEC1EP 0x00000300 | |
e080313c | 110 | #define SPCR_TSEC1EP_SHIFT (31-23) |
4e8b750c HS |
111 | /* TSEC2 data priority */ |
112 | #define SPCR_TSEC2DP 0x00000030 | |
e080313c | 113 | #define SPCR_TSEC2DP_SHIFT (31-27) |
4e8b750c HS |
114 | /* TSEC2 buffer descriptor priority */ |
115 | #define SPCR_TSEC2BDP 0x0000000C | |
e080313c | 116 | #define SPCR_TSEC2BDP_SHIFT (31-29) |
4e8b750c HS |
117 | /* TSEC2 emergency priority */ |
118 | #define SPCR_TSEC2EP 0x00000003 | |
e080313c | 119 | #define SPCR_TSEC2EP_SHIFT (31-31) |
d87c57b2 | 120 | |
9403fc41 | 121 | #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ |
8439e99d MS |
122 | defined(CONFIG_ARCH_MPC837X) |
123 | /* SPCR bits - MPC8308, MPC831x and MPC837X specific */ | |
4e8b750c HS |
124 | /* TSEC data priority */ |
125 | #define SPCR_TSECDP 0x00003000 | |
d87c57b2 | 126 | #define SPCR_TSECDP_SHIFT (31-19) |
4e8b750c HS |
127 | /* TSEC buffer descriptor priority */ |
128 | #define SPCR_TSECBDP 0x00000C00 | |
ec2638ea | 129 | #define SPCR_TSECBDP_SHIFT (31-21) |
4e8b750c HS |
130 | /* TSEC emergency priority */ |
131 | #define SPCR_TSECEP 0x00000300 | |
ec2638ea | 132 | #define SPCR_TSECEP_SHIFT (31-23) |
e080313c | 133 | #endif |
f046ccd1 | 134 | |
e080313c DL |
135 | /* SICRL/H - System I/O Configuration Register Low/High |
136 | */ | |
d5cfa4aa | 137 | #if defined(CONFIG_ARCH_MPC834X) |
e080313c DL |
138 | /* SICRL bits - MPC8349 specific */ |
139 | #define SICRL_LDP_A 0x80000000 | |
140 | #define SICRL_USB1 0x40000000 | |
141 | #define SICRL_USB0 0x20000000 | |
142 | #define SICRL_UART 0x0C000000 | |
143 | #define SICRL_GPIO1_A 0x02000000 | |
144 | #define SICRL_GPIO1_B 0x01000000 | |
145 | #define SICRL_GPIO1_C 0x00800000 | |
146 | #define SICRL_GPIO1_D 0x00400000 | |
147 | #define SICRL_GPIO1_E 0x00200000 | |
148 | #define SICRL_GPIO1_F 0x00180000 | |
149 | #define SICRL_GPIO1_G 0x00040000 | |
150 | #define SICRL_GPIO1_H 0x00020000 | |
151 | #define SICRL_GPIO1_I 0x00010000 | |
152 | #define SICRL_GPIO1_J 0x00008000 | |
153 | #define SICRL_GPIO1_K 0x00004000 | |
154 | #define SICRL_GPIO1_L 0x00003000 | |
155 | ||
156 | /* SICRH bits - MPC8349 specific */ | |
157 | #define SICRH_DDR 0x80000000 | |
158 | #define SICRH_TSEC1_A 0x10000000 | |
159 | #define SICRH_TSEC1_B 0x08000000 | |
160 | #define SICRH_TSEC1_C 0x04000000 | |
161 | #define SICRH_TSEC1_D 0x02000000 | |
162 | #define SICRH_TSEC1_E 0x01000000 | |
163 | #define SICRH_TSEC1_F 0x00800000 | |
164 | #define SICRH_TSEC2_A 0x00400000 | |
165 | #define SICRH_TSEC2_B 0x00200000 | |
166 | #define SICRH_TSEC2_C 0x00100000 | |
167 | #define SICRH_TSEC2_D 0x00080000 | |
168 | #define SICRH_TSEC2_E 0x00040000 | |
169 | #define SICRH_TSEC2_F 0x00020000 | |
170 | #define SICRH_TSEC2_G 0x00010000 | |
171 | #define SICRH_TSEC2_H 0x00008000 | |
172 | #define SICRH_GPIO2_A 0x00004000 | |
173 | #define SICRH_GPIO2_B 0x00002000 | |
174 | #define SICRH_GPIO2_C 0x00001000 | |
175 | #define SICRH_GPIO2_D 0x00000800 | |
176 | #define SICRH_GPIO2_E 0x00000400 | |
177 | #define SICRH_GPIO2_F 0x00000200 | |
178 | #define SICRH_GPIO2_G 0x00000180 | |
179 | #define SICRH_GPIO2_H 0x00000060 | |
180 | #define SICRH_TSOBI1 0x00000002 | |
181 | #define SICRH_TSOBI2 0x00000001 | |
182 | ||
61abced7 | 183 | #elif defined(CONFIG_ARCH_MPC8360) |
e080313c DL |
184 | /* SICRL bits - MPC8360 specific */ |
185 | #define SICRL_LDP_A 0xC0000000 | |
186 | #define SICRL_LCLK_1 0x10000000 | |
187 | #define SICRL_LCLK_2 0x08000000 | |
188 | #define SICRL_SRCID_A 0x03000000 | |
189 | #define SICRL_IRQ_CKSTP_A 0x00C00000 | |
190 | ||
191 | /* SICRH bits - MPC8360 specific */ | |
192 | #define SICRH_DDR 0x80000000 | |
193 | #define SICRH_SECONDARY_DDR 0x40000000 | |
194 | #define SICRH_SDDROE 0x20000000 | |
195 | #define SICRH_IRQ3 0x10000000 | |
196 | #define SICRH_UC1EOBI 0x00000004 | |
197 | #define SICRH_UC2E1OBI 0x00000002 | |
198 | #define SICRH_UC2E2OBI 0x00000001 | |
24c3aca3 | 199 | |
bd3b867e | 200 | #elif defined(CONFIG_ARCH_MPC832X) |
2c7920af | 201 | /* SICRL bits - MPC832x specific */ |
24c3aca3 DL |
202 | #define SICRL_LDP_LCS_A 0x80000000 |
203 | #define SICRL_IRQ_CKS 0x20000000 | |
204 | #define SICRL_PCI_MSRC 0x10000000 | |
205 | #define SICRL_URT_CTPR 0x06000000 | |
206 | #define SICRL_IRQ_CTPR 0x00C00000 | |
d87c57b2 | 207 | |
9403fc41 | 208 | #elif defined(CONFIG_ARCH_MPC8313) |
555da617 | 209 | /* SICRL bits - MPC8313 specific */ |
d87c57b2 SW |
210 | #define SICRL_LBC 0x30000000 |
211 | #define SICRL_UART 0x0C000000 | |
212 | #define SICRL_SPI_A 0x03000000 | |
213 | #define SICRL_SPI_B 0x00C00000 | |
214 | #define SICRL_SPI_C 0x00300000 | |
215 | #define SICRL_SPI_D 0x000C0000 | |
f986325d RM |
216 | #define SICRL_USBDR_11 0x00000C00 |
217 | #define SICRL_USBDR_10 0x00000800 | |
218 | #define SICRL_USBDR_01 0x00000400 | |
219 | #define SICRL_USBDR_00 0x00000000 | |
d87c57b2 SW |
220 | #define SICRL_ETSEC1_A 0x0000000C |
221 | #define SICRL_ETSEC2_A 0x00000003 | |
222 | ||
555da617 | 223 | /* SICRH bits - MPC8313 specific */ |
d87c57b2 SW |
224 | #define SICRH_INTR_A 0x02000000 |
225 | #define SICRH_INTR_B 0x00C00000 | |
226 | #define SICRH_IIC 0x00300000 | |
227 | #define SICRH_ETSEC2_B 0x000C0000 | |
228 | #define SICRH_ETSEC2_C 0x00030000 | |
229 | #define SICRH_ETSEC2_D 0x0000C000 | |
230 | #define SICRH_ETSEC2_E 0x00003000 | |
231 | #define SICRH_ETSEC2_F 0x00000C00 | |
232 | #define SICRH_ETSEC2_G 0x00000300 | |
233 | #define SICRH_ETSEC1_B 0x00000080 | |
234 | #define SICRH_ETSEC1_C 0x00000060 | |
235 | #define SICRH_GTX1_DLY 0x00000008 | |
236 | #define SICRH_GTX2_DLY 0x00000004 | |
237 | #define SICRH_TSOBI1 0x00000002 | |
238 | #define SICRH_TSOBI2 0x00000001 | |
239 | ||
8439e99d MS |
240 | #elif defined(CONFIG_ARCH_MPC837X) |
241 | /* SICRL bits - MPC837X specific */ | |
03051c3d DL |
242 | #define SICRL_USB_A 0xC0000000 |
243 | #define SICRL_USB_B 0x30000000 | |
e1ac387f | 244 | #define SICRL_USB_B_SD 0x20000000 |
03051c3d DL |
245 | #define SICRL_UART 0x0C000000 |
246 | #define SICRL_GPIO_A 0x02000000 | |
247 | #define SICRL_GPIO_B 0x01000000 | |
248 | #define SICRL_GPIO_C 0x00800000 | |
249 | #define SICRL_GPIO_D 0x00400000 | |
250 | #define SICRL_GPIO_E 0x00200000 | |
251 | #define SICRL_GPIO_F 0x00180000 | |
252 | #define SICRL_GPIO_G 0x00040000 | |
253 | #define SICRL_GPIO_H 0x00020000 | |
254 | #define SICRL_GPIO_I 0x00010000 | |
255 | #define SICRL_GPIO_J 0x00008000 | |
256 | #define SICRL_GPIO_K 0x00004000 | |
257 | #define SICRL_GPIO_L 0x00003000 | |
258 | #define SICRL_DMA_A 0x00000800 | |
259 | #define SICRL_DMA_B 0x00000400 | |
260 | #define SICRL_DMA_C 0x00000200 | |
261 | #define SICRL_DMA_D 0x00000100 | |
262 | #define SICRL_DMA_E 0x00000080 | |
263 | #define SICRL_DMA_F 0x00000040 | |
264 | #define SICRL_DMA_G 0x00000020 | |
265 | #define SICRL_DMA_H 0x00000010 | |
266 | #define SICRL_DMA_I 0x00000008 | |
267 | #define SICRL_DMA_J 0x00000004 | |
268 | #define SICRL_LDP_A 0x00000002 | |
269 | #define SICRL_LDP_B 0x00000001 | |
270 | ||
8439e99d | 271 | /* SICRH bits - MPC837X specific */ |
03051c3d DL |
272 | #define SICRH_DDR 0x80000000 |
273 | #define SICRH_TSEC1_A 0x10000000 | |
274 | #define SICRH_TSEC1_B 0x08000000 | |
275 | #define SICRH_TSEC2_A 0x00400000 | |
276 | #define SICRH_TSEC2_B 0x00200000 | |
277 | #define SICRH_TSEC2_C 0x00100000 | |
278 | #define SICRH_TSEC2_D 0x00080000 | |
279 | #define SICRH_TSEC2_E 0x00040000 | |
280 | #define SICRH_TMR 0x00010000 | |
281 | #define SICRH_GPIO2_A 0x00008000 | |
282 | #define SICRH_GPIO2_B 0x00004000 | |
283 | #define SICRH_GPIO2_C 0x00002000 | |
284 | #define SICRH_GPIO2_D 0x00001000 | |
285 | #define SICRH_GPIO2_E 0x00000C00 | |
e1ac387f | 286 | #define SICRH_GPIO2_E_SD 0x00000800 |
03051c3d DL |
287 | #define SICRH_GPIO2_F 0x00000300 |
288 | #define SICRH_GPIO2_G 0x000000C0 | |
289 | #define SICRH_GPIO2_H 0x00000030 | |
290 | #define SICRH_SPI 0x00000003 | |
e1ac387f | 291 | #define SICRH_SPI_SD 0x00000001 |
f3ce250d | 292 | |
4bc97a3b | 293 | #elif defined(CONFIG_ARCH_MPC8308) |
f3ce250d IY |
294 | /* SICRL bits - MPC8308 specific */ |
295 | #define SICRL_SPI_PF0 (0 << 28) | |
296 | #define SICRL_SPI_PF1 (1 << 28) | |
297 | #define SICRL_SPI_PF3 (3 << 28) | |
298 | #define SICRL_UART_PF0 (0 << 26) | |
299 | #define SICRL_UART_PF1 (1 << 26) | |
300 | #define SICRL_UART_PF3 (3 << 26) | |
301 | #define SICRL_IRQ_PF0 (0 << 24) | |
302 | #define SICRL_IRQ_PF1 (1 << 24) | |
303 | #define SICRL_I2C2_PF0 (0 << 20) | |
304 | #define SICRL_I2C2_PF1 (1 << 20) | |
305 | #define SICRL_ETSEC1_TX_CLK (0 << 6) | |
306 | #define SICRL_ETSEC1_GTX_CLK125 (1 << 6) | |
307 | ||
308 | /* SICRH bits - MPC8308 specific */ | |
309 | #define SICRH_ESDHC_A_SD (0 << 30) | |
310 | #define SICRH_ESDHC_A_GTM (1 << 30) | |
311 | #define SICRH_ESDHC_A_GPIO (3 << 30) | |
312 | #define SICRH_ESDHC_B_SD (0 << 28) | |
313 | #define SICRH_ESDHC_B_GTM (1 << 28) | |
314 | #define SICRH_ESDHC_B_GPIO (3 << 28) | |
315 | #define SICRH_ESDHC_C_SD (0 << 26) | |
316 | #define SICRH_ESDHC_C_GTM (1 << 26) | |
317 | #define SICRH_ESDHC_C_GPIO (3 << 26) | |
318 | #define SICRH_GPIO_A_GPIO (0 << 24) | |
319 | #define SICRH_GPIO_A_TSEC2 (1 << 24) | |
320 | #define SICRH_GPIO_B_GPIO (0 << 22) | |
321 | #define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22) | |
322 | #define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22) | |
323 | #define SICRH_IEEE1588_A_TMR (1 << 20) | |
324 | #define SICRH_IEEE1588_A_GPIO (3 << 20) | |
325 | #define SICRH_USB (1 << 18) | |
326 | #define SICRH_GTM_GTM (1 << 16) | |
327 | #define SICRH_GTM_GPIO (3 << 16) | |
328 | #define SICRH_IEEE1588_B_TMR (1 << 14) | |
329 | #define SICRH_IEEE1588_B_GPIO (3 << 14) | |
330 | #define SICRH_ETSEC2_CRS (1 << 12) | |
331 | #define SICRH_ETSEC2_GPIO (3 << 12) | |
332 | #define SICRH_GPIOSEL_0 (0 << 8) | |
333 | #define SICRH_GPIOSEL_1 (1 << 8) | |
334 | #define SICRH_TMROBI_V3P3 (0 << 4) | |
335 | #define SICRH_TMROBI_V2P5 (1 << 4) | |
336 | #define SICRH_TSOBI1_V3P3 (0 << 1) | |
337 | #define SICRH_TSOBI1_V2P5 (1 << 1) | |
338 | #define SICRH_TSOBI2_V3P3 (0 << 0) | |
339 | #define SICRH_TSOBI2_V2P5 (1 << 0) | |
a88731a6 | 340 | |
e080313c | 341 | #endif |
f046ccd1 | 342 | |
4e8b750c HS |
343 | /* |
344 | * SWCRR - System Watchdog Control Register | |
e080313c | 345 | */ |
4e8b750c HS |
346 | /* Register offset to immr */ |
347 | #define SWCRR 0x0204 | |
348 | /* Software Watchdog Time Count */ | |
349 | #define SWCRR_SWTC 0xFFFF0000 | |
350 | /* Watchdog Enable bit */ | |
351 | #define SWCRR_SWEN 0x00000004 | |
352 | /* Software Watchdog Reset/Interrupt Select bit */ | |
353 | #define SWCRR_SWRI 0x00000002 | |
354 | /* Software Watchdog Counter Prescale bit */ | |
355 | #define SWCRR_SWPR 0x00000001 | |
356 | #define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \ | |
357 | SWCRR_SWRI | SWCRR_SWPR)) | |
358 | ||
359 | /* | |
360 | * SWCNR - System Watchdog Counter Register | |
e080313c | 361 | */ |
4e8b750c HS |
362 | /* Register offset to immr */ |
363 | #define SWCNR 0x0208 | |
364 | /* Software Watchdog Count mask */ | |
365 | #define SWCNR_SWCN 0x0000FFFF | |
e080313c | 366 | #define SWCNR_RES ~(SWCNR_SWCN) |
f046ccd1 | 367 | |
4e8b750c HS |
368 | /* |
369 | * SWSRR - System Watchdog Service Register | |
f046ccd1 | 370 | */ |
4e8b750c HS |
371 | /* Register offset to immr */ |
372 | #define SWSRR 0x020E | |
f046ccd1 | 373 | |
4e8b750c HS |
374 | /* |
375 | * ACR - Arbiter Configuration Register | |
f046ccd1 | 376 | */ |
e080313c DL |
377 | #define ACR_COREDIS 0x10000000 /* Core disable */ |
378 | #define ACR_COREDIS_SHIFT (31-7) | |
379 | #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ | |
380 | #define ACR_PIPE_DEP_SHIFT (31-15) | |
381 | #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ | |
382 | #define ACR_PCI_RPTCNT_SHIFT (31-19) | |
383 | #define ACR_RPTCNT 0x00000700 /* Repeat count */ | |
384 | #define ACR_RPTCNT_SHIFT (31-23) | |
385 | #define ACR_APARK 0x00000030 /* Address parking */ | |
386 | #define ACR_APARK_SHIFT (31-27) | |
387 | #define ACR_PARKM 0x0000000F /* Parking master */ | |
388 | #define ACR_PARKM_SHIFT (31-31) | |
389 | ||
4e8b750c HS |
390 | /* |
391 | * ATR - Arbiter Timers Register | |
e080313c DL |
392 | */ |
393 | #define ATR_DTO 0x00FF0000 /* Data time out */ | |
002d27ca | 394 | #define ATR_DTO_SHIFT 16 |
e080313c | 395 | #define ATR_ATO 0x000000FF /* Address time out */ |
002d27ca | 396 | #define ATR_ATO_SHIFT 0 |
f046ccd1 | 397 | |
4e8b750c HS |
398 | /* |
399 | * AER - Arbiter Event Register | |
e080313c DL |
400 | */ |
401 | #define AER_ETEA 0x00000020 /* Transfer error */ | |
4e8b750c HS |
402 | /* Reserved transfer type */ |
403 | #define AER_RES 0x00000010 | |
404 | /* External control word transfer type */ | |
405 | #define AER_ECW 0x00000008 | |
406 | /* Address Only transfer type */ | |
407 | #define AER_AO 0x00000004 | |
e080313c DL |
408 | #define AER_DTO 0x00000002 /* Data time out */ |
409 | #define AER_ATO 0x00000001 /* Address time out */ | |
410 | ||
4e8b750c HS |
411 | /* |
412 | * AEATR - Arbiter Event Address Register | |
e080313c DL |
413 | */ |
414 | #define AEATR_EVENT 0x07000000 /* Event type */ | |
002d27ca | 415 | #define AEATR_EVENT_SHIFT 24 |
e080313c | 416 | #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ |
002d27ca | 417 | #define AEATR_MSTR_ID_SHIFT 16 |
e080313c | 418 | #define AEATR_TBST 0x00000800 /* Transfer burst */ |
002d27ca | 419 | #define AEATR_TBST_SHIFT 11 |
e080313c | 420 | #define AEATR_TSIZE 0x00000700 /* Transfer Size */ |
002d27ca | 421 | #define AEATR_TSIZE_SHIFT 8 |
e080313c | 422 | #define AEATR_TTYPE 0x0000001F /* Transfer Type */ |
002d27ca | 423 | #define AEATR_TTYPE_SHIFT 0 |
f046ccd1 | 424 | |
4e8b750c HS |
425 | /* |
426 | * HRCWL - Hard Reset Configuration Word Low | |
e080313c DL |
427 | */ |
428 | #define HRCWL_LBIUCM 0x80000000 | |
429 | #define HRCWL_LBIUCM_SHIFT 31 | |
430 | #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 | |
431 | #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 | |
432 | ||
433 | #define HRCWL_DDRCM 0x40000000 | |
434 | #define HRCWL_DDRCM_SHIFT 30 | |
435 | #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 | |
436 | #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 | |
437 | ||
438 | #define HRCWL_SPMF 0x0f000000 | |
439 | #define HRCWL_SPMF_SHIFT 24 | |
440 | #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 | |
441 | #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 | |
442 | #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 | |
443 | #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 | |
444 | #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 | |
445 | #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 | |
446 | #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 | |
447 | #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 | |
448 | #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 | |
449 | #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 | |
450 | #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 | |
451 | #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 | |
452 | #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 | |
453 | #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 | |
454 | #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 | |
455 | #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 | |
456 | ||
457 | #define HRCWL_VCO_BYPASS 0x00000000 | |
458 | #define HRCWL_VCO_1X2 0x00000000 | |
459 | #define HRCWL_VCO_1X4 0x00200000 | |
460 | #define HRCWL_VCO_1X8 0x00400000 | |
461 | ||
462 | #define HRCWL_COREPLL 0x007F0000 | |
463 | #define HRCWL_COREPLL_SHIFT 16 | |
464 | #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 | |
465 | #define HRCWL_CORE_TO_CSB_1X1 0x00020000 | |
466 | #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 | |
467 | #define HRCWL_CORE_TO_CSB_2X1 0x00040000 | |
468 | #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 | |
469 | #define HRCWL_CORE_TO_CSB_3X1 0x00060000 | |
470 | ||
61abced7 | 471 | #if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X) |
e080313c DL |
472 | #define HRCWL_CEVCOD 0x000000C0 |
473 | #define HRCWL_CEVCOD_SHIFT 6 | |
474 | #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 | |
475 | #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 | |
476 | #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 | |
477 | ||
478 | #define HRCWL_CEPDF 0x00000020 | |
479 | #define HRCWL_CEPDF_SHIFT 5 | |
480 | #define HRCWL_CE_PLL_DIV_1X1 0x00000000 | |
481 | #define HRCWL_CE_PLL_DIV_2X1 0x00000020 | |
482 | ||
483 | #define HRCWL_CEPMF 0x0000001F | |
484 | #define HRCWL_CEPMF_SHIFT 0 | |
485 | #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 | |
486 | #define HRCWL_CE_TO_PLL_1X2 0x00000002 | |
487 | #define HRCWL_CE_TO_PLL_1X3 0x00000003 | |
488 | #define HRCWL_CE_TO_PLL_1X4 0x00000004 | |
489 | #define HRCWL_CE_TO_PLL_1X5 0x00000005 | |
490 | #define HRCWL_CE_TO_PLL_1X6 0x00000006 | |
491 | #define HRCWL_CE_TO_PLL_1X7 0x00000007 | |
492 | #define HRCWL_CE_TO_PLL_1X8 0x00000008 | |
493 | #define HRCWL_CE_TO_PLL_1X9 0x00000009 | |
494 | #define HRCWL_CE_TO_PLL_1X10 0x0000000A | |
495 | #define HRCWL_CE_TO_PLL_1X11 0x0000000B | |
496 | #define HRCWL_CE_TO_PLL_1X12 0x0000000C | |
497 | #define HRCWL_CE_TO_PLL_1X13 0x0000000D | |
498 | #define HRCWL_CE_TO_PLL_1X14 0x0000000E | |
499 | #define HRCWL_CE_TO_PLL_1X15 0x0000000F | |
500 | #define HRCWL_CE_TO_PLL_1X16 0x00000010 | |
501 | #define HRCWL_CE_TO_PLL_1X17 0x00000011 | |
502 | #define HRCWL_CE_TO_PLL_1X18 0x00000012 | |
503 | #define HRCWL_CE_TO_PLL_1X19 0x00000013 | |
504 | #define HRCWL_CE_TO_PLL_1X20 0x00000014 | |
505 | #define HRCWL_CE_TO_PLL_1X21 0x00000015 | |
506 | #define HRCWL_CE_TO_PLL_1X22 0x00000016 | |
507 | #define HRCWL_CE_TO_PLL_1X23 0x00000017 | |
508 | #define HRCWL_CE_TO_PLL_1X24 0x00000018 | |
509 | #define HRCWL_CE_TO_PLL_1X25 0x00000019 | |
510 | #define HRCWL_CE_TO_PLL_1X26 0x0000001A | |
511 | #define HRCWL_CE_TO_PLL_1X27 0x0000001B | |
512 | #define HRCWL_CE_TO_PLL_1X28 0x0000001C | |
513 | #define HRCWL_CE_TO_PLL_1X29 0x0000001D | |
514 | #define HRCWL_CE_TO_PLL_1X30 0x0000001E | |
515 | #define HRCWL_CE_TO_PLL_1X31 0x0000001F | |
03051c3d | 516 | |
139ff3be | 517 | #elif defined(CONFIG_ARCH_MPC8308) |
6f3931a2 DL |
518 | #define HRCWL_SVCOD 0x30000000 |
519 | #define HRCWL_SVCOD_SHIFT 28 | |
520 | #define HRCWL_SVCOD_DIV_2 0x00000000 | |
521 | #define HRCWL_SVCOD_DIV_4 0x10000000 | |
522 | #define HRCWL_SVCOD_DIV_8 0x20000000 | |
523 | #define HRCWL_SVCOD_DIV_1 0x30000000 | |
524 | ||
8439e99d | 525 | #elif defined(CONFIG_ARCH_MPC837X) |
03051c3d DL |
526 | #define HRCWL_SVCOD 0x30000000 |
527 | #define HRCWL_SVCOD_SHIFT 28 | |
528 | #define HRCWL_SVCOD_DIV_4 0x00000000 | |
529 | #define HRCWL_SVCOD_DIV_8 0x10000000 | |
530 | #define HRCWL_SVCOD_DIV_2 0x20000000 | |
531 | #define HRCWL_SVCOD_DIV_1 0x30000000 | |
5f820439 | 532 | #endif |
f046ccd1 | 533 | |
4e8b750c HS |
534 | /* |
535 | * HRCWH - Hardware Reset Configuration Word High | |
de1d0a69 | 536 | */ |
e080313c DL |
537 | #define HRCWH_PCI_HOST 0x80000000 |
538 | #define HRCWH_PCI_HOST_SHIFT 31 | |
539 | #define HRCWH_PCI_AGENT 0x00000000 | |
f046ccd1 | 540 | |
d5cfa4aa | 541 | #if defined(CONFIG_ARCH_MPC834X) |
e080313c DL |
542 | #define HRCWH_32_BIT_PCI 0x00000000 |
543 | #define HRCWH_64_BIT_PCI 0x40000000 | |
5f820439 | 544 | #endif |
f046ccd1 | 545 | |
e080313c DL |
546 | #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 |
547 | #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 | |
548 | ||
549 | #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 | |
550 | #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 | |
f046ccd1 | 551 | |
d5cfa4aa | 552 | #if defined(CONFIG_ARCH_MPC834X) |
e080313c DL |
553 | #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 |
554 | #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 | |
555 | ||
61abced7 | 556 | #elif defined(CONFIG_ARCH_MPC8360) |
e080313c DL |
557 | #define HRCWH_PCICKDRV_DISABLE 0x00000000 |
558 | #define HRCWH_PCICKDRV_ENABLE 0x10000000 | |
5f820439 | 559 | #endif |
f046ccd1 | 560 | |
e080313c DL |
561 | #define HRCWH_CORE_DISABLE 0x08000000 |
562 | #define HRCWH_CORE_ENABLE 0x00000000 | |
f046ccd1 | 563 | |
e080313c DL |
564 | #define HRCWH_FROM_0X00000100 0x00000000 |
565 | #define HRCWH_FROM_0XFFF00100 0x04000000 | |
f046ccd1 | 566 | |
e080313c DL |
567 | #define HRCWH_BOOTSEQ_DISABLE 0x00000000 |
568 | #define HRCWH_BOOTSEQ_NORMAL 0x01000000 | |
569 | #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 | |
f046ccd1 | 570 | |
e080313c DL |
571 | #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 |
572 | #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 | |
f046ccd1 | 573 | |
e080313c DL |
574 | #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 |
575 | #define HRCWH_ROM_LOC_PCI1 0x00100000 | |
d5cfa4aa | 576 | #if defined(CONFIG_ARCH_MPC834X) |
e080313c | 577 | #define HRCWH_ROM_LOC_PCI2 0x00200000 |
5f820439 | 578 | #endif |
8439e99d | 579 | #if defined(CONFIG_ARCH_MPC837X) |
03051c3d DL |
580 | #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 |
581 | #endif | |
e080313c DL |
582 | #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 |
583 | #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 | |
584 | #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 | |
585 | ||
9403fc41 | 586 | #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ |
8439e99d | 587 | defined(CONFIG_ARCH_MPC837X) |
1636d1c8 | 588 | #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 |
d87c57b2 | 589 | #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 |
1636d1c8 | 590 | #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 |
d87c57b2 SW |
591 | #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 |
592 | ||
593 | #define HRCWH_RL_EXT_LEGACY 0x00000000 | |
594 | #define HRCWH_RL_EXT_NAND 0x00040000 | |
595 | ||
e6d9c891 | 596 | #define HRCWH_TSEC1M_MASK 0x0000E000 |
d87c57b2 SW |
597 | #define HRCWH_TSEC1M_IN_MII 0x00000000 |
598 | #define HRCWH_TSEC1M_IN_RMII 0x00002000 | |
599 | #define HRCWH_TSEC1M_IN_RGMII 0x00006000 | |
600 | #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 | |
601 | #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 | |
602 | ||
e6d9c891 | 603 | #define HRCWH_TSEC2M_MASK 0x00001C00 |
d87c57b2 SW |
604 | #define HRCWH_TSEC2M_IN_MII 0x00000000 |
605 | #define HRCWH_TSEC2M_IN_RMII 0x00000400 | |
606 | #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 | |
607 | #define HRCWH_TSEC2M_IN_RTBI 0x00001400 | |
608 | #define HRCWH_TSEC2M_IN_SGMII 0x00001800 | |
609 | #endif | |
610 | ||
d5cfa4aa | 611 | #if defined(CONFIG_ARCH_MPC834X) |
e080313c DL |
612 | #define HRCWH_TSEC1M_IN_RGMII 0x00000000 |
613 | #define HRCWH_TSEC1M_IN_RTBI 0x00004000 | |
614 | #define HRCWH_TSEC1M_IN_GMII 0x00008000 | |
615 | #define HRCWH_TSEC1M_IN_TBI 0x0000C000 | |
616 | #define HRCWH_TSEC2M_IN_RGMII 0x00000000 | |
617 | #define HRCWH_TSEC2M_IN_RTBI 0x00001000 | |
618 | #define HRCWH_TSEC2M_IN_GMII 0x00002000 | |
619 | #define HRCWH_TSEC2M_IN_TBI 0x00003000 | |
5f820439 DL |
620 | #endif |
621 | ||
61abced7 | 622 | #if defined(CONFIG_ARCH_MPC8360) |
e080313c DL |
623 | #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 |
624 | #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 | |
5f820439 | 625 | #endif |
f046ccd1 | 626 | |
e080313c DL |
627 | #define HRCWH_BIG_ENDIAN 0x00000000 |
628 | #define HRCWH_LITTLE_ENDIAN 0x00000008 | |
f046ccd1 | 629 | |
e080313c DL |
630 | #define HRCWH_LALE_NORMAL 0x00000000 |
631 | #define HRCWH_LALE_EARLY 0x00000004 | |
f6eda7f8 | 632 | |
e080313c DL |
633 | #define HRCWH_LDP_SET 0x00000000 |
634 | #define HRCWH_LDP_CLEAR 0x00000002 | |
f6eda7f8 | 635 | |
4e8b750c HS |
636 | /* |
637 | * RSR - Reset Status Register | |
e080313c | 638 | */ |
9403fc41 | 639 | #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ |
8439e99d | 640 | defined(CONFIG_ARCH_MPC837X) |
03051c3d DL |
641 | #define RSR_RSTSRC 0xF0000000 /* Reset source */ |
642 | #define RSR_RSTSRC_SHIFT 28 | |
643 | #else | |
e080313c DL |
644 | #define RSR_RSTSRC 0xE0000000 /* Reset source */ |
645 | #define RSR_RSTSRC_SHIFT 29 | |
03051c3d | 646 | #endif |
e080313c DL |
647 | #define RSR_BSF 0x00010000 /* Boot seq. fail */ |
648 | #define RSR_BSF_SHIFT 16 | |
4e8b750c HS |
649 | /* software soft reset */ |
650 | #define RSR_SWSR 0x00002000 | |
e080313c | 651 | #define RSR_SWSR_SHIFT 13 |
4e8b750c HS |
652 | /* software hard reset */ |
653 | #define RSR_SWHR 0x00001000 | |
e080313c DL |
654 | #define RSR_SWHR_SHIFT 12 |
655 | #define RSR_JHRS 0x00000200 /* jtag hreset */ | |
656 | #define RSR_JHRS_SHIFT 9 | |
4e8b750c HS |
657 | /* jtag sreset status */ |
658 | #define RSR_JSRS 0x00000100 | |
e080313c | 659 | #define RSR_JSRS_SHIFT 8 |
4e8b750c HS |
660 | /* checkstop reset status */ |
661 | #define RSR_CSHR 0x00000010 | |
e080313c | 662 | #define RSR_CSHR_SHIFT 4 |
4e8b750c HS |
663 | /* software watchdog reset status */ |
664 | #define RSR_SWRS 0x00000008 | |
e080313c | 665 | #define RSR_SWRS_SHIFT 3 |
4e8b750c HS |
666 | /* bus monitop reset status */ |
667 | #define RSR_BMRS 0x00000004 | |
e080313c DL |
668 | #define RSR_BMRS_SHIFT 2 |
669 | #define RSR_SRS 0x00000002 /* soft reset status */ | |
670 | #define RSR_SRS_SHIFT 1 | |
671 | #define RSR_HRS 0x00000001 /* hard reset status */ | |
672 | #define RSR_HRS_SHIFT 0 | |
4e8b750c HS |
673 | #define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \ |
674 | RSR_SWHR | RSR_JHRS | \ | |
675 | RSR_JSRS | RSR_CSHR | \ | |
676 | RSR_SWRS | RSR_BMRS | \ | |
677 | RSR_SRS | RSR_HRS)) | |
678 | /* | |
679 | * RMR - Reset Mode Register | |
e080313c | 680 | */ |
4e8b750c HS |
681 | /* checkstop reset enable */ |
682 | #define RMR_CSRE 0x00000001 | |
e080313c DL |
683 | #define RMR_CSRE_SHIFT 0 |
684 | #define RMR_RES ~(RMR_CSRE) | |
685 | ||
4e8b750c HS |
686 | /* |
687 | * RCR - Reset Control Register | |
e080313c | 688 | */ |
4e8b750c HS |
689 | /* software hard reset */ |
690 | #define RCR_SWHR 0x00000002 | |
691 | /* software soft reset */ | |
692 | #define RCR_SWSR 0x00000001 | |
e080313c DL |
693 | #define RCR_RES ~(RCR_SWHR | RCR_SWSR) |
694 | ||
4e8b750c HS |
695 | /* |
696 | * RCER - Reset Control Enable Register | |
e080313c | 697 | */ |
4e8b750c HS |
698 | /* software hard reset */ |
699 | #define RCER_CRE 0x00000001 | |
e080313c DL |
700 | #define RCER_RES ~(RCER_CRE) |
701 | ||
4e8b750c HS |
702 | /* |
703 | * SPMR - System PLL Mode Register | |
e080313c DL |
704 | */ |
705 | #define SPMR_LBIUCM 0x80000000 | |
26e5f794 | 706 | #define SPMR_LBIUCM_SHIFT 31 |
e080313c | 707 | #define SPMR_DDRCM 0x40000000 |
26e5f794 | 708 | #define SPMR_DDRCM_SHIFT 30 |
e080313c | 709 | #define SPMR_SPMF 0x0F000000 |
26e5f794 | 710 | #define SPMR_SPMF_SHIFT 24 |
e080313c DL |
711 | #define SPMR_CKID 0x00800000 |
712 | #define SPMR_CKID_SHIFT 23 | |
713 | #define SPMR_COREPLL 0x007F0000 | |
26e5f794 | 714 | #define SPMR_COREPLL_SHIFT 16 |
e080313c | 715 | #define SPMR_CEVCOD 0x000000C0 |
26e5f794 | 716 | #define SPMR_CEVCOD_SHIFT 6 |
e080313c | 717 | #define SPMR_CEPDF 0x00000020 |
26e5f794 | 718 | #define SPMR_CEPDF_SHIFT 5 |
e080313c | 719 | #define SPMR_CEPMF 0x0000001F |
26e5f794 | 720 | #define SPMR_CEPMF_SHIFT 0 |
e080313c | 721 | |
4e8b750c HS |
722 | /* |
723 | * OCCR - Output Clock Control Register | |
e080313c DL |
724 | */ |
725 | #define OCCR_PCICOE0 0x80000000 | |
726 | #define OCCR_PCICOE1 0x40000000 | |
727 | #define OCCR_PCICOE2 0x20000000 | |
728 | #define OCCR_PCICOE3 0x10000000 | |
729 | #define OCCR_PCICOE4 0x08000000 | |
730 | #define OCCR_PCICOE5 0x04000000 | |
731 | #define OCCR_PCICOE6 0x02000000 | |
732 | #define OCCR_PCICOE7 0x01000000 | |
733 | #define OCCR_PCICD0 0x00800000 | |
734 | #define OCCR_PCICD1 0x00400000 | |
735 | #define OCCR_PCICD2 0x00200000 | |
736 | #define OCCR_PCICD3 0x00100000 | |
737 | #define OCCR_PCICD4 0x00080000 | |
738 | #define OCCR_PCICD5 0x00040000 | |
739 | #define OCCR_PCICD6 0x00020000 | |
740 | #define OCCR_PCICD7 0x00010000 | |
741 | #define OCCR_PCI1CR 0x00000002 | |
742 | #define OCCR_PCI2CR 0x00000001 | |
743 | #define OCCR_PCICR OCCR_PCI1CR | |
744 | ||
4e8b750c HS |
745 | /* |
746 | * SCCR - System Clock Control Register | |
e080313c DL |
747 | */ |
748 | #define SCCR_ENCCM 0x03000000 | |
749 | #define SCCR_ENCCM_SHIFT 24 | |
750 | #define SCCR_ENCCM_0 0x00000000 | |
751 | #define SCCR_ENCCM_1 0x01000000 | |
752 | #define SCCR_ENCCM_2 0x02000000 | |
753 | #define SCCR_ENCCM_3 0x03000000 | |
754 | ||
755 | #define SCCR_PCICM 0x00010000 | |
756 | #define SCCR_PCICM_SHIFT 16 | |
757 | ||
d5cfa4aa MS |
758 | #if defined(CONFIG_ARCH_MPC834X) |
759 | /* SCCR bits - MPC834X specific */ | |
e080313c DL |
760 | #define SCCR_TSEC1CM 0xc0000000 |
761 | #define SCCR_TSEC1CM_SHIFT 30 | |
762 | #define SCCR_TSEC1CM_0 0x00000000 | |
763 | #define SCCR_TSEC1CM_1 0x40000000 | |
764 | #define SCCR_TSEC1CM_2 0x80000000 | |
765 | #define SCCR_TSEC1CM_3 0xC0000000 | |
766 | ||
767 | #define SCCR_TSEC2CM 0x30000000 | |
768 | #define SCCR_TSEC2CM_SHIFT 28 | |
769 | #define SCCR_TSEC2CM_0 0x00000000 | |
770 | #define SCCR_TSEC2CM_1 0x10000000 | |
771 | #define SCCR_TSEC2CM_2 0x20000000 | |
772 | #define SCCR_TSEC2CM_3 0x30000000 | |
d87c57b2 | 773 | |
03051c3d DL |
774 | /* The MPH must have the same clock ratio as DR, unless its clock disabled */ |
775 | #define SCCR_USBMPHCM 0x00c00000 | |
776 | #define SCCR_USBMPHCM_SHIFT 22 | |
777 | #define SCCR_USBDRCM 0x00300000 | |
778 | #define SCCR_USBDRCM_SHIFT 20 | |
779 | #define SCCR_USBCM 0x00f00000 | |
780 | #define SCCR_USBCM_SHIFT 20 | |
781 | #define SCCR_USBCM_0 0x00000000 | |
782 | #define SCCR_USBCM_1 0x00500000 | |
783 | #define SCCR_USBCM_2 0x00A00000 | |
784 | #define SCCR_USBCM_3 0x00F00000 | |
785 | ||
9403fc41 | 786 | #elif defined(CONFIG_ARCH_MPC8313) |
a8cb43a8 | 787 | /* TSEC1 bits are for TSEC2 as well */ |
d87c57b2 SW |
788 | #define SCCR_TSEC1CM 0xc0000000 |
789 | #define SCCR_TSEC1CM_SHIFT 30 | |
9e896478 | 790 | #define SCCR_TSEC1CM_0 0x00000000 |
d87c57b2 SW |
791 | #define SCCR_TSEC1CM_1 0x40000000 |
792 | #define SCCR_TSEC1CM_2 0x80000000 | |
793 | #define SCCR_TSEC1CM_3 0xC0000000 | |
794 | ||
795 | #define SCCR_TSEC1ON 0x20000000 | |
df33f6b4 | 796 | #define SCCR_TSEC1ON_SHIFT 29 |
d87c57b2 | 797 | #define SCCR_TSEC2ON 0x10000000 |
df33f6b4 | 798 | #define SCCR_TSEC2ON_SHIFT 28 |
d87c57b2 | 799 | |
e080313c DL |
800 | #define SCCR_USBDRCM 0x00300000 |
801 | #define SCCR_USBDRCM_SHIFT 20 | |
03051c3d DL |
802 | #define SCCR_USBDRCM_0 0x00000000 |
803 | #define SCCR_USBDRCM_1 0x00100000 | |
804 | #define SCCR_USBDRCM_2 0x00200000 | |
805 | #define SCCR_USBDRCM_3 0x00300000 | |
e080313c | 806 | |
139ff3be | 807 | #elif defined(CONFIG_ARCH_MPC8308) |
7c619ddc | 808 | /* SCCR bits - MPC8315/MPC8308 specific */ |
555da617 DL |
809 | #define SCCR_TSEC1CM 0xc0000000 |
810 | #define SCCR_TSEC1CM_SHIFT 30 | |
811 | #define SCCR_TSEC1CM_0 0x00000000 | |
812 | #define SCCR_TSEC1CM_1 0x40000000 | |
813 | #define SCCR_TSEC1CM_2 0x80000000 | |
814 | #define SCCR_TSEC1CM_3 0xC0000000 | |
815 | ||
816 | #define SCCR_TSEC2CM 0x30000000 | |
817 | #define SCCR_TSEC2CM_SHIFT 28 | |
818 | #define SCCR_TSEC2CM_0 0x00000000 | |
819 | #define SCCR_TSEC2CM_1 0x10000000 | |
820 | #define SCCR_TSEC2CM_2 0x20000000 | |
821 | #define SCCR_TSEC2CM_3 0x30000000 | |
822 | ||
7c619ddc IY |
823 | #define SCCR_SDHCCM 0x0c000000 |
824 | #define SCCR_SDHCCM_SHIFT 26 | |
825 | #define SCCR_SDHCCM_0 0x00000000 | |
826 | #define SCCR_SDHCCM_1 0x04000000 | |
827 | #define SCCR_SDHCCM_2 0x08000000 | |
828 | #define SCCR_SDHCCM_3 0x0c000000 | |
829 | ||
6f3931a2 DL |
830 | #define SCCR_USBDRCM 0x00c00000 |
831 | #define SCCR_USBDRCM_SHIFT 22 | |
555da617 | 832 | #define SCCR_USBDRCM_0 0x00000000 |
6f3931a2 DL |
833 | #define SCCR_USBDRCM_1 0x00400000 |
834 | #define SCCR_USBDRCM_2 0x00800000 | |
835 | #define SCCR_USBDRCM_3 0x00c00000 | |
555da617 | 836 | |
6f3931a2 DL |
837 | #define SCCR_SATA1CM 0x00003000 |
838 | #define SCCR_SATA1CM_SHIFT 12 | |
839 | #define SCCR_SATACM 0x00003c00 | |
840 | #define SCCR_SATACM_SHIFT 10 | |
555da617 | 841 | #define SCCR_SATACM_0 0x00000000 |
6f3931a2 DL |
842 | #define SCCR_SATACM_1 0x00001400 |
843 | #define SCCR_SATACM_2 0x00002800 | |
844 | #define SCCR_SATACM_3 0x00003c00 | |
555da617 | 845 | |
6f3931a2 DL |
846 | #define SCCR_TDMCM 0x00000030 |
847 | #define SCCR_TDMCM_SHIFT 4 | |
555da617 | 848 | #define SCCR_TDMCM_0 0x00000000 |
6f3931a2 DL |
849 | #define SCCR_TDMCM_1 0x00000010 |
850 | #define SCCR_TDMCM_2 0x00000020 | |
851 | #define SCCR_TDMCM_3 0x00000030 | |
555da617 | 852 | |
8439e99d MS |
853 | #elif defined(CONFIG_ARCH_MPC837X) |
854 | /* SCCR bits - MPC837X specific */ | |
03051c3d DL |
855 | #define SCCR_TSEC1CM 0xc0000000 |
856 | #define SCCR_TSEC1CM_SHIFT 30 | |
857 | #define SCCR_TSEC1CM_0 0x00000000 | |
858 | #define SCCR_TSEC1CM_1 0x40000000 | |
859 | #define SCCR_TSEC1CM_2 0x80000000 | |
860 | #define SCCR_TSEC1CM_3 0xC0000000 | |
861 | ||
862 | #define SCCR_TSEC2CM 0x30000000 | |
863 | #define SCCR_TSEC2CM_SHIFT 28 | |
864 | #define SCCR_TSEC2CM_0 0x00000000 | |
865 | #define SCCR_TSEC2CM_1 0x10000000 | |
866 | #define SCCR_TSEC2CM_2 0x20000000 | |
867 | #define SCCR_TSEC2CM_3 0x30000000 | |
868 | ||
869 | #define SCCR_SDHCCM 0x0c000000 | |
870 | #define SCCR_SDHCCM_SHIFT 26 | |
871 | #define SCCR_SDHCCM_0 0x00000000 | |
872 | #define SCCR_SDHCCM_1 0x04000000 | |
873 | #define SCCR_SDHCCM_2 0x08000000 | |
874 | #define SCCR_SDHCCM_3 0x0c000000 | |
875 | ||
876 | #define SCCR_USBDRCM 0x00c00000 | |
877 | #define SCCR_USBDRCM_SHIFT 22 | |
878 | #define SCCR_USBDRCM_0 0x00000000 | |
879 | #define SCCR_USBDRCM_1 0x00400000 | |
880 | #define SCCR_USBDRCM_2 0x00800000 | |
881 | #define SCCR_USBDRCM_3 0x00c00000 | |
882 | ||
fd6646c0 AV |
883 | /* All of the four SATA controllers must have the same clock ratio */ |
884 | #define SCCR_SATA1CM 0x000000c0 | |
885 | #define SCCR_SATA1CM_SHIFT 6 | |
886 | #define SCCR_SATACM 0x000000ff | |
887 | #define SCCR_SATACM_SHIFT 0 | |
888 | #define SCCR_SATACM_0 0x00000000 | |
889 | #define SCCR_SATACM_1 0x00000055 | |
890 | #define SCCR_SATACM_2 0x000000aa | |
891 | #define SCCR_SATACM_3 0x000000ff | |
892 | #endif | |
893 | ||
03051c3d DL |
894 | #define SCCR_PCIEXP1CM 0x00300000 |
895 | #define SCCR_PCIEXP1CM_SHIFT 20 | |
896 | #define SCCR_PCIEXP1CM_0 0x00000000 | |
897 | #define SCCR_PCIEXP1CM_1 0x00100000 | |
898 | #define SCCR_PCIEXP1CM_2 0x00200000 | |
899 | #define SCCR_PCIEXP1CM_3 0x00300000 | |
900 | ||
901 | #define SCCR_PCIEXP2CM 0x000c0000 | |
902 | #define SCCR_PCIEXP2CM_SHIFT 18 | |
903 | #define SCCR_PCIEXP2CM_0 0x00000000 | |
904 | #define SCCR_PCIEXP2CM_1 0x00040000 | |
905 | #define SCCR_PCIEXP2CM_2 0x00080000 | |
906 | #define SCCR_PCIEXP2CM_3 0x000c0000 | |
907 | ||
4e8b750c HS |
908 | /* |
909 | * CSn_BDNS - Chip Select memory Bounds Register | |
e080313c DL |
910 | */ |
911 | #define CSBNDS_SA 0x00FF0000 | |
912 | #define CSBNDS_SA_SHIFT 8 | |
913 | #define CSBNDS_EA 0x000000FF | |
914 | #define CSBNDS_EA_SHIFT 24 | |
915 | ||
e4061556 MS |
916 | #ifndef CONFIG_MPC83XX_SDRAM |
917 | ||
4e8b750c HS |
918 | /* |
919 | * CSn_CONFIG - Chip Select Configuration Register | |
e080313c DL |
920 | */ |
921 | #define CSCONFIG_EN 0x80000000 | |
922 | #define CSCONFIG_AP 0x00800000 | |
9403fc41 | 923 | #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) |
2fef4020 JH |
924 | #define CSCONFIG_ODT_RD_NEVER 0x00000000 |
925 | #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 | |
926 | #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 | |
927 | #define CSCONFIG_ODT_RD_ALL 0x00400000 | |
928 | #define CSCONFIG_ODT_WR_NEVER 0x00000000 | |
929 | #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 | |
930 | #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 | |
931 | #define CSCONFIG_ODT_WR_ALL 0x00040000 | |
bd3b867e | 932 | #elif defined(CONFIG_ARCH_MPC832X) |
2fef4020 | 933 | #define CSCONFIG_ODT_RD_CFG 0x00400000 |
6d2c26ac | 934 | #define CSCONFIG_ODT_WR_CFG 0x00040000 |
8439e99d | 935 | #elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X) |
2fef4020 JH |
936 | #define CSCONFIG_ODT_RD_NEVER 0x00000000 |
937 | #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 | |
938 | #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 | |
939 | #define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000 | |
940 | #define CSCONFIG_ODT_RD_ALL 0x00400000 | |
941 | #define CSCONFIG_ODT_WR_NEVER 0x00000000 | |
942 | #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 | |
943 | #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 | |
944 | #define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000 | |
945 | #define CSCONFIG_ODT_WR_ALL 0x00040000 | |
6d2c26ac | 946 | #endif |
d82b4fc0 | 947 | #define CSCONFIG_BANK_BIT_3 0x00004000 |
e080313c DL |
948 | #define CSCONFIG_ROW_BIT 0x00000700 |
949 | #define CSCONFIG_ROW_BIT_12 0x00000000 | |
950 | #define CSCONFIG_ROW_BIT_13 0x00000100 | |
951 | #define CSCONFIG_ROW_BIT_14 0x00000200 | |
952 | #define CSCONFIG_COL_BIT 0x00000007 | |
953 | #define CSCONFIG_COL_BIT_8 0x00000000 | |
954 | #define CSCONFIG_COL_BIT_9 0x00000001 | |
955 | #define CSCONFIG_COL_BIT_10 0x00000002 | |
956 | #define CSCONFIG_COL_BIT_11 0x00000003 | |
957 | ||
4e8b750c HS |
958 | /* |
959 | * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 | |
d87c57b2 SW |
960 | */ |
961 | #define TIMING_CFG0_RWT 0xC0000000 | |
962 | #define TIMING_CFG0_RWT_SHIFT 30 | |
963 | #define TIMING_CFG0_WRT 0x30000000 | |
964 | #define TIMING_CFG0_WRT_SHIFT 28 | |
965 | #define TIMING_CFG0_RRT 0x0C000000 | |
966 | #define TIMING_CFG0_RRT_SHIFT 26 | |
967 | #define TIMING_CFG0_WWT 0x03000000 | |
968 | #define TIMING_CFG0_WWT_SHIFT 24 | |
969 | #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 | |
970 | #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 | |
971 | #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 | |
972 | #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 | |
973 | #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 | |
974 | #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 | |
d892b2db | 975 | #define TIMING_CFG0_MRS_CYC 0x0000000F |
d87c57b2 SW |
976 | #define TIMING_CFG0_MRS_CYC_SHIFT 0 |
977 | ||
4e8b750c HS |
978 | /* |
979 | * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 | |
e080313c DL |
980 | */ |
981 | #define TIMING_CFG1_PRETOACT 0x70000000 | |
982 | #define TIMING_CFG1_PRETOACT_SHIFT 28 | |
983 | #define TIMING_CFG1_ACTTOPRE 0x0F000000 | |
984 | #define TIMING_CFG1_ACTTOPRE_SHIFT 24 | |
985 | #define TIMING_CFG1_ACTTORW 0x00700000 | |
986 | #define TIMING_CFG1_ACTTORW_SHIFT 20 | |
987 | #define TIMING_CFG1_CASLAT 0x00070000 | |
988 | #define TIMING_CFG1_CASLAT_SHIFT 16 | |
989 | #define TIMING_CFG1_REFREC 0x0000F000 | |
990 | #define TIMING_CFG1_REFREC_SHIFT 12 | |
991 | #define TIMING_CFG1_WRREC 0x00000700 | |
992 | #define TIMING_CFG1_WRREC_SHIFT 8 | |
993 | #define TIMING_CFG1_ACTTOACT 0x00000070 | |
994 | #define TIMING_CFG1_ACTTOACT_SHIFT 4 | |
995 | #define TIMING_CFG1_WRTORD 0x00000007 | |
996 | #define TIMING_CFG1_WRTORD_SHIFT 0 | |
997 | #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ | |
998 | #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ | |
facdad5f HS |
999 | #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ |
1000 | #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ | |
1001 | #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ | |
2b68b233 HS |
1002 | #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ |
1003 | #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ | |
e080313c | 1004 | |
4e8b750c HS |
1005 | /* |
1006 | * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 | |
e080313c | 1007 | */ |
8d172c0f XX |
1008 | #define TIMING_CFG2_CPO 0x0F800000 |
1009 | #define TIMING_CFG2_CPO_SHIFT 23 | |
e080313c DL |
1010 | #define TIMING_CFG2_ACSM 0x00080000 |
1011 | #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 | |
1012 | #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 | |
4e8b750c HS |
1013 | /* default (= CASLAT + 1) */ |
1014 | #define TIMING_CFG2_CPO_DEF 0x00000000 | |
e080313c | 1015 | |
d87c57b2 SW |
1016 | #define TIMING_CFG2_ADD_LAT 0x70000000 |
1017 | #define TIMING_CFG2_ADD_LAT_SHIFT 28 | |
1018 | #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 | |
1019 | #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 | |
1020 | #define TIMING_CFG2_RD_TO_PRE 0x0000E000 | |
1021 | #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 | |
1022 | #define TIMING_CFG2_CKE_PLS 0x000001C0 | |
1023 | #define TIMING_CFG2_CKE_PLS_SHIFT 6 | |
1024 | #define TIMING_CFG2_FOUR_ACT 0x0000003F | |
1025 | #define TIMING_CFG2_FOUR_ACT_SHIFT 0 | |
1026 | ||
f1ccd106 HS |
1027 | /* |
1028 | * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 | |
1029 | */ | |
1030 | #define TIMING_CFG3_EXT_REFREC 0x00070000 | |
1031 | #define TIMING_CFG3_EXT_REFREC_SHIFT 16 | |
1032 | ||
4e8b750c HS |
1033 | /* |
1034 | * DDR_SDRAM_CFG - DDR SDRAM Control Configuration | |
e080313c DL |
1035 | */ |
1036 | #define SDRAM_CFG_MEM_EN 0x80000000 | |
1037 | #define SDRAM_CFG_SREN 0x40000000 | |
1038 | #define SDRAM_CFG_ECC_EN 0x20000000 | |
1039 | #define SDRAM_CFG_RD_EN 0x10000000 | |
bbea46f7 KP |
1040 | #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 |
1041 | #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 | |
1042 | #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 | |
e080313c DL |
1043 | #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 |
1044 | #define SDRAM_CFG_DYN_PWR 0x00200000 | |
9403fc41 | 1045 | #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) |
2fef4020 JH |
1046 | #define SDRAM_CFG_DBW_MASK 0x00180000 |
1047 | #define SDRAM_CFG_DBW_16 0x00100000 | |
1048 | #define SDRAM_CFG_DBW_32 0x00080000 | |
1049 | #else | |
e080313c | 1050 | #define SDRAM_CFG_32_BE 0x00080000 |
2fef4020 | 1051 | #endif |
4bc97a3b | 1052 | #if !defined(CONFIG_ARCH_MPC8308) |
e080313c | 1053 | #define SDRAM_CFG_8_BE 0x00040000 |
2fef4020 | 1054 | #endif |
e080313c DL |
1055 | #define SDRAM_CFG_NCAP 0x00020000 |
1056 | #define SDRAM_CFG_2T_EN 0x00008000 | |
a7b8126e | 1057 | #define SDRAM_CFG_HSE 0x00000008 |
d87c57b2 | 1058 | #define SDRAM_CFG_BI 0x00000001 |
e080313c | 1059 | |
4e8b750c HS |
1060 | /* |
1061 | * DDR_SDRAM_MODE - DDR SDRAM Mode Register | |
e080313c DL |
1062 | */ |
1063 | #define SDRAM_MODE_ESD 0xFFFF0000 | |
1064 | #define SDRAM_MODE_ESD_SHIFT 16 | |
1065 | #define SDRAM_MODE_SD 0x0000FFFF | |
1066 | #define SDRAM_MODE_SD_SHIFT 0 | |
4e8b750c HS |
1067 | /* select extended mode reg */ |
1068 | #define DDR_MODE_EXT_MODEREG 0x4000 | |
1069 | /* operating mode, mask */ | |
1070 | #define DDR_MODE_EXT_OPMODE 0x3FF8 | |
e080313c | 1071 | #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ |
4e8b750c HS |
1072 | /* QFC / compatibility, mask */ |
1073 | #define DDR_MODE_QFC 0x0004 | |
1074 | /* compatible to older SDRAMs */ | |
1075 | #define DDR_MODE_QFC_COMP 0x0000 | |
1076 | /* weak drivers */ | |
1077 | #define DDR_MODE_WEAK 0x0002 | |
1078 | /* disable DLL */ | |
1079 | #define DDR_MODE_DLL_DIS 0x0001 | |
1080 | /* CAS latency, mask */ | |
1081 | #define DDR_MODE_CASLAT 0x0070 | |
e080313c DL |
1082 | #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ |
1083 | #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ | |
1084 | #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ | |
1085 | #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ | |
4e8b750c HS |
1086 | /* sequential burst */ |
1087 | #define DDR_MODE_BTYPE_SEQ 0x0000 | |
1088 | /* interleaved burst */ | |
1089 | #define DDR_MODE_BTYPE_ILVD 0x0008 | |
e080313c DL |
1090 | #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ |
1091 | #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ | |
4e8b750c HS |
1092 | /* exact value for 7.8125us */ |
1093 | #define DDR_REFINT_166MHZ_7US 1302 | |
1094 | /* use 256 cycles as a starting point */ | |
1095 | #define DDR_BSTOPRE 256 | |
1096 | /* select mode register */ | |
1097 | #define DDR_MODE_MODEREG 0x0000 | |
e080313c | 1098 | |
4e8b750c HS |
1099 | /* |
1100 | * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register | |
e080313c DL |
1101 | */ |
1102 | #define SDRAM_INTERVAL_REFINT 0x3FFF0000 | |
1103 | #define SDRAM_INTERVAL_REFINT_SHIFT 16 | |
e080313c DL |
1104 | #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 |
1105 | ||
4e8b750c HS |
1106 | /* |
1107 | * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register | |
e080313c DL |
1108 | */ |
1109 | #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 | |
1110 | #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 | |
1111 | #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 | |
1112 | #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 | |
1113 | #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 | |
1114 | ||
4e8b750c HS |
1115 | /* |
1116 | * ECC_ERR_INJECT - Memory data path error injection mask ECC | |
e080313c | 1117 | */ |
4e8b750c HS |
1118 | /* ECC Mirror Byte */ |
1119 | #define ECC_ERR_INJECT_EMB (0x80000000 >> 22) | |
1120 | /* Error Injection Enable */ | |
1121 | #define ECC_ERR_INJECT_EIEN (0x80000000 >> 23) | |
1122 | /* ECC Erroe Injection Enable */ | |
1123 | #define ECC_ERR_INJECT_EEIM (0xff000000 >> 24) | |
e080313c DL |
1124 | #define ECC_ERR_INJECT_EEIM_SHIFT 0 |
1125 | ||
4e8b750c HS |
1126 | /* |
1127 | * CAPTURE_ECC - Memory data path read capture ECC | |
e080313c | 1128 | */ |
4e8b750c | 1129 | #define CAPTURE_ECC_ECE (0xff000000 >> 24) |
e080313c DL |
1130 | #define CAPTURE_ECC_ECE_SHIFT 0 |
1131 | ||
4e8b750c HS |
1132 | /* |
1133 | * ERR_DETECT - Memory error detect | |
e080313c | 1134 | */ |
4e8b750c HS |
1135 | /* Multiple Memory Errors */ |
1136 | #define ECC_ERROR_DETECT_MME (0x80000000 >> 0) | |
1137 | /* Multiple-Bit Error */ | |
1138 | #define ECC_ERROR_DETECT_MBE (0x80000000 >> 28) | |
1139 | /* Single-Bit ECC Error Pickup */ | |
1140 | #define ECC_ERROR_DETECT_SBE (0x80000000 >> 29) | |
1141 | /* Memory Select Error */ | |
1142 | #define ECC_ERROR_DETECT_MSE (0x80000000 >> 31) | |
e080313c | 1143 | |
4e8b750c HS |
1144 | /* |
1145 | * ERR_DISABLE - Memory error disable | |
e080313c | 1146 | */ |
4e8b750c HS |
1147 | /* Multiple-Bit ECC Error Disable */ |
1148 | #define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28) | |
1149 | /* Sinle-Bit ECC Error disable */ | |
1150 | #define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29) | |
1151 | /* Memory Select Error Disable */ | |
1152 | #define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31) | |
1153 | #define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \ | |
1154 | ECC_ERROR_DISABLE_SBED | \ | |
1155 | ECC_ERROR_DISABLE_MBED)) | |
1156 | ||
1157 | /* | |
1158 | * ERR_INT_EN - Memory error interrupt enable | |
e080313c | 1159 | */ |
4e8b750c HS |
1160 | /* Multiple-Bit ECC Error Interrupt Enable */ |
1161 | #define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28) | |
1162 | /* Single-Bit ECC Error Interrupt Enable */ | |
1163 | #define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29) | |
1164 | /* Memory Select Error Interrupt Enable */ | |
1165 | #define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31) | |
1166 | #define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \ | |
1167 | ECC_ERR_INT_EN_SBEE | \ | |
1168 | ECC_ERR_INT_EN_MSEE)) | |
1169 | ||
1170 | /* | |
1171 | * CAPTURE_ATTRIBUTES - Memory error attributes capture | |
e080313c | 1172 | */ |
4e8b750c HS |
1173 | /* Data Beat Num */ |
1174 | #define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1) | |
e080313c | 1175 | #define ECC_CAPT_ATTR_BNUM_SHIFT 28 |
4e8b750c HS |
1176 | /* Transaction Size */ |
1177 | #define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6) | |
e080313c DL |
1178 | #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 |
1179 | #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 | |
1180 | #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 | |
1181 | #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 | |
1182 | #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 | |
4e8b750c HS |
1183 | /* Transaction Source */ |
1184 | #define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11) | |
e080313c DL |
1185 | #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 |
1186 | #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 | |
1187 | #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 | |
1188 | #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 | |
1189 | #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) | |
1190 | #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 | |
1191 | #define ECC_CAPT_ATTR_TSRC_I2C 0x9 | |
1192 | #define ECC_CAPT_ATTR_TSRC_JTAG 0xA | |
1193 | #define ECC_CAPT_ATTR_TSRC_PCI1 0xD | |
1194 | #define ECC_CAPT_ATTR_TSRC_PCI2 0xE | |
1195 | #define ECC_CAPT_ATTR_TSRC_DMA 0xF | |
1196 | #define ECC_CAPT_ATTR_TSRC_SHIFT 16 | |
4e8b750c HS |
1197 | /* Transaction Type */ |
1198 | #define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18) | |
e080313c DL |
1199 | #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 |
1200 | #define ECC_CAPT_ATTR_TTYP_READ 0x2 | |
1201 | #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 | |
1202 | #define ECC_CAPT_ATTR_TTYP_SHIFT 12 | |
4e8b750c | 1203 | #define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */ |
e080313c | 1204 | |
4e8b750c HS |
1205 | /* |
1206 | * ERR_SBE - Single bit ECC memory error management | |
e080313c | 1207 | */ |
4e8b750c HS |
1208 | /* Single-Bit Error Threshold 0..255 */ |
1209 | #define ECC_ERROR_MAN_SBET (0xff000000 >> 8) | |
e080313c | 1210 | #define ECC_ERROR_MAN_SBET_SHIFT 16 |
4e8b750c HS |
1211 | /* Single Bit Error Counter 0..255 */ |
1212 | #define ECC_ERROR_MAN_SBEC (0xff000000 >> 24) | |
e080313c DL |
1213 | #define ECC_ERROR_MAN_SBEC_SHIFT 0 |
1214 | ||
e4061556 MS |
1215 | #endif /* !CONFIG_MPC83XX_SDRAM */ |
1216 | ||
4e8b750c | 1217 | /* |
0c1b10fe | 1218 | * PCI_CONFIG_ADDRESS - PCI Config Address Register |
e080313c DL |
1219 | */ |
1220 | #define PCI_CONFIG_ADDRESS_EN 0x80000000 | |
1221 | #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 | |
1222 | #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 | |
1223 | #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 | |
1224 | #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 | |
1225 | #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 | |
1226 | #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 | |
1227 | #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 | |
1228 | #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc | |
1229 | ||
4e8b750c HS |
1230 | /* |
1231 | * POTAR - PCI Outbound Translation Address Register | |
e080313c DL |
1232 | */ |
1233 | #define POTAR_TA_MASK 0x000fffff | |
1234 | ||
4e8b750c HS |
1235 | /* |
1236 | * POBAR - PCI Outbound Base Address Register | |
e080313c DL |
1237 | */ |
1238 | #define POBAR_BA_MASK 0x000fffff | |
1239 | ||
4e8b750c HS |
1240 | /* |
1241 | * POCMR - PCI Outbound Comparision Mask Register | |
e080313c DL |
1242 | */ |
1243 | #define POCMR_EN 0x80000000 | |
4e8b750c HS |
1244 | /* 0-memory space 1-I/O space */ |
1245 | #define POCMR_IO 0x40000000 | |
e080313c DL |
1246 | #define POCMR_SE 0x20000000 /* streaming enable */ |
1247 | #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ | |
1248 | #define POCMR_CM_MASK 0x000fffff | |
1249 | #define POCMR_CM_4G 0x00000000 | |
1250 | #define POCMR_CM_2G 0x00080000 | |
1251 | #define POCMR_CM_1G 0x000C0000 | |
1252 | #define POCMR_CM_512M 0x000E0000 | |
1253 | #define POCMR_CM_256M 0x000F0000 | |
1254 | #define POCMR_CM_128M 0x000F8000 | |
1255 | #define POCMR_CM_64M 0x000FC000 | |
1256 | #define POCMR_CM_32M 0x000FE000 | |
1257 | #define POCMR_CM_16M 0x000FF000 | |
1258 | #define POCMR_CM_8M 0x000FF800 | |
1259 | #define POCMR_CM_4M 0x000FFC00 | |
1260 | #define POCMR_CM_2M 0x000FFE00 | |
1261 | #define POCMR_CM_1M 0x000FFF00 | |
1262 | #define POCMR_CM_512K 0x000FFF80 | |
1263 | #define POCMR_CM_256K 0x000FFFC0 | |
1264 | #define POCMR_CM_128K 0x000FFFE0 | |
1265 | #define POCMR_CM_64K 0x000FFFF0 | |
1266 | #define POCMR_CM_32K 0x000FFFF8 | |
1267 | #define POCMR_CM_16K 0x000FFFFC | |
1268 | #define POCMR_CM_8K 0x000FFFFE | |
1269 | #define POCMR_CM_4K 0x000FFFFF | |
1270 | ||
4e8b750c HS |
1271 | /* |
1272 | * PITAR - PCI Inbound Translation Address Register | |
e080313c DL |
1273 | */ |
1274 | #define PITAR_TA_MASK 0x000fffff | |
1275 | ||
4e8b750c HS |
1276 | /* |
1277 | * PIBAR - PCI Inbound Base/Extended Address Register | |
e080313c DL |
1278 | */ |
1279 | #define PIBAR_MASK 0xffffffff | |
1280 | #define PIEBAR_EBA_MASK 0x000fffff | |
1281 | ||
4e8b750c HS |
1282 | /* |
1283 | * PIWAR - PCI Inbound Windows Attributes Register | |
e080313c DL |
1284 | */ |
1285 | #define PIWAR_EN 0x80000000 | |
1286 | #define PIWAR_PF 0x20000000 | |
1287 | #define PIWAR_RTT_MASK 0x000f0000 | |
1288 | #define PIWAR_RTT_NO_SNOOP 0x00040000 | |
1289 | #define PIWAR_RTT_SNOOP 0x00050000 | |
1290 | #define PIWAR_WTT_MASK 0x0000f000 | |
1291 | #define PIWAR_WTT_NO_SNOOP 0x00004000 | |
1292 | #define PIWAR_WTT_SNOOP 0x00005000 | |
1293 | #define PIWAR_IWS_MASK 0x0000003F | |
1294 | #define PIWAR_IWS_4K 0x0000000B | |
1295 | #define PIWAR_IWS_8K 0x0000000C | |
1296 | #define PIWAR_IWS_16K 0x0000000D | |
1297 | #define PIWAR_IWS_32K 0x0000000E | |
1298 | #define PIWAR_IWS_64K 0x0000000F | |
1299 | #define PIWAR_IWS_128K 0x00000010 | |
1300 | #define PIWAR_IWS_256K 0x00000011 | |
1301 | #define PIWAR_IWS_512K 0x00000012 | |
1302 | #define PIWAR_IWS_1M 0x00000013 | |
1303 | #define PIWAR_IWS_2M 0x00000014 | |
1304 | #define PIWAR_IWS_4M 0x00000015 | |
1305 | #define PIWAR_IWS_8M 0x00000016 | |
1306 | #define PIWAR_IWS_16M 0x00000017 | |
1307 | #define PIWAR_IWS_32M 0x00000018 | |
1308 | #define PIWAR_IWS_64M 0x00000019 | |
1309 | #define PIWAR_IWS_128M 0x0000001A | |
1310 | #define PIWAR_IWS_256M 0x0000001B | |
1311 | #define PIWAR_IWS_512M 0x0000001C | |
1312 | #define PIWAR_IWS_1G 0x0000001D | |
1313 | #define PIWAR_IWS_2G 0x0000001E | |
f6eda7f8 | 1314 | |
4e8b750c HS |
1315 | /* |
1316 | * PMCCR1 - PCI Configuration Register 1 | |
d87c57b2 SW |
1317 | */ |
1318 | #define PMCCR1_POWER_OFF 0x00000020 | |
1319 | ||
e4061556 | 1320 | #ifndef CONFIG_RAM |
4e8b750c HS |
1321 | /* |
1322 | * DDRCDR - DDR Control Driver Register | |
d87c57b2 | 1323 | */ |
9e896478 | 1324 | #define DDRCDR_DHC_EN 0x80000000 |
d87c57b2 SW |
1325 | #define DDRCDR_EN 0x40000000 |
1326 | #define DDRCDR_PZ 0x3C000000 | |
1327 | #define DDRCDR_PZ_MAXZ 0x00000000 | |
1328 | #define DDRCDR_PZ_HIZ 0x20000000 | |
1329 | #define DDRCDR_PZ_NOMZ 0x30000000 | |
1330 | #define DDRCDR_PZ_LOZ 0x38000000 | |
1331 | #define DDRCDR_PZ_MINZ 0x3C000000 | |
1332 | #define DDRCDR_NZ 0x3C000000 | |
1333 | #define DDRCDR_NZ_MAXZ 0x00000000 | |
1334 | #define DDRCDR_NZ_HIZ 0x02000000 | |
1335 | #define DDRCDR_NZ_NOMZ 0x03000000 | |
1336 | #define DDRCDR_NZ_LOZ 0x03800000 | |
1337 | #define DDRCDR_NZ_MINZ 0x03C00000 | |
1338 | #define DDRCDR_ODT 0x00080000 | |
1339 | #define DDRCDR_DDR_CFG 0x00040000 | |
1340 | #define DDRCDR_M_ODR 0x00000002 | |
1341 | #define DDRCDR_Q_DRN 0x00000001 | |
e4061556 | 1342 | #endif /* !CONFIG_RAM */ |
d87c57b2 | 1343 | |
4e8b750c HS |
1344 | /* |
1345 | * PCIE Bridge Register | |
1346 | */ | |
fd6646c0 AV |
1347 | #define PEX_CSB_CTRL_OBPIOE 0x00000001 |
1348 | #define PEX_CSB_CTRL_IBPIOE 0x00000002 | |
1349 | #define PEX_CSB_CTRL_WDMAE 0x00000004 | |
1350 | #define PEX_CSB_CTRL_RDMAE 0x00000008 | |
1351 | ||
1352 | #define PEX_CSB_OBCTRL_PIOE 0x00000001 | |
1353 | #define PEX_CSB_OBCTRL_MEMWE 0x00000002 | |
1354 | #define PEX_CSB_OBCTRL_IOWE 0x00000004 | |
1355 | #define PEX_CSB_OBCTRL_CFGWE 0x00000008 | |
1356 | ||
1357 | #define PEX_CSB_IBCTRL_PIOE 0x00000001 | |
1358 | ||
1359 | #define PEX_OWAR_EN 0x00000001 | |
1360 | #define PEX_OWAR_TYPE_CFG 0x00000000 | |
1361 | #define PEX_OWAR_TYPE_IO 0x00000002 | |
1362 | #define PEX_OWAR_TYPE_MEM 0x00000004 | |
1363 | #define PEX_OWAR_RLXO 0x00000008 | |
1364 | #define PEX_OWAR_NANP 0x00000010 | |
1365 | #define PEX_OWAR_SIZE 0xFFFFF000 | |
1366 | ||
1367 | #define PEX_IWAR_EN 0x00000001 | |
1368 | #define PEX_IWAR_TYPE_INT 0x00000000 | |
1369 | #define PEX_IWAR_TYPE_PF 0x00000004 | |
1370 | #define PEX_IWAR_TYPE_NO_PF 0x00000006 | |
1371 | #define PEX_IWAR_NSOV 0x00000008 | |
1372 | #define PEX_IWAR_NSNP 0x00000010 | |
1373 | #define PEX_IWAR_SIZE 0xFFFFF000 | |
1374 | #define PEX_IWAR_SIZE_1M 0x000FF000 | |
1375 | #define PEX_IWAR_SIZE_2M 0x001FF000 | |
1376 | #define PEX_IWAR_SIZE_4M 0x003FF000 | |
1377 | #define PEX_IWAR_SIZE_8M 0x007FF000 | |
1378 | #define PEX_IWAR_SIZE_16M 0x00FFF000 | |
1379 | #define PEX_IWAR_SIZE_32M 0x01FFF000 | |
1380 | #define PEX_IWAR_SIZE_64M 0x03FFF000 | |
1381 | #define PEX_IWAR_SIZE_128M 0x07FFF000 | |
1382 | #define PEX_IWAR_SIZE_256M 0x0FFFF000 | |
1383 | ||
1384 | #define PEX_GCLK_RATIO 0x440 | |
1385 | ||
49ea3b6e SW |
1386 | #ifndef __ASSEMBLY__ |
1387 | struct pci_region; | |
6aa3d3bf | 1388 | void mpc83xx_pci_init(int num_buses, struct pci_region **reg); |
75f35209 | 1389 | void mpc83xx_pcislave_unlock(int bus); |
6aa3d3bf | 1390 | void mpc83xx_pcie_init(int num_buses, struct pci_region **reg); |
49ea3b6e SW |
1391 | #endif |
1392 | ||
f046ccd1 | 1393 | #endif /* __MPC83XX_H__ */ |