[people/ms/u-boot.git] / include / mpc85xx.h

/*
 * Copyright 2004, 2007 Freescale Semiconductor.
 * Copyright(c) 2003 Motorola Inc.
 */

#ifndef	__MPC85xx_H__
#define __MPC85xx_H__

#include <asm/fsl_lbc.h>

/* define for common ppc_asm.tmpl */
#define EXC_OFF_SYS_RESET	0x100	/* System reset */
#define _START_OFFSET		0

#if defined(CONFIG_E500)
#include <e500.h>
#endif

/*
 * SCCR - System Clock Control Register, 9-8
 */
#define SCCR_CLPD       0x00000004      /* CPM Low Power Disable */
#define SCCR_DFBRG_MSK  0x00000003      /* Division by BRGCLK Mask */
#define SCCR_DFBRG_SHIFT 0

#define SCCR_DFBRG00    0x00000000      /* BRGCLK division by 4 */
#define SCCR_DFBRG01    0x00000001      /* BRGCLK div by 16 (normal) */
#define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
#define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */

#endif	/* __MPC85xx_H__ */
Commit	Line	Data
42d1f039	1	/*
61a21e98	2	* Copyright 2004, 2007 Freescale Semiconductor.
42d1f039	3	* Copyright(c) 2003 Motorola Inc.
42d1f039 WD	4	*/
	5
	6	#ifndef __MPC85xx_H__
	7	#define __MPC85xx_H__
	8
bf30bb1f AV	9	#include <asm/fsl_lbc.h>
bf30bb1f AV	10
61a21e98 AF	11	/* define for common ppc_asm.tmpl */
	12	#define EXC_OFF_SYS_RESET 0x100 /* System reset */
	13	#define _START_OFFSET 0
42d1f039 WD	14
	15	#if defined(CONFIG_E500)
	16	#include <e500.h>
	17	#endif
	18
0ac6f8b7 WD	19	/*
0ac6f8b7 WD	20	* SCCR - System Clock Control Register, 9-8
42d1f039	21	*/
0ac6f8b7 WD	22	#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
0ac6f8b7 WD	23	#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
42d1f039 WD	24	#define SCCR_DFBRG_SHIFT 0
42d1f039 WD	25
0ac6f8b7 WD	26	#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
	27	#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
	28	#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
	29	#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
42d1f039 WD	30
42d1f039 WD	31	#endif /* __MPC85xx_H__ */