[people/ms/u-boot.git] / include / mtd / cfi_flash.h

/*
 * (C) Copyright 2009
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#ifndef __CFI_FLASH_H__
#define __CFI_FLASH_H__

#define FLASH_CMD_CFI			0x98
#define FLASH_CMD_READ_ID		0x90
#define FLASH_CMD_RESET			0xff
#define FLASH_CMD_BLOCK_ERASE		0x20
#define FLASH_CMD_ERASE_CONFIRM		0xD0
#define FLASH_CMD_WRITE			0x40
#define FLASH_CMD_PROTECT		0x60
#define FLASH_CMD_SETUP			0x60
#define FLASH_CMD_SET_CR_CONFIRM	0x03
#define FLASH_CMD_PROTECT_SET		0x01
#define FLASH_CMD_PROTECT_CLEAR		0xD0
#define FLASH_CMD_CLEAR_STATUS		0x50
#define FLASH_CMD_READ_STATUS		0x70
#define FLASH_CMD_WRITE_TO_BUFFER	0xE8
#define FLASH_CMD_WRITE_BUFFER_PROG	0xE9
#define FLASH_CMD_WRITE_BUFFER_CONFIRM	0xD0

#define FLASH_STATUS_DONE		0x80
#define FLASH_STATUS_ESS		0x40
#define FLASH_STATUS_ECLBS		0x20
#define FLASH_STATUS_PSLBS		0x10
#define FLASH_STATUS_VPENS		0x08
#define FLASH_STATUS_PSS		0x04
#define FLASH_STATUS_DPS		0x02
#define FLASH_STATUS_R			0x01
#define FLASH_STATUS_PROTECT		0x01

#define AMD_CMD_RESET			0xF0
#define AMD_CMD_WRITE			0xA0
#define AMD_CMD_ERASE_START		0x80
#define AMD_CMD_ERASE_SECTOR		0x30
#define AMD_CMD_UNLOCK_START		0xAA
#define AMD_CMD_UNLOCK_ACK		0x55
#define AMD_CMD_WRITE_TO_BUFFER		0x25
#define AMD_CMD_WRITE_BUFFER_CONFIRM	0x29
#define AMD_CMD_SET_PPB_ENTRY		0xC0
#define AMD_CMD_SET_PPB_EXIT_BC1	0x90
#define AMD_CMD_SET_PPB_EXIT_BC2	0x00
#define AMD_CMD_PPB_UNLOCK_BC1		0x80
#define AMD_CMD_PPB_UNLOCK_BC2		0x30
#define AMD_CMD_PPB_LOCK_BC1		0xA0
#define AMD_CMD_PPB_LOCK_BC2		0x00

#define AMD_STATUS_TOGGLE		0x40
#define AMD_STATUS_ERROR		0x20

#define ATM_CMD_UNLOCK_SECT		0x70
#define ATM_CMD_SOFTLOCK_START		0x80
#define ATM_CMD_LOCK_SECT		0x40

#define FLASH_CONTINUATION_CODE		0x7F

#define FLASH_OFFSET_MANUFACTURER_ID	0x00
#define FLASH_OFFSET_DEVICE_ID		0x01
#define FLASH_OFFSET_DEVICE_ID2		0x0E
#define FLASH_OFFSET_DEVICE_ID3		0x0F
#define FLASH_OFFSET_CFI		0x55
#define FLASH_OFFSET_CFI_ALT		0x555
#define FLASH_OFFSET_CFI_RESP		0x10
#define FLASH_OFFSET_PRIMARY_VENDOR	0x13
/* extended query table primary address */
#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR	0x15
#define FLASH_OFFSET_WTOUT		0x1F
#define FLASH_OFFSET_WBTOUT		0x20
#define FLASH_OFFSET_ETOUT		0x21
#define FLASH_OFFSET_CETOUT		0x22
#define FLASH_OFFSET_WMAX_TOUT		0x23
#define FLASH_OFFSET_WBMAX_TOUT		0x24
#define FLASH_OFFSET_EMAX_TOUT		0x25
#define FLASH_OFFSET_CEMAX_TOUT		0x26
#define FLASH_OFFSET_SIZE		0x27
#define FLASH_OFFSET_INTERFACE		0x28
#define FLASH_OFFSET_BUFFER_SIZE	0x2A
#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
#define FLASH_OFFSET_ERASE_REGIONS	0x2D
#define FLASH_OFFSET_PROTECT		0x02
#define FLASH_OFFSET_USER_PROTECTION	0x85
#define FLASH_OFFSET_INTEL_PROTECTION	0x81

#define CFI_CMDSET_NONE			0
#define CFI_CMDSET_INTEL_EXTENDED	1
#define CFI_CMDSET_AMD_STANDARD		2
#define CFI_CMDSET_INTEL_STANDARD	3
#define CFI_CMDSET_AMD_EXTENDED		4
#define CFI_CMDSET_MITSU_STANDARD	256
#define CFI_CMDSET_MITSU_EXTENDED	257
#define CFI_CMDSET_SST			258
#define CFI_CMDSET_INTEL_PROG_REGIONS	512

#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
# undef  FLASH_CMD_RESET
# define FLASH_CMD_RESET	AMD_CMD_RESET /* use AMD-Reset instead */
#endif

#define NUM_ERASE_REGIONS	4 /* max. number of erase regions */

typedef union {
	unsigned char c;
	unsigned short w;
	unsigned long l;
	unsigned long long ll;
} cfiword_t;

/* CFI standard query structure */
struct cfi_qry {
	u8	qry[3];
	u16	p_id;
	u16	p_adr;
	u16	a_id;
	u16	a_adr;
	u8	vcc_min;
	u8	vcc_max;
	u8	vpp_min;
	u8	vpp_max;
	u8	word_write_timeout_typ;
	u8	buf_write_timeout_typ;
	u8	block_erase_timeout_typ;
	u8	chip_erase_timeout_typ;
	u8	word_write_timeout_max;
	u8	buf_write_timeout_max;
	u8	block_erase_timeout_max;
	u8	chip_erase_timeout_max;
	u8	dev_size;
	u16	interface_desc;
	u16	max_buf_write_size;
	u8	num_erase_regions;
	u32	erase_region_info[NUM_ERASE_REGIONS];
} __attribute__((packed));

struct cfi_pri_hdr {
	u8	pri[3];
	u8	major_version;
	u8	minor_version;
} __attribute__((packed));

#ifndef CONFIG_SYS_FLASH_BANKS_LIST
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#endif

/*
 * CFI_MAX_FLASH_BANKS only used for flash_info struct declaration.
 *
 * Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined
 */
#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
#define CONFIG_SYS_MAX_FLASH_BANKS	(cfi_flash_num_flash_banks)
#define CFI_MAX_FLASH_BANKS	CONFIG_SYS_MAX_FLASH_BANKS_DETECT
/* board code can update this variable before CFI detection */
extern int cfi_flash_num_flash_banks;
#else
#define CFI_MAX_FLASH_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
#endif

void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
		     uint offset, u32 cmd);

#endif /* __CFI_FLASH_H__ */
Commit	Line	Data
fa36ae79 SR	1	/*
	2	* (C) Copyright 2009
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	#ifndef __CFI_FLASH_H__
	26	#define __CFI_FLASH_H__
	27
	28	#define FLASH_CMD_CFI 0x98
	29	#define FLASH_CMD_READ_ID 0x90
	30	#define FLASH_CMD_RESET 0xff
	31	#define FLASH_CMD_BLOCK_ERASE 0x20
	32	#define FLASH_CMD_ERASE_CONFIRM 0xD0
	33	#define FLASH_CMD_WRITE 0x40
	34	#define FLASH_CMD_PROTECT 0x60
6f726f95 SR	35	#define FLASH_CMD_SETUP 0x60
6f726f95 SR	36	#define FLASH_CMD_SET_CR_CONFIRM 0x03
fa36ae79 SR	37	#define FLASH_CMD_PROTECT_SET 0x01
	38	#define FLASH_CMD_PROTECT_CLEAR 0xD0
	39	#define FLASH_CMD_CLEAR_STATUS 0x50
	40	#define FLASH_CMD_READ_STATUS 0x70
	41	#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
	42	#define FLASH_CMD_WRITE_BUFFER_PROG 0xE9
	43	#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
	44
	45	#define FLASH_STATUS_DONE 0x80
	46	#define FLASH_STATUS_ESS 0x40
	47	#define FLASH_STATUS_ECLBS 0x20
	48	#define FLASH_STATUS_PSLBS 0x10
	49	#define FLASH_STATUS_VPENS 0x08
	50	#define FLASH_STATUS_PSS 0x04
	51	#define FLASH_STATUS_DPS 0x02
	52	#define FLASH_STATUS_R 0x01
	53	#define FLASH_STATUS_PROTECT 0x01
	54
	55	#define AMD_CMD_RESET 0xF0
	56	#define AMD_CMD_WRITE 0xA0
	57	#define AMD_CMD_ERASE_START 0x80
	58	#define AMD_CMD_ERASE_SECTOR 0x30
	59	#define AMD_CMD_UNLOCK_START 0xAA
	60	#define AMD_CMD_UNLOCK_ACK 0x55
	61	#define AMD_CMD_WRITE_TO_BUFFER 0x25
	62	#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
66863b05 AG	63	#define AMD_CMD_SET_PPB_ENTRY 0xC0
	64	#define AMD_CMD_SET_PPB_EXIT_BC1 0x90
	65	#define AMD_CMD_SET_PPB_EXIT_BC2 0x00
	66	#define AMD_CMD_PPB_UNLOCK_BC1 0x80
	67	#define AMD_CMD_PPB_UNLOCK_BC2 0x30
	68	#define AMD_CMD_PPB_LOCK_BC1 0xA0
	69	#define AMD_CMD_PPB_LOCK_BC2 0x00
fa36ae79 SR	70
	71	#define AMD_STATUS_TOGGLE 0x40
	72	#define AMD_STATUS_ERROR 0x20
	73
	74	#define ATM_CMD_UNLOCK_SECT 0x70
	75	#define ATM_CMD_SOFTLOCK_START 0x80
	76	#define ATM_CMD_LOCK_SECT 0x40
	77
	78	#define FLASH_CONTINUATION_CODE 0x7F
	79
	80	#define FLASH_OFFSET_MANUFACTURER_ID 0x00
e303be2d SR	81	#define FLASH_OFFSET_DEVICE_ID 0x01
	82	#define FLASH_OFFSET_DEVICE_ID2 0x0E
	83	#define FLASH_OFFSET_DEVICE_ID3 0x0F
	84	#define FLASH_OFFSET_CFI 0x55
fa36ae79	85	#define FLASH_OFFSET_CFI_ALT 0x555
e303be2d SR	86	#define FLASH_OFFSET_CFI_RESP 0x10
e303be2d SR	87	#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
fa36ae79	88	/* extended query table primary address */
e303be2d	89	#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
fa36ae79	90	#define FLASH_OFFSET_WTOUT 0x1F
e303be2d SR	91	#define FLASH_OFFSET_WBTOUT 0x20
	92	#define FLASH_OFFSET_ETOUT 0x21
	93	#define FLASH_OFFSET_CETOUT 0x22
	94	#define FLASH_OFFSET_WMAX_TOUT 0x23
	95	#define FLASH_OFFSET_WBMAX_TOUT 0x24
	96	#define FLASH_OFFSET_EMAX_TOUT 0x25
	97	#define FLASH_OFFSET_CEMAX_TOUT 0x26
	98	#define FLASH_OFFSET_SIZE 0x27
	99	#define FLASH_OFFSET_INTERFACE 0x28
	100	#define FLASH_OFFSET_BUFFER_SIZE 0x2A
	101	#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
	102	#define FLASH_OFFSET_ERASE_REGIONS 0x2D
	103	#define FLASH_OFFSET_PROTECT 0x02
fa36ae79 SR	104	#define FLASH_OFFSET_USER_PROTECTION 0x85
	105	#define FLASH_OFFSET_INTEL_PROTECTION 0x81
	106
	107	#define CFI_CMDSET_NONE 0
	108	#define CFI_CMDSET_INTEL_EXTENDED 1
	109	#define CFI_CMDSET_AMD_STANDARD 2
	110	#define CFI_CMDSET_INTEL_STANDARD 3
	111	#define CFI_CMDSET_AMD_EXTENDED 4
	112	#define CFI_CMDSET_MITSU_STANDARD 256
	113	#define CFI_CMDSET_MITSU_EXTENDED 257
	114	#define CFI_CMDSET_SST 258
	115	#define CFI_CMDSET_INTEL_PROG_REGIONS 512
	116
	117	#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
	118	# undef FLASH_CMD_RESET
	119	# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
	120	#endif
	121
	122	#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
	123
	124	typedef union {
	125	unsigned char c;
	126	unsigned short w;
	127	unsigned long l;
	128	unsigned long long ll;
	129	} cfiword_t;
	130
	131	/* CFI standard query structure */
	132	struct cfi_qry {
	133	u8 qry[3];
	134	u16 p_id;
	135	u16 p_adr;
	136	u16 a_id;
	137	u16 a_adr;
	138	u8 vcc_min;
	139	u8 vcc_max;
	140	u8 vpp_min;
	141	u8 vpp_max;
	142	u8 word_write_timeout_typ;
	143	u8 buf_write_timeout_typ;
	144	u8 block_erase_timeout_typ;
	145	u8 chip_erase_timeout_typ;
	146	u8 word_write_timeout_max;
	147	u8 buf_write_timeout_max;
	148	u8 block_erase_timeout_max;
	149	u8 chip_erase_timeout_max;
	150	u8 dev_size;
	151	u16 interface_desc;
	152	u16 max_buf_write_size;
	153	u8 num_erase_regions;
	154	u32 erase_region_info[NUM_ERASE_REGIONS];
	155	} __attribute__((packed));
	156
	157	struct cfi_pri_hdr {
	158	u8 pri[3];
	159	u8 major_version;
	160	u8 minor_version;
	161	} __attribute__((packed));
	162
ca5def3f SR	163	#ifndef CONFIG_SYS_FLASH_BANKS_LIST
	164	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	165	#endif
	166
	167	/*
	168	* CFI_MAX_FLASH_BANKS only used for flash_info struct declaration.
	169	*
	170	* Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined
	171	*/
	172	#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
	173	#define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks)
	174	#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT
	175	/* board code can update this variable before CFI detection */
	176	extern int cfi_flash_num_flash_banks;
	177	#else
	178	#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS
	179	#endif
	180
fa36ae79 SR	181	void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
	182	uint offset, u32 cmd);
	183
	184	#endif /* __CFI_FLASH_H__ */