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89973f8a BW |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Benjamin Warren, biggerbadderben@gmail.com | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
89973f8a BW |
6 | */ |
7 | ||
8 | /* | |
9 | * netdev.h - definitions an prototypes for network devices | |
10 | */ | |
11 | ||
12 | #ifndef _NETDEV_H_ | |
13 | #define _NETDEV_H_ | |
14 | ||
15 | /* | |
16 | * Board and CPU-specific initialization functions | |
17 | * board_eth_init() has highest priority. cpu_eth_init() only | |
18 | * gets called if board_eth_init() isn't instantiated or fails. | |
19 | * Return values: | |
20 | * 0: success | |
21 | * -1: failure | |
22 | */ | |
23 | ||
24 | int board_eth_init(bd_t *bis); | |
25 | int cpu_eth_init(bd_t *bis); | |
26 | ||
27 | /* Driver initialization prototypes */ | |
c041e9d2 | 28 | int at91emac_register(bd_t *bis, unsigned long iobase); |
bd6ce9d1 WD |
29 | int au1x00_enet_initialize(bd_t*); |
30 | int ax88180_initialize(bd_t *bis); | |
799e125c | 31 | int bcm_sf2_eth_register(bd_t *bis, u8 dev_num); |
89973f8a | 32 | int bfin_EMAC_initialize(bd_t *bis); |
efdd7319 | 33 | int calxedaxgmac_initialize(u32 id, ulong base_addr); |
b1c0eaac | 34 | int cs8900_initialize(u8 dev_num, int base_addr); |
8453587e | 35 | int davinci_emac_initialize(void); |
bd6ce9d1 | 36 | int dc21x4x_initialize(bd_t *bis); |
92a190aa | 37 | int designware_initialize(ulong base_addr, u32 interface); |
bd6ce9d1 | 38 | int dm9000_initialize(bd_t *bis); |
62cbc408 | 39 | int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); |
ad3381cf | 40 | int e1000_initialize(bd_t *bis); |
10efa024 | 41 | int eepro100_initialize(bd_t *bis); |
a61a8196 RM |
42 | int enc28j60_initialize(unsigned int bus, unsigned int cs, |
43 | unsigned int max_hz, unsigned int mode); | |
594d57d0 | 44 | int ep93xx_eth_initialize(u8 dev_num, int base_addr); |
164846ee | 45 | int eth_3com_initialize (bd_t * bis); |
bd6ce9d1 | 46 | int ethoc_initialize(u8 dev_num, int base_addr); |
3456a148 | 47 | int fec_initialize (bd_t *bis); |
bd6ce9d1 | 48 | int fecmxc_initialize(bd_t *bis); |
9e27e9dc | 49 | int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr); |
b3dbf4a5 | 50 | int ftgmac100_initialize(bd_t *bits); |
750326e5 | 51 | int ftmac100_initialize(bd_t *bits); |
c4775476 | 52 | int ftmac110_initialize(bd_t *bits); |
89973f8a | 53 | int greth_initialize(bd_t *bis); |
6aca145e | 54 | void gt6426x_eth_initialize(bd_t *bis); |
45a1693a | 55 | int ks8851_mll_initialize(u8 dev_num, int base_addr); |
b7ad4109 | 56 | int lan91c96_initialize(u8 dev_num, int base_addr); |
ac2916a2 | 57 | int lpc32xx_eth_initialize(bd_t *bis); |
89973f8a BW |
58 | int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); |
59 | int mcdmafec_initialize(bd_t *bis); | |
60 | int mcffec_initialize(bd_t *bis); | |
a0aad08f | 61 | int mpc512x_fec_initialize(bd_t *bis); |
e1d7480b | 62 | int mpc5xxx_fec_initialize(bd_t *bis); |
ba705b5b | 63 | int mpc82xx_scc_enet_initialize(bd_t *bis); |
d44265ad | 64 | int mvgbe_initialize(bd_t *bis); |
19fc2eae | 65 | int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr); |
b902b8dd | 66 | int natsemi_initialize(bd_t *bis); |
d0201692 | 67 | int ne2k_register(void); |
cc94074e | 68 | int npe_initialize(bd_t *bis); |
19403633 | 69 | int ns8382x_initialize(bd_t *bis); |
e3090534 | 70 | int pcnet_initialize(bd_t *bis); |
25a85906 | 71 | int ppc_4xx_eth_initialize (bd_t *bis); |
0b252f50 | 72 | int rtl8139_initialize(bd_t *bis); |
02d69891 | 73 | int rtl8169_initialize(bd_t *bis); |
9eb79bd8 | 74 | int scc_initialize(bd_t *bis); |
bd6ce9d1 | 75 | int sh_eth_initialize(bd_t *bis); |
89973f8a | 76 | int skge_initialize(bd_t *bis); |
7194ab80 | 77 | int smc91111_initialize(u8 dev_num, int base_addr); |
bd6ce9d1 | 78 | int smc911x_initialize(u8 dev_num, int base_addr); |
ccdd12f8 | 79 | int tsi108_eth_initialize(bd_t *bis); |
2b5243fc | 80 | int uec_standard_init(bd_t *bis); |
89973f8a | 81 | int uli526x_initialize(bd_t *bis); |
79788bb1 | 82 | int armada100_fec_register(unsigned long base_addr); |
4f1ec4c1 MS |
83 | int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, |
84 | unsigned long dma_addr); | |
0c9c99a2 | 85 | int xilinx_emaclite_of_init(const void *blob); |
c1044a1e MS |
86 | int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, |
87 | int txpp, int rxpp); | |
df482650 SL |
88 | int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, |
89 | unsigned long ctrl_addr); | |
f88a6869 | 90 | int zynq_gem_of_init(const void *blob); |
58405378 MS |
91 | int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, |
92 | int phy_addr, u32 emio); | |
df482650 SL |
93 | /* |
94 | * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface | |
95 | * exported by a public hader file, we need a global definition at this point. | |
96 | */ | |
97 | #if defined(CONFIG_XILINX_LL_TEMAC) | |
98 | #define XILINX_LL_TEMAC_M_FIFO 0 /* use FIFO Ctrl */ | |
99 | #define XILINX_LL_TEMAC_M_SDMA_PLB (1 << 0)/* use SDMA Ctrl via PLB */ | |
100 | #define XILINX_LL_TEMAC_M_SDMA_DCR (1 << 1)/* use SDMA Ctrl via DCR */ | |
101 | #endif | |
89973f8a BW |
102 | |
103 | /* Boards with PCI network controllers can call this from their board_eth_init() | |
104 | * function to initialize whatever's on board. | |
105 | * Return value is total # of devices found */ | |
106 | ||
107 | static inline int pci_eth_init(bd_t *bis) | |
108 | { | |
109 | int num = 0; | |
e3090534 | 110 | |
10efa024 BW |
111 | #ifdef CONFIG_PCI |
112 | ||
113 | #ifdef CONFIG_EEPRO100 | |
114 | num += eepro100_initialize(bis); | |
115 | #endif | |
8ca0b3f9 BW |
116 | #ifdef CONFIG_TULIP |
117 | num += dc21x4x_initialize(bis); | |
118 | #endif | |
ad3381cf BW |
119 | #ifdef CONFIG_E1000 |
120 | num += e1000_initialize(bis); | |
121 | #endif | |
e3090534 BW |
122 | #ifdef CONFIG_PCNET |
123 | num += pcnet_initialize(bis); | |
124 | #endif | |
b902b8dd BW |
125 | #ifdef CONFIG_NATSEMI |
126 | num += natsemi_initialize(bis); | |
127 | #endif | |
19403633 BW |
128 | #ifdef CONFIG_NS8382X |
129 | num += ns8382x_initialize(bis); | |
130 | #endif | |
0b252f50 BW |
131 | #if defined(CONFIG_RTL8139) |
132 | num += rtl8139_initialize(bis); | |
133 | #endif | |
02d69891 BW |
134 | #if defined(CONFIG_RTL8169) |
135 | num += rtl8169_initialize(bis); | |
136 | #endif | |
b11f664f | 137 | #if defined(CONFIG_ULI526X) |
89973f8a BW |
138 | num += uli526x_initialize(bis); |
139 | #endif | |
10efa024 BW |
140 | |
141 | #endif /* CONFIG_PCI */ | |
89973f8a BW |
142 | return num; |
143 | } | |
144 | ||
6f51deb7 PW |
145 | /* |
146 | * Boards with mv88e61xx switch can use this by defining | |
147 | * CONFIG_MV88E61XX_SWITCH in respective board configheader file | |
148 | * the stuct and enums here are used to specify switch configuration params | |
149 | */ | |
150 | #if defined(CONFIG_MV88E61XX_SWITCH) | |
0a16ea59 AA |
151 | |
152 | /* constants for any 88E61xx switch */ | |
153 | #define MV88E61XX_MAX_PORTS_NUM 6 | |
6f51deb7 PW |
154 | |
155 | enum mv88e61xx_cfg_mdip { | |
156 | MV88E61XX_MDIP_NOCHANGE, | |
157 | MV88E61XX_MDIP_REVERSE | |
158 | }; | |
159 | ||
160 | enum mv88e61xx_cfg_ledinit { | |
161 | MV88E61XX_LED_INIT_DIS, | |
162 | MV88E61XX_LED_INIT_EN | |
163 | }; | |
164 | ||
165 | enum mv88e61xx_cfg_rgmiid { | |
166 | MV88E61XX_RGMII_DELAY_DIS, | |
167 | MV88E61XX_RGMII_DELAY_EN | |
168 | }; | |
169 | ||
170 | enum mv88e61xx_cfg_prtstt { | |
171 | MV88E61XX_PORTSTT_DISABLED, | |
172 | MV88E61XX_PORTSTT_BLOCKING, | |
173 | MV88E61XX_PORTSTT_LEARNING, | |
174 | MV88E61XX_PORTSTT_FORWARDING | |
175 | }; | |
176 | ||
177 | struct mv88e61xx_config { | |
178 | char *name; | |
0a16ea59 | 179 | u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; |
6f51deb7 PW |
180 | enum mv88e61xx_cfg_rgmiid rgmii_delay; |
181 | enum mv88e61xx_cfg_prtstt portstate; | |
182 | enum mv88e61xx_cfg_ledinit led_init; | |
183 | enum mv88e61xx_cfg_mdip mdip; | |
184 | u32 ports_enabled; | |
185 | u8 cpuport; | |
186 | }; | |
187 | ||
0a16ea59 AA |
188 | /* |
189 | * Common mappings for Internal VLANs | |
190 | * These mappings consider that all ports are useable; the driver | |
191 | * will mask inexistent/unused ports. | |
192 | */ | |
193 | ||
194 | /* Switch mode : routes any port to any port */ | |
195 | #define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } | |
196 | ||
197 | /* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ | |
198 | #define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } | |
199 | ||
6f51deb7 PW |
200 | int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); |
201 | #endif /* CONFIG_MV88E61XX_SWITCH */ | |
202 | ||
fe428b90 TK |
203 | struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id); |
204 | #ifdef CONFIG_PHYLIB | |
205 | struct phy_device; | |
206 | int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
207 | struct mii_dev *bus, struct phy_device *phydev); | |
208 | #else | |
2e5f4421 MV |
209 | /* |
210 | * Allow FEC to fine-tune MII configuration on boards which require this. | |
211 | */ | |
212 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); | |
fe428b90 | 213 | #endif |
2e5f4421 | 214 | |
89973f8a | 215 | #endif /* _NETDEV_H_ */ |