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5c952cf0 WD |
1 | /* |
2 | * (C) Copyright 2004, Psyent Corporation <www.psyent.com> | |
3 | * Scott McNutt <smcnutt@psyent.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5c952cf0 WD |
6 | */ |
7 | ||
8 | #ifndef __NIOS2_H__ | |
9 | #define __NIOS2_H__ | |
10 | ||
11 | /*------------------------------------------------------------------------ | |
12 | * Control registers -- use with wrctl() & rdctl() | |
13 | *----------------------------------------------------------------------*/ | |
14 | #define CTL_STATUS 0 /* Processor status reg */ | |
15 | #define CTL_ESTATUS 1 /* Exception status reg */ | |
16 | #define CTL_BSTATUS 2 /* Break status reg */ | |
17 | #define CTL_IENABLE 3 /* Interrut enable reg */ | |
18 | #define CTL_IPENDING 4 /* Interrut pending reg */ | |
19 | ||
20 | /*------------------------------------------------------------------------ | |
21 | * Access to control regs | |
22 | *----------------------------------------------------------------------*/ | |
5c952cf0 | 23 | |
4f63bfb6 TC |
24 | #define rdctl(reg) __builtin_rdctl(reg) |
25 | #define wrctl(reg, val) __builtin_wrctl(reg, val) | |
5c952cf0 WD |
26 | |
27 | /*------------------------------------------------------------------------ | |
28 | * Control reg bit masks | |
29 | *----------------------------------------------------------------------*/ | |
30 | #define STATUS_IE (1<<0) /* Interrupt enable */ | |
31 | #define STATUS_U (1<<1) /* User-mode */ | |
32 | ||
33 | /*------------------------------------------------------------------------ | |
34 | * Bit-31 Cache bypass -- only valid for data access. When data cache | |
35 | * is not implemented, bit 31 is ignored for compatibility. | |
36 | *----------------------------------------------------------------------*/ | |
37 | #define CACHE_BYPASS(a) ((a) | 0x80000000) | |
38 | #define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) | |
39 | ||
40 | #endif /* __NIOS2_H__ */ |