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a06ea964 NC |
1 | /* AArch64 assembler/disassembler support. |
2 | ||
82704155 | 3 | Copyright (C) 2009-2019 Free Software Foundation, Inc. |
a06ea964 NC |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GNU Binutils. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the license, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; see the file COPYING3. If not, | |
20 | see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef OPCODE_AARCH64_H | |
23 | #define OPCODE_AARCH64_H | |
24 | ||
25 | #include "bfd.h" | |
26 | #include "bfd_stdint.h" | |
27 | #include <assert.h> | |
28 | #include <stdlib.h> | |
29 | ||
d3e12b29 YQ |
30 | #ifdef __cplusplus |
31 | extern "C" { | |
32 | #endif | |
33 | ||
a06ea964 NC |
34 | /* The offset for pc-relative addressing is currently defined to be 0. */ |
35 | #define AARCH64_PCREL_OFFSET 0 | |
36 | ||
37 | typedef uint32_t aarch64_insn; | |
38 | ||
39 | /* The following bitmasks control CPU features. */ | |
c0e7cef7 NC |
40 | #define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */ |
41 | #define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */ | |
b6b9ca0c TC |
42 | #define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */ |
43 | #define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */ | |
44 | #define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */ | |
a06ea964 | 45 | #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ |
acb787b0 | 46 | #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ |
1924ff75 | 47 | #define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */ |
a06ea964 NC |
48 | #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ |
49 | #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ | |
50 | #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ | |
e60bb1dd | 51 | #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ |
ee804238 | 52 | #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ |
f21cce2c | 53 | #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ |
290806fd | 54 | #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ |
9e1f0fa7 | 55 | #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ |
250aafa4 | 56 | #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ |
af117b3c | 57 | #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ |
c8a6db6f | 58 | #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ |
73af8ed6 | 59 | #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ |
c0890d26 | 60 | #define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */ |
d74d4880 | 61 | #define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */ |
f482d304 | 62 | #define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */ |
65a55fbb | 63 | #define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */ |
d0f7791c | 64 | #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */ |
70d56181 | 65 | #define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */ |
a06ea964 | 66 | |
13c60ad7 SD |
67 | /* Flag Manipulation insns. */ |
68 | #define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL | |
69 | /* FRINT[32,64][Z,X] insns. */ | |
70 | #define AARCH64_FEATURE_FRINTTS 0x8000000000ULL | |
68dfbb92 SD |
71 | /* SB instruction. */ |
72 | #define AARCH64_FEATURE_SB 0x10000000000ULL | |
2ac435d4 SD |
73 | /* Execution and Data Prediction Restriction instructions. */ |
74 | #define AARCH64_FEATURE_PREDRES 0x20000000000ULL | |
3fd229a4 SD |
75 | /* DC CVADP. */ |
76 | #define AARCH64_FEATURE_CVADP 0x40000000000ULL | |
af4bcb4c SD |
77 | /* Random Number instructions. */ |
78 | #define AARCH64_FEATURE_RNG 0x80000000000ULL | |
ff605452 SD |
79 | /* BTI instructions. */ |
80 | #define AARCH64_FEATURE_BTI 0x100000000000ULL | |
a97330e7 SD |
81 | /* SCXTNUM_ELx. */ |
82 | #define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL | |
83 | /* ID_PFR2 instructions. */ | |
84 | #define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL | |
104fefee SD |
85 | /* SSBS mechanism enabled. */ |
86 | #define AARCH64_FEATURE_SSBS 0x800000000000ULL | |
73b605ec SD |
87 | /* Memory Tagging Extension. */ |
88 | #define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL | |
b83b4b13 SD |
89 | /* Transactional Memory Extension. */ |
90 | #define AARCH64_FEATURE_TME 0x2000000000000ULL | |
13c60ad7 | 91 | |
a06ea964 NC |
92 | /* Architectures are the sum of the base and extensions. */ |
93 | #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ | |
94 | AARCH64_FEATURE_FP \ | |
95 | | AARCH64_FEATURE_SIMD) | |
1924ff75 SN |
96 | #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ |
97 | AARCH64_FEATURE_CRC \ | |
250aafa4 | 98 | | AARCH64_FEATURE_V8_1 \ |
88f0ea34 MW |
99 | | AARCH64_FEATURE_LSE \ |
100 | | AARCH64_FEATURE_PAN \ | |
101 | | AARCH64_FEATURE_LOR \ | |
102 | | AARCH64_FEATURE_RDMA) | |
1924ff75 | 103 | #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \ |
acb787b0 | 104 | AARCH64_FEATURE_V8_2 \ |
1924ff75 SN |
105 | | AARCH64_FEATURE_RAS) |
106 | #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \ | |
d74d4880 | 107 | AARCH64_FEATURE_V8_3 \ |
f482d304 RS |
108 | | AARCH64_FEATURE_RCPC \ |
109 | | AARCH64_FEATURE_COMPNUM) | |
b6b9ca0c | 110 | #define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \ |
981b557a | 111 | AARCH64_FEATURE_V8_4 \ |
d0f7791c TC |
112 | | AARCH64_FEATURE_DOTPROD \ |
113 | | AARCH64_FEATURE_F16_FML) | |
70d56181 | 114 | #define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ |
13c60ad7 SD |
115 | AARCH64_FEATURE_V8_5 \ |
116 | | AARCH64_FEATURE_FLAGMANIP \ | |
68dfbb92 | 117 | | AARCH64_FEATURE_FRINTTS \ |
2ac435d4 | 118 | | AARCH64_FEATURE_SB \ |
3fd229a4 | 119 | | AARCH64_FEATURE_PREDRES \ |
ff605452 | 120 | | AARCH64_FEATURE_CVADP \ |
a97330e7 SD |
121 | | AARCH64_FEATURE_BTI \ |
122 | | AARCH64_FEATURE_SCXTNUM \ | |
104fefee SD |
123 | | AARCH64_FEATURE_ID_PFR2 \ |
124 | | AARCH64_FEATURE_SSBS) | |
70d56181 | 125 | |
88f0ea34 | 126 | |
a06ea964 NC |
127 | #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) |
128 | #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ | |
129 | ||
130 | /* CPU-specific features. */ | |
21b81e67 | 131 | typedef unsigned long long aarch64_feature_set; |
a06ea964 | 132 | |
93d8990c SN |
133 | #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ |
134 | ((~(CPU) & (FEAT)) == 0) | |
135 | ||
136 | #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ | |
a06ea964 NC |
137 | (((CPU) & (FEAT)) != 0) |
138 | ||
93d8990c SN |
139 | #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ |
140 | AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) | |
141 | ||
a06ea964 NC |
142 | #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ |
143 | do \ | |
144 | { \ | |
145 | (TARG) = (F1) | (F2); \ | |
146 | } \ | |
147 | while (0) | |
148 | ||
149 | #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ | |
150 | do \ | |
151 | { \ | |
152 | (TARG) = (F1) &~ (F2); \ | |
153 | } \ | |
154 | while (0) | |
155 | ||
156 | #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) | |
157 | ||
a06ea964 NC |
158 | enum aarch64_operand_class |
159 | { | |
160 | AARCH64_OPND_CLASS_NIL, | |
161 | AARCH64_OPND_CLASS_INT_REG, | |
162 | AARCH64_OPND_CLASS_MODIFIED_REG, | |
163 | AARCH64_OPND_CLASS_FP_REG, | |
164 | AARCH64_OPND_CLASS_SIMD_REG, | |
165 | AARCH64_OPND_CLASS_SIMD_ELEMENT, | |
166 | AARCH64_OPND_CLASS_SISD_REG, | |
167 | AARCH64_OPND_CLASS_SIMD_REGLIST, | |
f11ad6bc RS |
168 | AARCH64_OPND_CLASS_SVE_REG, |
169 | AARCH64_OPND_CLASS_PRED_REG, | |
a06ea964 NC |
170 | AARCH64_OPND_CLASS_ADDRESS, |
171 | AARCH64_OPND_CLASS_IMMEDIATE, | |
172 | AARCH64_OPND_CLASS_SYSTEM, | |
68a64283 | 173 | AARCH64_OPND_CLASS_COND, |
a06ea964 NC |
174 | }; |
175 | ||
176 | /* Operand code that helps both parsing and coding. | |
177 | Keep AARCH64_OPERANDS synced. */ | |
178 | ||
179 | enum aarch64_opnd | |
180 | { | |
181 | AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ | |
182 | ||
183 | AARCH64_OPND_Rd, /* Integer register as destination. */ | |
184 | AARCH64_OPND_Rn, /* Integer register as source. */ | |
185 | AARCH64_OPND_Rm, /* Integer register as source. */ | |
186 | AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ | |
187 | AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ | |
bd7ceb8d | 188 | AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ |
a06ea964 NC |
189 | AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ |
190 | AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ | |
191 | AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ | |
192 | ||
193 | AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ | |
194 | AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ | |
c84364ec | 195 | AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */ |
ee804238 | 196 | AARCH64_OPND_PAIRREG, /* Paired register operand. */ |
a06ea964 NC |
197 | AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ |
198 | AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ | |
199 | ||
200 | AARCH64_OPND_Fd, /* Floating-point Fd. */ | |
201 | AARCH64_OPND_Fn, /* Floating-point Fn. */ | |
202 | AARCH64_OPND_Fm, /* Floating-point Fm. */ | |
203 | AARCH64_OPND_Fa, /* Floating-point Fa. */ | |
204 | AARCH64_OPND_Ft, /* Floating-point Ft. */ | |
205 | AARCH64_OPND_Ft2, /* Floating-point Ft2. */ | |
206 | ||
207 | AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ | |
208 | AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ | |
209 | AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ | |
210 | ||
f42f1a1d | 211 | AARCH64_OPND_Va, /* AdvSIMD Vector Va. */ |
a06ea964 NC |
212 | AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ |
213 | AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ | |
214 | AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ | |
215 | AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ | |
216 | AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ | |
217 | AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ | |
218 | AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ | |
219 | AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ | |
369c9167 TC |
220 | AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when |
221 | qualifier is S_H. */ | |
a06ea964 NC |
222 | AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ |
223 | AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ | |
224 | AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single | |
225 | structure to all lanes. */ | |
226 | AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ | |
227 | ||
a6a51754 RL |
228 | AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ |
229 | AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ | |
a06ea964 NC |
230 | |
231 | AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ | |
f42f1a1d | 232 | AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */ |
a06ea964 NC |
233 | AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ |
234 | AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ | |
235 | AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ | |
236 | AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ | |
237 | AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ | |
238 | AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction | |
239 | (no encoding). */ | |
240 | AARCH64_OPND_IMM0, /* Immediate for #0. */ | |
241 | AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ | |
242 | AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ | |
243 | AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ | |
244 | AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ | |
245 | AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ | |
246 | AARCH64_OPND_IMM, /* Immediate. */ | |
f42f1a1d | 247 | AARCH64_OPND_IMM_2, /* Immediate. */ |
a06ea964 NC |
248 | AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ |
249 | AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ | |
250 | AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ | |
193614f2 | 251 | AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */ |
a06ea964 | 252 | AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ |
193614f2 | 253 | AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */ |
a06ea964 NC |
254 | AARCH64_OPND_BIT_NUM, /* Immediate. */ |
255 | AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ | |
256 | AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ | |
e950b345 | 257 | AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ |
a06ea964 NC |
258 | AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for |
259 | each condition flag. */ | |
260 | ||
261 | AARCH64_OPND_LIMM, /* Logical Immediate. */ | |
262 | AARCH64_OPND_AIMM, /* Arithmetic immediate. */ | |
263 | AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ | |
264 | AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ | |
265 | AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ | |
c2c4ff8d SN |
266 | AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */ |
267 | AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */ | |
268 | AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */ | |
a06ea964 NC |
269 | |
270 | AARCH64_OPND_COND, /* Standard condition as the last operand. */ | |
68a64283 | 271 | AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ |
a06ea964 NC |
272 | |
273 | AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ | |
274 | AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ | |
275 | AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ | |
276 | AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ | |
277 | AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ | |
278 | ||
279 | AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ | |
280 | AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ | |
281 | AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ | |
282 | AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ | |
283 | AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is | |
284 | negative or unaligned and there is | |
285 | no writeback allowed. This operand code | |
286 | is only used to support the programmer- | |
287 | friendly feature of using LDR/STR as the | |
288 | the mnemonic name for LDUR/STUR instructions | |
289 | wherever there is no ambiguity. */ | |
3f06e550 | 290 | AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ |
fb3265b3 SD |
291 | AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of |
292 | 16) immediate. */ | |
a06ea964 | 293 | AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ |
fb3265b3 SD |
294 | AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of |
295 | 16) immediate. */ | |
a06ea964 | 296 | AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ |
f42f1a1d | 297 | AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */ |
a06ea964 NC |
298 | AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ |
299 | ||
300 | AARCH64_OPND_SYSREG, /* System register operand. */ | |
301 | AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ | |
302 | AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ | |
303 | AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ | |
304 | AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ | |
305 | AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ | |
2ac435d4 | 306 | AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */ |
a06ea964 NC |
307 | AARCH64_OPND_BARRIER, /* Barrier operand. */ |
308 | AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ | |
309 | AARCH64_OPND_PRFOP, /* Prefetch operation. */ | |
1e6f4800 | 310 | AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ |
ff605452 | 311 | AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ |
f11ad6bc | 312 | |
582e12bf | 313 | AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ |
98907a70 RS |
314 | AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ |
315 | AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */ | |
316 | AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */ | |
317 | AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */ | |
318 | AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */ | |
319 | AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */ | |
4df068de RS |
320 | AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */ |
321 | AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ | |
322 | AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ | |
323 | AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ | |
c8d59609 | 324 | AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ |
4df068de RS |
325 | AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ |
326 | AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ | |
327 | AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ | |
328 | AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ | |
329 | AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ | |
330 | AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ | |
331 | AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ | |
332 | AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ | |
333 | AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ | |
334 | AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ | |
335 | AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */ | |
336 | AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */ | |
337 | AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. | |
338 | Bit 14 controls S/U choice. */ | |
339 | AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. | |
340 | Bit 22 controls S/U choice. */ | |
341 | AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. | |
342 | Bit 14 controls S/U choice. */ | |
343 | AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. | |
344 | Bit 22 controls S/U choice. */ | |
345 | AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. | |
346 | Bit 14 controls S/U choice. */ | |
347 | AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. | |
348 | Bit 22 controls S/U choice. */ | |
349 | AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. | |
350 | Bit 14 controls S/U choice. */ | |
351 | AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. | |
352 | Bit 22 controls S/U choice. */ | |
353 | AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */ | |
354 | AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */ | |
355 | AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */ | |
356 | AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */ | |
357 | AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ | |
358 | AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ | |
359 | AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ | |
e950b345 RS |
360 | AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */ |
361 | AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */ | |
165d4950 RS |
362 | AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */ |
363 | AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */ | |
364 | AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */ | |
365 | AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */ | |
582e12bf RS |
366 | AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */ |
367 | AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */ | |
e950b345 RS |
368 | AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ |
369 | AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ | |
370 | AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ | |
245d2e3f | 371 | AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ |
2442d846 | 372 | AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ |
245d2e3f | 373 | AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ |
f11ad6bc RS |
374 | AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ |
375 | AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ | |
376 | AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ | |
377 | AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ | |
378 | AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ | |
379 | AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ | |
380 | AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ | |
381 | AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ | |
047cd301 RS |
382 | AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */ |
383 | AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ | |
e950b345 RS |
384 | AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ |
385 | AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ | |
386 | AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ | |
387 | AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ | |
388 | AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ | |
389 | AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ | |
390 | AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ | |
391 | AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */ | |
392 | AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */ | |
393 | AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ | |
394 | AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ | |
395 | AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ | |
047cd301 RS |
396 | AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ |
397 | AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ | |
398 | AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ | |
399 | AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ | |
f11ad6bc RS |
400 | AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ |
401 | AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ | |
402 | AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ | |
403 | AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ | |
404 | AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ | |
582e12bf RS |
405 | AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ |
406 | AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ | |
407 | AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ | |
f11ad6bc RS |
408 | AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ |
409 | AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ | |
410 | AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ | |
411 | AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ | |
412 | AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ | |
b83b4b13 | 413 | AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ |
f42f1a1d | 414 | AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ |
a06ea964 NC |
415 | }; |
416 | ||
417 | /* Qualifier constrains an operand. It either specifies a variant of an | |
418 | operand type or limits values available to an operand type. | |
419 | ||
420 | N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ | |
421 | ||
422 | enum aarch64_opnd_qualifier | |
423 | { | |
424 | /* Indicating no further qualification on an operand. */ | |
425 | AARCH64_OPND_QLF_NIL, | |
426 | ||
427 | /* Qualifying an operand which is a general purpose (integer) register; | |
428 | indicating the operand data size or a specific register. */ | |
429 | AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ | |
430 | AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ | |
431 | AARCH64_OPND_QLF_WSP, /* WSP. */ | |
432 | AARCH64_OPND_QLF_SP, /* SP. */ | |
433 | ||
434 | /* Qualifying an operand which is a floating-point register, a SIMD | |
435 | vector element or a SIMD vector element list; indicating operand data | |
436 | size or the size of each SIMD vector element in the case of a SIMD | |
437 | vector element list. | |
438 | These qualifiers are also used to qualify an address operand to | |
439 | indicate the size of data element a load/store instruction is | |
440 | accessing. | |
441 | They are also used for the immediate shift operand in e.g. SSHR. Such | |
442 | a use is only for the ease of operand encoding/decoding and qualifier | |
443 | sequence matching; such a use should not be applied widely; use the value | |
444 | constraint qualifiers for immediate operands wherever possible. */ | |
445 | AARCH64_OPND_QLF_S_B, | |
446 | AARCH64_OPND_QLF_S_H, | |
447 | AARCH64_OPND_QLF_S_S, | |
448 | AARCH64_OPND_QLF_S_D, | |
449 | AARCH64_OPND_QLF_S_Q, | |
00c2093f TC |
450 | /* This type qualifier has a special meaning in that it means that 4 x 1 byte |
451 | are selected by the instruction. Other than that it has no difference | |
452 | with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical | |
453 | reasons and is an exception from normal AArch64 disassembly scheme. */ | |
454 | AARCH64_OPND_QLF_S_4B, | |
a06ea964 NC |
455 | |
456 | /* Qualifying an operand which is a SIMD vector register or a SIMD vector | |
457 | register list; indicating register shape. | |
458 | They are also used for the immediate shift operand in e.g. SSHR. Such | |
459 | a use is only for the ease of operand encoding/decoding and qualifier | |
460 | sequence matching; such a use should not be applied widely; use the value | |
461 | constraint qualifiers for immediate operands wherever possible. */ | |
a3b3345a | 462 | AARCH64_OPND_QLF_V_4B, |
a06ea964 NC |
463 | AARCH64_OPND_QLF_V_8B, |
464 | AARCH64_OPND_QLF_V_16B, | |
3067d3b9 | 465 | AARCH64_OPND_QLF_V_2H, |
a06ea964 NC |
466 | AARCH64_OPND_QLF_V_4H, |
467 | AARCH64_OPND_QLF_V_8H, | |
468 | AARCH64_OPND_QLF_V_2S, | |
469 | AARCH64_OPND_QLF_V_4S, | |
470 | AARCH64_OPND_QLF_V_1D, | |
471 | AARCH64_OPND_QLF_V_2D, | |
472 | AARCH64_OPND_QLF_V_1Q, | |
473 | ||
d50c751e RS |
474 | AARCH64_OPND_QLF_P_Z, |
475 | AARCH64_OPND_QLF_P_M, | |
fb3265b3 SD |
476 | |
477 | /* Used in scaled signed immediate that are scaled by a Tag granule | |
478 | like in stg, st2g, etc. */ | |
479 | AARCH64_OPND_QLF_imm_tag, | |
d50c751e | 480 | |
a06ea964 | 481 | /* Constraint on value. */ |
a6a51754 | 482 | AARCH64_OPND_QLF_CR, /* CRn, CRm. */ |
a06ea964 NC |
483 | AARCH64_OPND_QLF_imm_0_7, |
484 | AARCH64_OPND_QLF_imm_0_15, | |
485 | AARCH64_OPND_QLF_imm_0_31, | |
486 | AARCH64_OPND_QLF_imm_0_63, | |
487 | AARCH64_OPND_QLF_imm_1_32, | |
488 | AARCH64_OPND_QLF_imm_1_64, | |
489 | ||
490 | /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros | |
491 | or shift-ones. */ | |
492 | AARCH64_OPND_QLF_LSL, | |
493 | AARCH64_OPND_QLF_MSL, | |
494 | ||
495 | /* Special qualifier helping retrieve qualifier information during the | |
496 | decoding time (currently not in use). */ | |
497 | AARCH64_OPND_QLF_RETRIEVE, | |
498 | }; | |
499 | \f | |
500 | /* Instruction class. */ | |
501 | ||
502 | enum aarch64_insn_class | |
503 | { | |
504 | addsub_carry, | |
505 | addsub_ext, | |
506 | addsub_imm, | |
507 | addsub_shift, | |
508 | asimdall, | |
509 | asimddiff, | |
510 | asimdelem, | |
511 | asimdext, | |
512 | asimdimm, | |
513 | asimdins, | |
514 | asimdmisc, | |
515 | asimdperm, | |
516 | asimdsame, | |
517 | asimdshf, | |
518 | asimdtbl, | |
519 | asisddiff, | |
520 | asisdelem, | |
521 | asisdlse, | |
522 | asisdlsep, | |
523 | asisdlso, | |
524 | asisdlsop, | |
525 | asisdmisc, | |
526 | asisdone, | |
527 | asisdpair, | |
528 | asisdsame, | |
529 | asisdshf, | |
530 | bitfield, | |
531 | branch_imm, | |
532 | branch_reg, | |
533 | compbranch, | |
534 | condbranch, | |
535 | condcmp_imm, | |
536 | condcmp_reg, | |
537 | condsel, | |
538 | cryptoaes, | |
539 | cryptosha2, | |
540 | cryptosha3, | |
541 | dp_1src, | |
542 | dp_2src, | |
543 | dp_3src, | |
544 | exception, | |
545 | extract, | |
546 | float2fix, | |
547 | float2int, | |
548 | floatccmp, | |
549 | floatcmp, | |
550 | floatdp1, | |
551 | floatdp2, | |
552 | floatdp3, | |
553 | floatimm, | |
554 | floatsel, | |
555 | ldst_immpost, | |
556 | ldst_immpre, | |
557 | ldst_imm9, /* immpost or immpre */ | |
3f06e550 | 558 | ldst_imm10, /* LDRAA/LDRAB */ |
a06ea964 NC |
559 | ldst_pos, |
560 | ldst_regoff, | |
561 | ldst_unpriv, | |
562 | ldst_unscaled, | |
563 | ldstexcl, | |
564 | ldstnapair_offs, | |
565 | ldstpair_off, | |
566 | ldstpair_indexed, | |
567 | loadlit, | |
568 | log_imm, | |
569 | log_shift, | |
ee804238 | 570 | lse_atomic, |
a06ea964 NC |
571 | movewide, |
572 | pcreladdr, | |
573 | ic_system, | |
116b6019 RS |
574 | sve_cpy, |
575 | sve_index, | |
576 | sve_limm, | |
577 | sve_misc, | |
578 | sve_movprfx, | |
579 | sve_pred_zm, | |
580 | sve_shift_pred, | |
581 | sve_shift_unpred, | |
582 | sve_size_bhs, | |
583 | sve_size_bhsd, | |
584 | sve_size_hsd, | |
585 | sve_size_sd, | |
a06ea964 | 586 | testbranch, |
f42f1a1d TC |
587 | cryptosm3, |
588 | cryptosm4, | |
65a55fbb | 589 | dotproduct, |
a06ea964 NC |
590 | }; |
591 | ||
592 | /* Opcode enumerators. */ | |
593 | ||
594 | enum aarch64_op | |
595 | { | |
596 | OP_NIL, | |
597 | OP_STRB_POS, | |
598 | OP_LDRB_POS, | |
599 | OP_LDRSB_POS, | |
600 | OP_STRH_POS, | |
601 | OP_LDRH_POS, | |
602 | OP_LDRSH_POS, | |
603 | OP_STR_POS, | |
604 | OP_LDR_POS, | |
605 | OP_STRF_POS, | |
606 | OP_LDRF_POS, | |
607 | OP_LDRSW_POS, | |
608 | OP_PRFM_POS, | |
609 | ||
610 | OP_STURB, | |
611 | OP_LDURB, | |
612 | OP_LDURSB, | |
613 | OP_STURH, | |
614 | OP_LDURH, | |
615 | OP_LDURSH, | |
616 | OP_STUR, | |
617 | OP_LDUR, | |
618 | OP_STURV, | |
619 | OP_LDURV, | |
620 | OP_LDURSW, | |
621 | OP_PRFUM, | |
622 | ||
623 | OP_LDR_LIT, | |
624 | OP_LDRV_LIT, | |
625 | OP_LDRSW_LIT, | |
626 | OP_PRFM_LIT, | |
627 | ||
628 | OP_ADD, | |
629 | OP_B, | |
630 | OP_BL, | |
631 | ||
632 | OP_MOVN, | |
633 | OP_MOVZ, | |
634 | OP_MOVK, | |
635 | ||
636 | OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ | |
637 | OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ | |
638 | OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ | |
639 | ||
640 | OP_MOV_V, /* MOV alias for moving vector register. */ | |
641 | ||
642 | OP_ASR_IMM, | |
643 | OP_LSR_IMM, | |
644 | OP_LSL_IMM, | |
645 | ||
646 | OP_BIC, | |
647 | ||
648 | OP_UBFX, | |
649 | OP_BFXIL, | |
650 | OP_SBFX, | |
651 | OP_SBFIZ, | |
652 | OP_BFI, | |
d685192a | 653 | OP_BFC, /* ARMv8.2. */ |
a06ea964 NC |
654 | OP_UBFIZ, |
655 | OP_UXTB, | |
656 | OP_UXTH, | |
657 | OP_UXTW, | |
658 | ||
a06ea964 NC |
659 | OP_CINC, |
660 | OP_CINV, | |
661 | OP_CNEG, | |
662 | OP_CSET, | |
663 | OP_CSETM, | |
664 | ||
665 | OP_FCVT, | |
666 | OP_FCVTN, | |
667 | OP_FCVTN2, | |
668 | OP_FCVTL, | |
669 | OP_FCVTL2, | |
670 | OP_FCVTXN_S, /* Scalar version. */ | |
671 | ||
672 | OP_ROR_IMM, | |
673 | ||
e30181a5 YZ |
674 | OP_SXTL, |
675 | OP_SXTL2, | |
676 | OP_UXTL, | |
677 | OP_UXTL2, | |
678 | ||
c0890d26 RS |
679 | OP_MOV_P_P, |
680 | OP_MOV_Z_P_Z, | |
681 | OP_MOV_Z_V, | |
682 | OP_MOV_Z_Z, | |
683 | OP_MOV_Z_Zi, | |
684 | OP_MOVM_P_P_P, | |
685 | OP_MOVS_P_P, | |
686 | OP_MOVZS_P_P_P, | |
687 | OP_MOVZ_P_P_P, | |
688 | OP_NOTS_P_P_P_Z, | |
689 | OP_NOT_P_P_P_Z, | |
690 | ||
c2c4ff8d SN |
691 | OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */ |
692 | ||
a06ea964 NC |
693 | OP_TOTAL_NUM, /* Pseudo. */ |
694 | }; | |
695 | ||
1d482394 TC |
696 | /* Error types. */ |
697 | enum err_type | |
698 | { | |
699 | ERR_OK, | |
700 | ERR_UND, | |
701 | ERR_UNP, | |
702 | ERR_NYI, | |
a68f4cd2 | 703 | ERR_VFI, |
1d482394 TC |
704 | ERR_NR_ENTRIES |
705 | }; | |
706 | ||
a06ea964 NC |
707 | /* Maximum number of operands an instruction can have. */ |
708 | #define AARCH64_MAX_OPND_NUM 6 | |
709 | /* Maximum number of qualifier sequences an instruction can have. */ | |
710 | #define AARCH64_MAX_QLF_SEQ_NUM 10 | |
711 | /* Operand qualifier typedef; optimized for the size. */ | |
712 | typedef unsigned char aarch64_opnd_qualifier_t; | |
713 | /* Operand qualifier sequence typedef. */ | |
714 | typedef aarch64_opnd_qualifier_t \ | |
715 | aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; | |
716 | ||
717 | /* FIXME: improve the efficiency. */ | |
718 | static inline bfd_boolean | |
719 | empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) | |
720 | { | |
721 | int i; | |
722 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
723 | if (qualifiers[i] != AARCH64_OPND_QLF_NIL) | |
724 | return FALSE; | |
725 | return TRUE; | |
726 | } | |
727 | ||
7e84b55d TC |
728 | /* Forward declare error reporting type. */ |
729 | typedef struct aarch64_operand_error aarch64_operand_error; | |
730 | /* Forward declare instruction sequence type. */ | |
731 | typedef struct aarch64_instr_sequence aarch64_instr_sequence; | |
732 | /* Forward declare instruction definition. */ | |
733 | typedef struct aarch64_inst aarch64_inst; | |
734 | ||
a06ea964 NC |
735 | /* This structure holds information for a particular opcode. */ |
736 | ||
737 | struct aarch64_opcode | |
738 | { | |
739 | /* The name of the mnemonic. */ | |
740 | const char *name; | |
741 | ||
742 | /* The opcode itself. Those bits which will be filled in with | |
743 | operands are zeroes. */ | |
744 | aarch64_insn opcode; | |
745 | ||
746 | /* The opcode mask. This is used by the disassembler. This is a | |
747 | mask containing ones indicating those bits which must match the | |
748 | opcode field, and zeroes indicating those bits which need not | |
749 | match (and are presumably filled in by operands). */ | |
750 | aarch64_insn mask; | |
751 | ||
752 | /* Instruction class. */ | |
753 | enum aarch64_insn_class iclass; | |
754 | ||
755 | /* Enumerator identifier. */ | |
756 | enum aarch64_op op; | |
757 | ||
758 | /* Which architecture variant provides this instruction. */ | |
759 | const aarch64_feature_set *avariant; | |
760 | ||
761 | /* An array of operand codes. Each code is an index into the | |
762 | operand table. They appear in the order which the operands must | |
763 | appear in assembly code, and are terminated by a zero. */ | |
764 | enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; | |
765 | ||
766 | /* A list of operand qualifier code sequence. Each operand qualifier | |
767 | code qualifies the corresponding operand code. Each operand | |
768 | qualifier sequence specifies a valid opcode variant and related | |
769 | constraint on operands. */ | |
770 | aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; | |
771 | ||
772 | /* Flags providing information about this instruction */ | |
eae424ae TC |
773 | uint64_t flags; |
774 | ||
775 | /* Extra constraints on the instruction that the verifier checks. */ | |
776 | uint32_t constraints; | |
4bd13cde | 777 | |
0c608d6b RS |
778 | /* If nonzero, this operand and operand 0 are both registers and |
779 | are required to have the same register number. */ | |
780 | unsigned char tied_operand; | |
781 | ||
4bd13cde | 782 | /* If non-NULL, a function to verify that a given instruction is valid. */ |
755b748f TC |
783 | enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn, |
784 | bfd_vma, bfd_boolean, aarch64_operand_error *, | |
785 | struct aarch64_instr_sequence *); | |
a06ea964 NC |
786 | }; |
787 | ||
788 | typedef struct aarch64_opcode aarch64_opcode; | |
789 | ||
790 | /* Table describing all the AArch64 opcodes. */ | |
791 | extern aarch64_opcode aarch64_opcode_table[]; | |
792 | ||
793 | /* Opcode flags. */ | |
794 | #define F_ALIAS (1 << 0) | |
795 | #define F_HAS_ALIAS (1 << 1) | |
796 | /* Disassembly preference priority 1-3 (the larger the higher). If nothing | |
797 | is specified, it is the priority 0 by default, i.e. the lowest priority. */ | |
798 | #define F_P1 (1 << 2) | |
799 | #define F_P2 (2 << 2) | |
800 | #define F_P3 (3 << 2) | |
801 | /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ | |
802 | #define F_COND (1 << 4) | |
803 | /* Instruction has the field of 'sf'. */ | |
804 | #define F_SF (1 << 5) | |
805 | /* Instruction has the field of 'size:Q'. */ | |
806 | #define F_SIZEQ (1 << 6) | |
807 | /* Floating-point instruction has the field of 'type'. */ | |
808 | #define F_FPTYPE (1 << 7) | |
809 | /* AdvSIMD scalar instruction has the field of 'size'. */ | |
810 | #define F_SSIZE (1 << 8) | |
811 | /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ | |
812 | #define F_T (1 << 9) | |
813 | /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ | |
814 | #define F_GPRSIZE_IN_Q (1 << 10) | |
815 | /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ | |
816 | #define F_LDS_SIZE (1 << 11) | |
817 | /* Optional operand; assume maximum of 1 operand can be optional. */ | |
818 | #define F_OPD0_OPT (1 << 12) | |
819 | #define F_OPD1_OPT (2 << 12) | |
820 | #define F_OPD2_OPT (3 << 12) | |
821 | #define F_OPD3_OPT (4 << 12) | |
822 | #define F_OPD4_OPT (5 << 12) | |
823 | /* Default value for the optional operand when omitted from the assembly. */ | |
824 | #define F_DEFAULT(X) (((X) & 0x1f) << 15) | |
825 | /* Instruction that is an alias of another instruction needs to be | |
826 | encoded/decoded by converting it to/from the real form, followed by | |
827 | the encoding/decoding according to the rules of the real opcode. | |
828 | This compares to the direct coding using the alias's information. | |
829 | N.B. this flag requires F_ALIAS to be used together. */ | |
830 | #define F_CONV (1 << 20) | |
831 | /* Use together with F_ALIAS to indicate an alias opcode is a programmer | |
832 | friendly pseudo instruction available only in the assembly code (thus will | |
833 | not show up in the disassembly). */ | |
834 | #define F_PSEUDO (1 << 21) | |
835 | /* Instruction has miscellaneous encoding/decoding rules. */ | |
836 | #define F_MISC (1 << 22) | |
837 | /* Instruction has the field of 'N'; used in conjunction with F_SF. */ | |
838 | #define F_N (1 << 23) | |
839 | /* Opcode dependent field. */ | |
840 | #define F_OD(X) (((X) & 0x7) << 24) | |
ee804238 JW |
841 | /* Instruction has the field of 'sz'. */ |
842 | #define F_LSE_SZ (1 << 27) | |
4989adac RS |
843 | /* Require an exact qualifier match, even for NIL qualifiers. */ |
844 | #define F_STRICT (1ULL << 28) | |
f9830ec1 TC |
845 | /* This system instruction is used to read system registers. */ |
846 | #define F_SYS_READ (1ULL << 29) | |
847 | /* This system instruction is used to write system registers. */ | |
848 | #define F_SYS_WRITE (1ULL << 30) | |
eae424ae TC |
849 | /* This instruction has an extra constraint on it that imposes a requirement on |
850 | subsequent instructions. */ | |
851 | #define F_SCAN (1ULL << 31) | |
852 | /* Next bit is 32. */ | |
853 | ||
854 | /* Instruction constraints. */ | |
855 | /* This instruction has a predication constraint on the instruction at PC+4. */ | |
856 | #define C_SCAN_MOVPRFX (1U << 0) | |
857 | /* This instruction's operation width is determined by the operand with the | |
858 | largest element size. */ | |
859 | #define C_MAX_ELEM (1U << 1) | |
860 | /* Next bit is 2. */ | |
a06ea964 NC |
861 | |
862 | static inline bfd_boolean | |
863 | alias_opcode_p (const aarch64_opcode *opcode) | |
864 | { | |
865 | return (opcode->flags & F_ALIAS) ? TRUE : FALSE; | |
866 | } | |
867 | ||
868 | static inline bfd_boolean | |
869 | opcode_has_alias (const aarch64_opcode *opcode) | |
870 | { | |
871 | return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; | |
872 | } | |
873 | ||
874 | /* Priority for disassembling preference. */ | |
875 | static inline int | |
876 | opcode_priority (const aarch64_opcode *opcode) | |
877 | { | |
878 | return (opcode->flags >> 2) & 0x3; | |
879 | } | |
880 | ||
881 | static inline bfd_boolean | |
882 | pseudo_opcode_p (const aarch64_opcode *opcode) | |
883 | { | |
884 | return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; | |
885 | } | |
886 | ||
887 | static inline bfd_boolean | |
888 | optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) | |
889 | { | |
890 | return (((opcode->flags >> 12) & 0x7) == idx + 1) | |
891 | ? TRUE : FALSE; | |
892 | } | |
893 | ||
894 | static inline aarch64_insn | |
895 | get_optional_operand_default_value (const aarch64_opcode *opcode) | |
896 | { | |
897 | return (opcode->flags >> 15) & 0x1f; | |
898 | } | |
899 | ||
900 | static inline unsigned int | |
901 | get_opcode_dependent_value (const aarch64_opcode *opcode) | |
902 | { | |
903 | return (opcode->flags >> 24) & 0x7; | |
904 | } | |
905 | ||
906 | static inline bfd_boolean | |
907 | opcode_has_special_coder (const aarch64_opcode *opcode) | |
908 | { | |
ee804238 | 909 | return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T |
a06ea964 NC |
910 | | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE |
911 | : FALSE; | |
912 | } | |
913 | \f | |
914 | struct aarch64_name_value_pair | |
915 | { | |
916 | const char * name; | |
917 | aarch64_insn value; | |
918 | }; | |
919 | ||
920 | extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; | |
a06ea964 NC |
921 | extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; |
922 | extern const struct aarch64_name_value_pair aarch64_prfops [32]; | |
9ed608f9 | 923 | extern const struct aarch64_name_value_pair aarch64_hint_options []; |
a06ea964 | 924 | |
49eec193 YZ |
925 | typedef struct |
926 | { | |
927 | const char * name; | |
928 | aarch64_insn value; | |
929 | uint32_t flags; | |
930 | } aarch64_sys_reg; | |
931 | ||
932 | extern const aarch64_sys_reg aarch64_sys_regs []; | |
87b8eed7 | 933 | extern const aarch64_sys_reg aarch64_pstatefields []; |
49eec193 | 934 | extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); |
f21cce2c MW |
935 | extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, |
936 | const aarch64_sys_reg *); | |
937 | extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, | |
938 | const aarch64_sys_reg *); | |
49eec193 | 939 | |
a06ea964 NC |
940 | typedef struct |
941 | { | |
875880c6 | 942 | const char *name; |
a06ea964 | 943 | uint32_t value; |
ea2deeec | 944 | uint32_t flags ; |
a06ea964 NC |
945 | } aarch64_sys_ins_reg; |
946 | ||
ea2deeec | 947 | extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); |
d6bf7ce6 MW |
948 | extern bfd_boolean |
949 | aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, | |
950 | const aarch64_sys_ins_reg *); | |
ea2deeec | 951 | |
a06ea964 NC |
952 | extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; |
953 | extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; | |
954 | extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; | |
955 | extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; | |
2ac435d4 | 956 | extern const aarch64_sys_ins_reg aarch64_sys_regs_sr []; |
a06ea964 NC |
957 | |
958 | /* Shift/extending operator kinds. | |
959 | N.B. order is important; keep aarch64_operand_modifiers synced. */ | |
960 | enum aarch64_modifier_kind | |
961 | { | |
962 | AARCH64_MOD_NONE, | |
963 | AARCH64_MOD_MSL, | |
964 | AARCH64_MOD_ROR, | |
965 | AARCH64_MOD_ASR, | |
966 | AARCH64_MOD_LSR, | |
967 | AARCH64_MOD_LSL, | |
968 | AARCH64_MOD_UXTB, | |
969 | AARCH64_MOD_UXTH, | |
970 | AARCH64_MOD_UXTW, | |
971 | AARCH64_MOD_UXTX, | |
972 | AARCH64_MOD_SXTB, | |
973 | AARCH64_MOD_SXTH, | |
974 | AARCH64_MOD_SXTW, | |
975 | AARCH64_MOD_SXTX, | |
2442d846 | 976 | AARCH64_MOD_MUL, |
98907a70 | 977 | AARCH64_MOD_MUL_VL, |
a06ea964 NC |
978 | }; |
979 | ||
980 | bfd_boolean | |
981 | aarch64_extend_operator_p (enum aarch64_modifier_kind); | |
982 | ||
983 | enum aarch64_modifier_kind | |
984 | aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); | |
985 | /* Condition. */ | |
986 | ||
987 | typedef struct | |
988 | { | |
989 | /* A list of names with the first one as the disassembly preference; | |
990 | terminated by NULL if fewer than 3. */ | |
bb7eff52 | 991 | const char *names[4]; |
a06ea964 NC |
992 | aarch64_insn value; |
993 | } aarch64_cond; | |
994 | ||
995 | extern const aarch64_cond aarch64_conds[16]; | |
996 | ||
997 | const aarch64_cond* get_cond_from_value (aarch64_insn value); | |
998 | const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); | |
999 | \f | |
1000 | /* Structure representing an operand. */ | |
1001 | ||
1002 | struct aarch64_opnd_info | |
1003 | { | |
1004 | enum aarch64_opnd type; | |
1005 | aarch64_opnd_qualifier_t qualifier; | |
1006 | int idx; | |
1007 | ||
1008 | union | |
1009 | { | |
1010 | struct | |
1011 | { | |
1012 | unsigned regno; | |
1013 | } reg; | |
1014 | struct | |
1015 | { | |
dab26bf4 RS |
1016 | unsigned int regno; |
1017 | int64_t index; | |
a06ea964 NC |
1018 | } reglane; |
1019 | /* e.g. LVn. */ | |
1020 | struct | |
1021 | { | |
1022 | unsigned first_regno : 5; | |
1023 | unsigned num_regs : 3; | |
1024 | /* 1 if it is a list of reg element. */ | |
1025 | unsigned has_index : 1; | |
1026 | /* Lane index; valid only when has_index is 1. */ | |
dab26bf4 | 1027 | int64_t index; |
a06ea964 NC |
1028 | } reglist; |
1029 | /* e.g. immediate or pc relative address offset. */ | |
1030 | struct | |
1031 | { | |
1032 | int64_t value; | |
1033 | unsigned is_fp : 1; | |
1034 | } imm; | |
1035 | /* e.g. address in STR (register offset). */ | |
1036 | struct | |
1037 | { | |
1038 | unsigned base_regno; | |
1039 | struct | |
1040 | { | |
1041 | union | |
1042 | { | |
1043 | int imm; | |
1044 | unsigned regno; | |
1045 | }; | |
1046 | unsigned is_reg; | |
1047 | } offset; | |
1048 | unsigned pcrel : 1; /* PC-relative. */ | |
1049 | unsigned writeback : 1; | |
1050 | unsigned preind : 1; /* Pre-indexed. */ | |
1051 | unsigned postind : 1; /* Post-indexed. */ | |
1052 | } addr; | |
561a72d4 TC |
1053 | |
1054 | struct | |
1055 | { | |
1056 | /* The encoding of the system register. */ | |
1057 | aarch64_insn value; | |
1058 | ||
1059 | /* The system register flags. */ | |
1060 | uint32_t flags; | |
1061 | } sysreg; | |
1062 | ||
a06ea964 | 1063 | const aarch64_cond *cond; |
a06ea964 NC |
1064 | /* The encoding of the PSTATE field. */ |
1065 | aarch64_insn pstatefield; | |
1066 | const aarch64_sys_ins_reg *sysins_op; | |
1067 | const struct aarch64_name_value_pair *barrier; | |
9ed608f9 | 1068 | const struct aarch64_name_value_pair *hint_option; |
a06ea964 NC |
1069 | const struct aarch64_name_value_pair *prfop; |
1070 | }; | |
1071 | ||
1072 | /* Operand shifter; in use when the operand is a register offset address, | |
1073 | add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ | |
1074 | struct | |
1075 | { | |
1076 | enum aarch64_modifier_kind kind; | |
a06ea964 NC |
1077 | unsigned operator_present: 1; /* Only valid during encoding. */ |
1078 | /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ | |
1079 | unsigned amount_present: 1; | |
2442d846 | 1080 | int64_t amount; |
a06ea964 NC |
1081 | } shifter; |
1082 | ||
1083 | unsigned skip:1; /* Operand is not completed if there is a fixup needed | |
1084 | to be done on it. In some (but not all) of these | |
1085 | cases, we need to tell libopcodes to skip the | |
1086 | constraint checking and the encoding for this | |
1087 | operand, so that the libopcodes can pick up the | |
1088 | right opcode before the operand is fixed-up. This | |
1089 | flag should only be used during the | |
1090 | assembling/encoding. */ | |
1091 | unsigned present:1; /* Whether this operand is present in the assembly | |
1092 | line; not used during the disassembly. */ | |
1093 | }; | |
1094 | ||
1095 | typedef struct aarch64_opnd_info aarch64_opnd_info; | |
1096 | ||
1097 | /* Structure representing an instruction. | |
1098 | ||
1099 | It is used during both the assembling and disassembling. The assembler | |
1100 | fills an aarch64_inst after a successful parsing and then passes it to the | |
1101 | encoding routine to do the encoding. During the disassembling, the | |
1102 | disassembler calls the decoding routine to decode a binary instruction; on a | |
1103 | successful return, such a structure will be filled with information of the | |
1104 | instruction; then the disassembler uses the information to print out the | |
1105 | instruction. */ | |
1106 | ||
1107 | struct aarch64_inst | |
1108 | { | |
1109 | /* The value of the binary instruction. */ | |
1110 | aarch64_insn value; | |
1111 | ||
1112 | /* Corresponding opcode entry. */ | |
1113 | const aarch64_opcode *opcode; | |
1114 | ||
1115 | /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ | |
1116 | const aarch64_cond *cond; | |
1117 | ||
1118 | /* Operands information. */ | |
1119 | aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; | |
1120 | }; | |
1121 | ||
ff605452 SD |
1122 | /* Defining the HINT #imm values for the aarch64_hint_options. */ |
1123 | #define HINT_OPD_CSYNC 0x11 | |
1124 | #define HINT_OPD_C 0x22 | |
1125 | #define HINT_OPD_J 0x24 | |
1126 | #define HINT_OPD_JC 0x26 | |
1127 | #define HINT_OPD_NULL 0x00 | |
1128 | ||
a06ea964 NC |
1129 | \f |
1130 | /* Diagnosis related declaration and interface. */ | |
1131 | ||
1132 | /* Operand error kind enumerators. | |
1133 | ||
1134 | AARCH64_OPDE_RECOVERABLE | |
1135 | Less severe error found during the parsing, very possibly because that | |
1136 | GAS has picked up a wrong instruction template for the parsing. | |
1137 | ||
1138 | AARCH64_OPDE_SYNTAX_ERROR | |
1139 | General syntax error; it can be either a user error, or simply because | |
1140 | that GAS is trying a wrong instruction template. | |
1141 | ||
1142 | AARCH64_OPDE_FATAL_SYNTAX_ERROR | |
1143 | Definitely a user syntax error. | |
1144 | ||
1145 | AARCH64_OPDE_INVALID_VARIANT | |
1146 | No syntax error, but the operands are not a valid combination, e.g. | |
1147 | FMOV D0,S0 | |
1148 | ||
0c608d6b RS |
1149 | AARCH64_OPDE_UNTIED_OPERAND |
1150 | The asm failed to use the same register for a destination operand | |
1151 | and a tied source operand. | |
1152 | ||
a06ea964 NC |
1153 | AARCH64_OPDE_OUT_OF_RANGE |
1154 | Error about some immediate value out of a valid range. | |
1155 | ||
1156 | AARCH64_OPDE_UNALIGNED | |
1157 | Error about some immediate value not properly aligned (i.e. not being a | |
1158 | multiple times of a certain value). | |
1159 | ||
1160 | AARCH64_OPDE_REG_LIST | |
1161 | Error about the register list operand having unexpected number of | |
1162 | registers. | |
1163 | ||
1164 | AARCH64_OPDE_OTHER_ERROR | |
1165 | Error of the highest severity and used for any severe issue that does not | |
1166 | fall into any of the above categories. | |
1167 | ||
1168 | The enumerators are only interesting to GAS. They are declared here (in | |
1169 | libopcodes) because that some errors are detected (and then notified to GAS) | |
1170 | by libopcodes (rather than by GAS solely). | |
1171 | ||
1172 | The first three errors are only deteced by GAS while the | |
1173 | AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as | |
1174 | only libopcodes has the information about the valid variants of each | |
1175 | instruction. | |
1176 | ||
1177 | The enumerators have an increasing severity. This is helpful when there are | |
1178 | multiple instruction templates available for a given mnemonic name (e.g. | |
1179 | FMOV); this mechanism will help choose the most suitable template from which | |
1180 | the generated diagnostics can most closely describe the issues, if any. */ | |
1181 | ||
1182 | enum aarch64_operand_error_kind | |
1183 | { | |
1184 | AARCH64_OPDE_NIL, | |
1185 | AARCH64_OPDE_RECOVERABLE, | |
1186 | AARCH64_OPDE_SYNTAX_ERROR, | |
1187 | AARCH64_OPDE_FATAL_SYNTAX_ERROR, | |
1188 | AARCH64_OPDE_INVALID_VARIANT, | |
0c608d6b | 1189 | AARCH64_OPDE_UNTIED_OPERAND, |
a06ea964 NC |
1190 | AARCH64_OPDE_OUT_OF_RANGE, |
1191 | AARCH64_OPDE_UNALIGNED, | |
1192 | AARCH64_OPDE_REG_LIST, | |
1193 | AARCH64_OPDE_OTHER_ERROR | |
1194 | }; | |
1195 | ||
1196 | /* N.B. GAS assumes that this structure work well with shallow copy. */ | |
1197 | struct aarch64_operand_error | |
1198 | { | |
1199 | enum aarch64_operand_error_kind kind; | |
1200 | int index; | |
1201 | const char *error; | |
1202 | int data[3]; /* Some data for extra information. */ | |
7d02540a | 1203 | bfd_boolean non_fatal; |
a06ea964 NC |
1204 | }; |
1205 | ||
7e84b55d TC |
1206 | /* AArch64 sequence structure used to track instructions with F_SCAN |
1207 | dependencies for both assembler and disassembler. */ | |
1208 | struct aarch64_instr_sequence | |
1209 | { | |
1210 | /* The instruction that caused this sequence to be opened. */ | |
1211 | aarch64_inst *instr; | |
1212 | /* The number of instructions the above instruction allows to be kept in the | |
1213 | sequence before an automatic close is done. */ | |
1214 | int num_insns; | |
1215 | /* The instructions currently added to the sequence. */ | |
1216 | aarch64_inst **current_insns; | |
1217 | /* The number of instructions already in the sequence. */ | |
1218 | int next_insn; | |
1219 | }; | |
a06ea964 NC |
1220 | |
1221 | /* Encoding entrypoint. */ | |
1222 | ||
1223 | extern int | |
1224 | aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, | |
1225 | aarch64_insn *, aarch64_opnd_qualifier_t *, | |
7e84b55d | 1226 | aarch64_operand_error *, aarch64_instr_sequence *); |
a06ea964 NC |
1227 | |
1228 | extern const aarch64_opcode * | |
1229 | aarch64_replace_opcode (struct aarch64_inst *, | |
1230 | const aarch64_opcode *); | |
1231 | ||
1232 | /* Given the opcode enumerator OP, return the pointer to the corresponding | |
1233 | opcode entry. */ | |
1234 | ||
1235 | extern const aarch64_opcode * | |
1236 | aarch64_get_opcode (enum aarch64_op); | |
1237 | ||
1238 | /* Generate the string representation of an operand. */ | |
1239 | extern void | |
1240 | aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, | |
7d02540a TC |
1241 | const aarch64_opnd_info *, int, int *, bfd_vma *, |
1242 | char **); | |
a06ea964 NC |
1243 | |
1244 | /* Miscellaneous interface. */ | |
1245 | ||
1246 | extern int | |
1247 | aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); | |
1248 | ||
1249 | extern aarch64_opnd_qualifier_t | |
1250 | aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, | |
1251 | const aarch64_opnd_qualifier_t, int); | |
1252 | ||
a68f4cd2 TC |
1253 | extern bfd_boolean |
1254 | aarch64_is_destructive_by_operands (const aarch64_opcode *); | |
1255 | ||
a06ea964 NC |
1256 | extern int |
1257 | aarch64_num_of_operands (const aarch64_opcode *); | |
1258 | ||
1259 | extern int | |
1260 | aarch64_stack_pointer_p (const aarch64_opnd_info *); | |
1261 | ||
e141d84e YQ |
1262 | extern int |
1263 | aarch64_zero_register_p (const aarch64_opnd_info *); | |
a06ea964 | 1264 | |
1d482394 | 1265 | extern enum err_type |
561a72d4 | 1266 | aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean, |
a68f4cd2 TC |
1267 | aarch64_operand_error *); |
1268 | ||
1269 | extern void | |
1270 | init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *); | |
36f4aab1 | 1271 | |
a06ea964 NC |
1272 | /* Given an operand qualifier, return the expected data element size |
1273 | of a qualified operand. */ | |
1274 | extern unsigned char | |
1275 | aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); | |
1276 | ||
1277 | extern enum aarch64_operand_class | |
1278 | aarch64_get_operand_class (enum aarch64_opnd); | |
1279 | ||
1280 | extern const char * | |
1281 | aarch64_get_operand_name (enum aarch64_opnd); | |
1282 | ||
1283 | extern const char * | |
1284 | aarch64_get_operand_desc (enum aarch64_opnd); | |
1285 | ||
e950b345 RS |
1286 | extern bfd_boolean |
1287 | aarch64_sve_dupm_mov_immediate_p (uint64_t, int); | |
1288 | ||
a06ea964 NC |
1289 | #ifdef DEBUG_AARCH64 |
1290 | extern int debug_dump; | |
1291 | ||
1292 | extern void | |
1293 | aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); | |
1294 | ||
1295 | #define DEBUG_TRACE(M, ...) \ | |
1296 | { \ | |
1297 | if (debug_dump) \ | |
1298 | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ | |
1299 | } | |
1300 | ||
1301 | #define DEBUG_TRACE_IF(C, M, ...) \ | |
1302 | { \ | |
1303 | if (debug_dump && (C)) \ | |
1304 | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ | |
1305 | } | |
1306 | #else /* !DEBUG_AARCH64 */ | |
1307 | #define DEBUG_TRACE(M, ...) ; | |
1308 | #define DEBUG_TRACE_IF(C, M, ...) ; | |
1309 | #endif /* DEBUG_AARCH64 */ | |
1310 | ||
245d2e3f RS |
1311 | extern const char *const aarch64_sve_pattern_array[32]; |
1312 | extern const char *const aarch64_sve_prfop_array[16]; | |
1313 | ||
d3e12b29 YQ |
1314 | #ifdef __cplusplus |
1315 | } | |
1316 | #endif | |
1317 | ||
a06ea964 | 1318 | #endif /* OPCODE_AARCH64_H */ |