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5f184715 AF |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Andy Fleming <afleming@freescale.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5f184715 AF |
6 | * |
7 | * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h | |
8 | */ | |
9 | ||
10 | #ifndef _PHY_H | |
11 | #define _PHY_H | |
12 | ||
13 | #include <linux/list.h> | |
14 | #include <linux/mii.h> | |
15 | #include <linux/ethtool.h> | |
16 | #include <linux/mdio.h> | |
17 | ||
18 | #define PHY_MAX_ADDR 32 | |
19 | ||
20 | #define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ | |
21 | SUPPORTED_10baseT_Full | \ | |
22 | SUPPORTED_100baseT_Half | \ | |
23 | SUPPORTED_100baseT_Full | \ | |
24 | SUPPORTED_Autoneg | \ | |
25 | SUPPORTED_TP | \ | |
26 | SUPPORTED_MII) | |
27 | ||
28 | #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ | |
29 | SUPPORTED_1000baseT_Half | \ | |
30 | SUPPORTED_1000baseT_Full) | |
31 | ||
32 | #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ | |
33 | SUPPORTED_10000baseT_Full) | |
34 | ||
35 | #define PHY_ANEG_TIMEOUT 4000 | |
36 | ||
37 | ||
38 | typedef enum { | |
39 | PHY_INTERFACE_MODE_MII, | |
40 | PHY_INTERFACE_MODE_GMII, | |
41 | PHY_INTERFACE_MODE_SGMII, | |
7794b1a7 | 42 | PHY_INTERFACE_MODE_QSGMII, |
5f184715 AF |
43 | PHY_INTERFACE_MODE_TBI, |
44 | PHY_INTERFACE_MODE_RMII, | |
45 | PHY_INTERFACE_MODE_RGMII, | |
46 | PHY_INTERFACE_MODE_RGMII_ID, | |
47 | PHY_INTERFACE_MODE_RGMII_RXID, | |
48 | PHY_INTERFACE_MODE_RGMII_TXID, | |
49 | PHY_INTERFACE_MODE_RTBI, | |
50 | PHY_INTERFACE_MODE_XGMII, | |
51 | PHY_INTERFACE_MODE_NONE /* Must be last */ | |
52 | } phy_interface_t; | |
53 | ||
54 | static const char *phy_interface_strings[] = { | |
55 | [PHY_INTERFACE_MODE_MII] = "mii", | |
56 | [PHY_INTERFACE_MODE_GMII] = "gmii", | |
57 | [PHY_INTERFACE_MODE_SGMII] = "sgmii", | |
7794b1a7 | 58 | [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", |
5f184715 AF |
59 | [PHY_INTERFACE_MODE_TBI] = "tbi", |
60 | [PHY_INTERFACE_MODE_RMII] = "rmii", | |
61 | [PHY_INTERFACE_MODE_RGMII] = "rgmii", | |
62 | [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", | |
63 | [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", | |
64 | [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", | |
65 | [PHY_INTERFACE_MODE_RTBI] = "rtbi", | |
66 | [PHY_INTERFACE_MODE_XGMII] = "xgmii", | |
67 | [PHY_INTERFACE_MODE_NONE] = "", | |
68 | }; | |
69 | ||
70 | static inline const char *phy_string_for_interface(phy_interface_t i) | |
71 | { | |
72 | /* Default to unknown */ | |
73 | if (i > PHY_INTERFACE_MODE_NONE) | |
74 | i = PHY_INTERFACE_MODE_NONE; | |
75 | ||
76 | return phy_interface_strings[i]; | |
77 | } | |
78 | ||
79 | ||
80 | struct phy_device; | |
81 | ||
82 | #define MDIO_NAME_LEN 32 | |
83 | ||
84 | struct mii_dev { | |
85 | struct list_head link; | |
86 | char name[MDIO_NAME_LEN]; | |
87 | void *priv; | |
88 | int (*read)(struct mii_dev *bus, int addr, int devad, int reg); | |
89 | int (*write)(struct mii_dev *bus, int addr, int devad, int reg, | |
90 | u16 val); | |
91 | int (*reset)(struct mii_dev *bus); | |
92 | struct phy_device *phymap[PHY_MAX_ADDR]; | |
93 | u32 phy_mask; | |
94 | }; | |
95 | ||
96 | /* struct phy_driver: a structure which defines PHY behavior | |
97 | * | |
98 | * uid will contain a number which represents the PHY. During | |
99 | * startup, the driver will poll the PHY to find out what its | |
100 | * UID--as defined by registers 2 and 3--is. The 32-bit result | |
101 | * gotten from the PHY will be masked to | |
102 | * discard any bits which may change based on revision numbers | |
103 | * unimportant to functionality | |
104 | * | |
105 | */ | |
106 | struct phy_driver { | |
107 | char *name; | |
108 | unsigned int uid; | |
109 | unsigned int mask; | |
110 | unsigned int mmds; | |
111 | ||
112 | u32 features; | |
113 | ||
114 | /* Called to do any driver startup necessities */ | |
115 | /* Will be called during phy_connect */ | |
116 | int (*probe)(struct phy_device *phydev); | |
117 | ||
118 | /* Called to configure the PHY, and modify the controller | |
119 | * based on the results. Should be called after phy_connect */ | |
120 | int (*config)(struct phy_device *phydev); | |
121 | ||
122 | /* Called when starting up the controller */ | |
123 | int (*startup)(struct phy_device *phydev); | |
124 | ||
125 | /* Called when bringing down the controller */ | |
126 | int (*shutdown)(struct phy_device *phydev); | |
127 | ||
128 | struct list_head list; | |
129 | }; | |
130 | ||
131 | struct phy_device { | |
132 | /* Information about the PHY type */ | |
133 | /* And management functions */ | |
134 | struct mii_dev *bus; | |
135 | struct phy_driver *drv; | |
136 | void *priv; | |
137 | ||
138 | struct eth_device *dev; | |
139 | ||
140 | /* forced speed & duplex (no autoneg) | |
141 | * partner speed & duplex & pause (autoneg) | |
142 | */ | |
143 | int speed; | |
144 | int duplex; | |
145 | ||
146 | /* The most recently read link state */ | |
147 | int link; | |
148 | int port; | |
149 | phy_interface_t interface; | |
150 | ||
151 | u32 advertising; | |
152 | u32 supported; | |
153 | u32 mmds; | |
154 | ||
155 | int autoneg; | |
156 | int addr; | |
157 | int pause; | |
158 | int asym_pause; | |
159 | u32 phy_id; | |
160 | u32 flags; | |
161 | }; | |
162 | ||
163 | static inline int phy_read(struct phy_device *phydev, int devad, int regnum) | |
164 | { | |
165 | struct mii_dev *bus = phydev->bus; | |
166 | ||
167 | return bus->read(bus, phydev->addr, devad, regnum); | |
168 | } | |
169 | ||
170 | static inline int phy_write(struct phy_device *phydev, int devad, int regnum, | |
171 | u16 val) | |
172 | { | |
173 | struct mii_dev *bus = phydev->bus; | |
174 | ||
175 | return bus->write(bus, phydev->addr, devad, regnum, val); | |
176 | } | |
177 | ||
178 | #ifdef CONFIG_PHYLIB_10G | |
179 | extern struct phy_driver gen10g_driver; | |
180 | ||
181 | /* For now, XGMII is the only 10G interface */ | |
182 | static inline int is_10g_interface(phy_interface_t interface) | |
183 | { | |
184 | return interface == PHY_INTERFACE_MODE_XGMII; | |
185 | } | |
186 | ||
187 | #endif | |
188 | ||
189 | int phy_init(void); | |
190 | int phy_reset(struct phy_device *phydev); | |
1adb406b TK |
191 | struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, |
192 | phy_interface_t interface); | |
193 | void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); | |
5f184715 AF |
194 | struct phy_device *phy_connect(struct mii_dev *bus, int addr, |
195 | struct eth_device *dev, | |
196 | phy_interface_t interface); | |
197 | int phy_startup(struct phy_device *phydev); | |
198 | int phy_config(struct phy_device *phydev); | |
199 | int phy_shutdown(struct phy_device *phydev); | |
200 | int phy_register(struct phy_driver *drv); | |
201 | int genphy_config_aneg(struct phy_device *phydev); | |
8682aba7 | 202 | int genphy_restart_aneg(struct phy_device *phydev); |
5f184715 | 203 | int genphy_update_link(struct phy_device *phydev); |
e2043f5c | 204 | int genphy_parse_link(struct phy_device *phydev); |
5f184715 AF |
205 | int genphy_config(struct phy_device *phydev); |
206 | int genphy_startup(struct phy_device *phydev); | |
207 | int genphy_shutdown(struct phy_device *phydev); | |
208 | int gen10g_config(struct phy_device *phydev); | |
209 | int gen10g_startup(struct phy_device *phydev); | |
210 | int gen10g_shutdown(struct phy_device *phydev); | |
211 | int gen10g_discover_mmds(struct phy_device *phydev); | |
212 | ||
9082eeac AF |
213 | int phy_atheros_init(void); |
214 | int phy_broadcom_init(void); | |
215 | int phy_davicom_init(void); | |
f485c8a3 | 216 | int phy_et1011c_init(void); |
9082eeac AF |
217 | int phy_lxt_init(void); |
218 | int phy_marvell_init(void); | |
219 | int phy_micrel_init(void); | |
220 | int phy_natsemi_init(void); | |
221 | int phy_realtek_init(void); | |
b6abf555 | 222 | int phy_smsc_init(void); |
9082eeac AF |
223 | int phy_teranetics_init(void); |
224 | int phy_vitesse_init(void); | |
a836626c TT |
225 | |
226 | /* PHY UIDs for various PHYs that are referenced in external code */ | |
227 | #define PHY_UID_TN2020 0x00a19410 | |
228 | ||
5f184715 | 229 | #endif |