[thirdparty/u-boot.git] / include / phy_interface.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2020 NXP
 *	Andy Fleming <afleming@gmail.com>
 *
 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
 */

#ifndef _PHY_INTERFACE_H
#define _PHY_INTERFACE_H

#include <string.h>

typedef enum {
	PHY_INTERFACE_MODE_NA, /* don't touch */
	PHY_INTERFACE_MODE_INTERNAL,
	PHY_INTERFACE_MODE_MII,
	PHY_INTERFACE_MODE_GMII,
	PHY_INTERFACE_MODE_SGMII,
	PHY_INTERFACE_MODE_TBI,
	PHY_INTERFACE_MODE_REVMII,
	PHY_INTERFACE_MODE_RMII,
	PHY_INTERFACE_MODE_REVRMII,
	PHY_INTERFACE_MODE_RGMII,
	PHY_INTERFACE_MODE_RGMII_ID,
	PHY_INTERFACE_MODE_RGMII_RXID,
	PHY_INTERFACE_MODE_RGMII_TXID,
	PHY_INTERFACE_MODE_RTBI,
	PHY_INTERFACE_MODE_SMII,
	PHY_INTERFACE_MODE_XGMII,
	PHY_INTERFACE_MODE_XLGMII,
	PHY_INTERFACE_MODE_MOCA,
	PHY_INTERFACE_MODE_QSGMII,
	PHY_INTERFACE_MODE_TRGMII,
	PHY_INTERFACE_MODE_100BASEX,
	PHY_INTERFACE_MODE_1000BASEX,
	PHY_INTERFACE_MODE_2500BASEX,
	PHY_INTERFACE_MODE_5GBASER,
	PHY_INTERFACE_MODE_RXAUI,
	PHY_INTERFACE_MODE_XAUI,
	/* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
	PHY_INTERFACE_MODE_10GBASER,
	PHY_INTERFACE_MODE_25GBASER,
	PHY_INTERFACE_MODE_USXGMII,
	/* 10GBASE-KR - with Clause 73 AN */
	PHY_INTERFACE_MODE_10GKR,
	PHY_INTERFACE_MODE_QUSGMII,
	PHY_INTERFACE_MODE_1000BASEKX,
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
	/* LX2160A SERDES modes */
	PHY_INTERFACE_MODE_25G_AUI,
	PHY_INTERFACE_MODE_XLAUI,
	PHY_INTERFACE_MODE_CAUI2,
	PHY_INTERFACE_MODE_CAUI4,
#endif
#if defined(CONFIG_PHY_NCSI)
	PHY_INTERFACE_MODE_NCSI,
#endif
	PHY_INTERFACE_MODE_MAX,
} phy_interface_t;

static const char * const phy_interface_strings[] = {
	[PHY_INTERFACE_MODE_NA]			= "",
	[PHY_INTERFACE_MODE_INTERNAL]		= "internal",
	[PHY_INTERFACE_MODE_MII]		= "mii",
	[PHY_INTERFACE_MODE_GMII]		= "gmii",
	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
	[PHY_INTERFACE_MODE_TBI]		= "tbi",
	[PHY_INTERFACE_MODE_REVMII]		= "rev-mii",
	[PHY_INTERFACE_MODE_RMII]		= "rmii",
	[PHY_INTERFACE_MODE_REVRMII]		= "rev-rmii",
	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
	[PHY_INTERFACE_MODE_RGMII_ID]		= "rgmii-id",
	[PHY_INTERFACE_MODE_RGMII_RXID]		= "rgmii-rxid",
	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
	[PHY_INTERFACE_MODE_SMII]		= "smii",
	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
	[PHY_INTERFACE_MODE_XLGMII]		= "xlgmii",
	[PHY_INTERFACE_MODE_MOCA]		= "moca",
	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
	[PHY_INTERFACE_MODE_TRGMII]		= "trgmii",
	[PHY_INTERFACE_MODE_1000BASEX]		= "1000base-x",
	[PHY_INTERFACE_MODE_1000BASEKX]		= "1000base-kx",
	[PHY_INTERFACE_MODE_2500BASEX]		= "2500base-x",
	[PHY_INTERFACE_MODE_5GBASER]		= "5gbase-r",
	[PHY_INTERFACE_MODE_RXAUI]		= "rxaui",
	[PHY_INTERFACE_MODE_XAUI]		= "xaui",
	[PHY_INTERFACE_MODE_10GBASER]		= "10gbase-r",
	[PHY_INTERFACE_MODE_25GBASER]		= "25gbase-r",
	[PHY_INTERFACE_MODE_USXGMII]		= "usxgmii",
	[PHY_INTERFACE_MODE_10GKR]		= "10gbase-kr",
	[PHY_INTERFACE_MODE_100BASEX]		= "100base-x",
	[PHY_INTERFACE_MODE_QUSGMII]		= "qusgmii",
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
	/* LX2160A SERDES modes */
	[PHY_INTERFACE_MODE_25G_AUI]		= "25g-aui",
	[PHY_INTERFACE_MODE_XLAUI]		= "xlaui4",
	[PHY_INTERFACE_MODE_CAUI2]		= "caui2",
	[PHY_INTERFACE_MODE_CAUI4]		= "caui4",
#endif
#if defined(CONFIG_PHY_NCSI)
	[PHY_INTERFACE_MODE_NCSI]		= "NC-SI",
#endif
};

/* Backplane modes:
 * are considered a sub-type of phy_interface_t: XGMII
 * and are specified in "phy-connection-type" with one of the following strings
 */
static const char * const backplane_mode_strings[] = {
	"10gbase-kr",
	"40gbase-kr4",
};

static inline const char *phy_string_for_interface(phy_interface_t i)
{
	/* Default to unknown */
	if (i >= PHY_INTERFACE_MODE_MAX)
		i = PHY_INTERFACE_MODE_NA;

	return phy_interface_strings[i];
}

static inline bool is_backplane_mode(const char *phyconn)
{
	int i;

	if (!phyconn)
		return false;
	for (i = 0; i < ARRAY_SIZE(backplane_mode_strings); i++) {
		if (!strcmp(phyconn, backplane_mode_strings[i]))
			return true;
	}
	return false;
}

#endif /* _PHY_INTERFACE_H */
Commit	Line	Data
f070b1a2 JH	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright 2011 Freescale Semiconductor, Inc.
5d3bcdb1	4	* Copyright 2020 NXP
f070b1a2 JH	5	* Andy Fleming <afleming@gmail.com>
	6	*
	7	* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
	8	*/
	9
	10	#ifndef _PHY_INTERFACE_H
	11	#define _PHY_INTERFACE_H
	12
2a64ada7 SG	13	#include <string.h>
2a64ada7 SG	14
f070b1a2	15	typedef enum {
c677fb1e	16	PHY_INTERFACE_MODE_NA, /* don't touch */
75d28899	17	PHY_INTERFACE_MODE_INTERNAL,
f070b1a2 JH	18	PHY_INTERFACE_MODE_MII,
	19	PHY_INTERFACE_MODE_GMII,
	20	PHY_INTERFACE_MODE_SGMII,
f070b1a2	21	PHY_INTERFACE_MODE_TBI,
75d28899	22	PHY_INTERFACE_MODE_REVMII,
f070b1a2	23	PHY_INTERFACE_MODE_RMII,
75d28899	24	PHY_INTERFACE_MODE_REVRMII,
f070b1a2 JH	25	PHY_INTERFACE_MODE_RGMII,
	26	PHY_INTERFACE_MODE_RGMII_ID,
	27	PHY_INTERFACE_MODE_RGMII_RXID,
	28	PHY_INTERFACE_MODE_RGMII_TXID,
	29	PHY_INTERFACE_MODE_RTBI,
75d28899 MV	30	PHY_INTERFACE_MODE_SMII,
	31	PHY_INTERFACE_MODE_XGMII,
	32	PHY_INTERFACE_MODE_XLGMII,
	33	PHY_INTERFACE_MODE_MOCA,
	34	PHY_INTERFACE_MODE_QSGMII,
	35	PHY_INTERFACE_MODE_TRGMII,
	36	PHY_INTERFACE_MODE_100BASEX,
16bacd5e SC	37	PHY_INTERFACE_MODE_1000BASEX,
16bacd5e SC	38	PHY_INTERFACE_MODE_2500BASEX,
166ea497	39	PHY_INTERFACE_MODE_5GBASER,
75d28899 MV	40	PHY_INTERFACE_MODE_RXAUI,
	41	PHY_INTERFACE_MODE_XAUI,
	42	/* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
	43	PHY_INTERFACE_MODE_10GBASER,
	44	PHY_INTERFACE_MODE_25GBASER,
	45	PHY_INTERFACE_MODE_USXGMII,
	46	/* 10GBASE-KR - with Clause 73 AN */
	47	PHY_INTERFACE_MODE_10GKR,
	48	PHY_INTERFACE_MODE_QUSGMII,
	49	PHY_INTERFACE_MODE_1000BASEKX,
	50	#if defined(CONFIG_ARCH_LX2160A) \|\| defined(CONFIG_ARCH_LX2162A)
	51	/* LX2160A SERDES modes */
5b723986 PJ	52	PHY_INTERFACE_MODE_25G_AUI,
	53	PHY_INTERFACE_MODE_XLAUI,
	54	PHY_INTERFACE_MODE_CAUI2,
	55	PHY_INTERFACE_MODE_CAUI4,
75d28899 MV	56	#endif
75d28899 MV	57	#if defined(CONFIG_PHY_NCSI)
e2ffeaa1	58	PHY_INTERFACE_MODE_NCSI,
75d28899	59	#endif
6706d7dc	60	PHY_INTERFACE_MODE_MAX,
f070b1a2 JH	61	} phy_interface_t;
	62
	63	static const char * const phy_interface_strings[] = {
75d28899 MV	64	[PHY_INTERFACE_MODE_NA] = "",
75d28899 MV	65	[PHY_INTERFACE_MODE_INTERNAL] = "internal",
f070b1a2 JH	66	[PHY_INTERFACE_MODE_MII] = "mii",
	67	[PHY_INTERFACE_MODE_GMII] = "gmii",
	68	[PHY_INTERFACE_MODE_SGMII] = "sgmii",
f070b1a2	69	[PHY_INTERFACE_MODE_TBI] = "tbi",
75d28899	70	[PHY_INTERFACE_MODE_REVMII] = "rev-mii",
f070b1a2	71	[PHY_INTERFACE_MODE_RMII] = "rmii",
75d28899	72	[PHY_INTERFACE_MODE_REVRMII] = "rev-rmii",
f070b1a2 JH	73	[PHY_INTERFACE_MODE_RGMII] = "rgmii",
	74	[PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
	75	[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
	76	[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
	77	[PHY_INTERFACE_MODE_RTBI] = "rtbi",
75d28899 MV	78	[PHY_INTERFACE_MODE_SMII] = "smii",
	79	[PHY_INTERFACE_MODE_XGMII] = "xgmii",
	80	[PHY_INTERFACE_MODE_XLGMII] = "xlgmii",
	81	[PHY_INTERFACE_MODE_MOCA] = "moca",
	82	[PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
	83	[PHY_INTERFACE_MODE_TRGMII] = "trgmii",
16bacd5e	84	[PHY_INTERFACE_MODE_1000BASEX] = "1000base-x",
75d28899	85	[PHY_INTERFACE_MODE_1000BASEKX] = "1000base-kx",
16bacd5e	86	[PHY_INTERFACE_MODE_2500BASEX] = "2500base-x",
166ea497	87	[PHY_INTERFACE_MODE_5GBASER] = "5gbase-r",
75d28899 MV	88	[PHY_INTERFACE_MODE_RXAUI] = "rxaui",
	89	[PHY_INTERFACE_MODE_XAUI] = "xaui",
	90	[PHY_INTERFACE_MODE_10GBASER] = "10gbase-r",
	91	[PHY_INTERFACE_MODE_25GBASER] = "25gbase-r",
	92	[PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
	93	[PHY_INTERFACE_MODE_10GKR] = "10gbase-kr",
	94	[PHY_INTERFACE_MODE_100BASEX] = "100base-x",
	95	[PHY_INTERFACE_MODE_QUSGMII] = "qusgmii",
	96	#if defined(CONFIG_ARCH_LX2160A) \|\| defined(CONFIG_ARCH_LX2162A)
	97	/* LX2160A SERDES modes */
5b723986 PJ	98	[PHY_INTERFACE_MODE_25G_AUI] = "25g-aui",
	99	[PHY_INTERFACE_MODE_XLAUI] = "xlaui4",
	100	[PHY_INTERFACE_MODE_CAUI2] = "caui2",
	101	[PHY_INTERFACE_MODE_CAUI4] = "caui4",
75d28899 MV	102	#endif
75d28899 MV	103	#if defined(CONFIG_PHY_NCSI)
e2ffeaa1	104	[PHY_INTERFACE_MODE_NCSI] = "NC-SI",
75d28899	105	#endif
f070b1a2 JH	106	};
f070b1a2 JH	107
5d3bcdb1 FI	108	/* Backplane modes:
	109	* are considered a sub-type of phy_interface_t: XGMII
	110	* and are specified in "phy-connection-type" with one of the following strings
	111	*/
	112	static const char * const backplane_mode_strings[] = {
	113	"10gbase-kr",
	114	"40gbase-kr4",
	115	};
	116
f070b1a2 JH	117	static inline const char *phy_string_for_interface(phy_interface_t i)
	118	{
	119	/* Default to unknown */
faa6ce60	120	if (i >= PHY_INTERFACE_MODE_MAX)
ffb0f6f4	121	i = PHY_INTERFACE_MODE_NA;
f070b1a2 JH	122
	123	return phy_interface_strings[i];
	124	}
	125
5d3bcdb1 FI	126	static inline bool is_backplane_mode(const char *phyconn)
	127	{
	128	int i;
	129
	130	if (!phyconn)
	131	return false;
	132	for (i = 0; i < ARRAY_SIZE(backplane_mode_strings); i++) {
	133	if (!strcmp(phyconn, backplane_mode_strings[i]))
	134	return true;
	135	}
	136	return false;
	137	}
	138
f070b1a2	139	#endif /* _PHY_INTERFACE_H */