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Commit | Line | Data |
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58894524 RS |
1 | /* |
2 | * Copyright (C) 2012 Samsung Electronics | |
3 | * Rajeshwari Shinde <rajeshwari.s@samsung.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
58894524 RS |
6 | */ |
7 | ||
8 | #ifndef __MAX77686_H_ | |
9 | #define __MAX77686_H_ | |
10 | ||
11 | enum { | |
12 | MAX77686_REG_PMIC_ID = 0x0, | |
13 | MAX77686_REG_PMIC_INTSRC, | |
14 | MAX77686_REG_PMIC_INT1, | |
15 | MAX77686_REG_PMIC_INT2, | |
16 | MAX77686_REG_PMIC_INT1MSK, | |
17 | MAX77686_REG_PMIC_INT2MSK, | |
18 | ||
19 | MAX77686_REG_PMIC_STATUS1, | |
20 | MAX77686_REG_PMIC_STATUS2, | |
21 | ||
22 | MAX77686_REG_PMIC_PWRON, | |
23 | MAX77686_REG_PMIC_ONOFFDELAY, | |
24 | MAX77686_REG_PMIC_MRSTB, | |
25 | ||
26 | MAX77686_REG_PMIC_BUCK1CRTL = 0x10, | |
27 | MAX77686_REG_PMIC_BUCK1OUT, | |
28 | MAX77686_REG_PMIC_BUCK2CTRL1, | |
29 | MAX77686_REG_PMIC_BUCK234FREQ, | |
30 | MAX77686_REG_PMIC_BUCK2DVS1, | |
31 | MAX77686_REG_PMIC_BUCK2DVS2, | |
32 | MAX77686_REG_PMIC_BUCK2DVS3, | |
33 | MAX77686_REG_PMIC_BUCK2DVS4, | |
34 | MAX77686_REG_PMIC_BUCK2DVS5, | |
35 | MAX77686_REG_PMIC_BUCK2DVS6, | |
36 | MAX77686_REG_PMIC_BUCK2DVS7, | |
37 | MAX77686_REG_PMIC_BUCK2DVS8, | |
38 | MAX77686_REG_PMIC_BUCK3CTRL, | |
39 | MAX77686_REG_PMIC_BUCK3DVS1, | |
40 | MAX77686_REG_PMIC_BUCK3DVS2, | |
41 | MAX77686_REG_PMIC_BUCK3DVS3, | |
42 | MAX77686_REG_PMIC_BUCK3DVS4, | |
43 | MAX77686_REG_PMIC_BUCK3DVS5, | |
44 | MAX77686_REG_PMIC_BUCK3DVS6, | |
45 | MAX77686_REG_PMIC_BUCK3DVS7, | |
46 | MAX77686_REG_PMIC_BUCK3DVS8, | |
47 | MAX77686_REG_PMIC_BUCK4CTRL1, | |
48 | MAX77686_REG_PMIC_BUCK4DVS1 = 0x28, | |
49 | MAX77686_REG_PMIC_BUCK4DVS2, | |
50 | MAX77686_REG_PMIC_BUCK4DVS3, | |
51 | MAX77686_REG_PMIC_BUCK4DVS4, | |
52 | MAX77686_REG_PMIC_BUCK4DVS5, | |
53 | MAX77686_REG_PMIC_BUCK4DVS6, | |
54 | MAX77686_REG_PMIC_BUCK4DVS7, | |
55 | MAX77686_REG_PMIC_BUCK4DVS8, | |
56 | MAX77686_REG_PMIC_BUCK5CTRL, | |
57 | MAX77686_REG_PMIC_BUCK5OUT, | |
58 | MAX77686_REG_PMIC_BUCK6CRTL, | |
59 | MAX77686_REG_PMIC_BUCK6OUT, | |
60 | MAX77686_REG_PMIC_BUCK7CRTL, | |
61 | MAX77686_REG_PMIC_BUCK7OUT, | |
62 | MAX77686_REG_PMIC_BUCK8CRTL, | |
63 | MAX77686_REG_PMIC_BUCK8OUT, | |
64 | MAX77686_REG_PMIC_BUCK9CRTL, | |
65 | MAX77686_REG_PMIC_BUCK9OUT, | |
66 | ||
67 | MAX77686_REG_PMIC_LDO1CTRL1 = 0x40, | |
68 | MAX77686_REG_PMIC_LDO2CTRL1, | |
69 | MAX77686_REG_PMIC_LDO3CTRL1, | |
70 | MAX77686_REG_PMIC_LDO4CTRL1, | |
71 | MAX77686_REG_PMIC_LDO5CTRL1, | |
72 | MAX77686_REG_PMIC_LDO6CTRL1, | |
73 | MAX77686_REG_PMIC_LDO7CTRL1, | |
74 | MAX77686_REG_PMIC_LDO8CTRL1, | |
75 | MAX77686_REG_PMIC_LDO9CTRL1, | |
76 | MAX77686_REG_PMIC_LDO10CTRL1, | |
77 | MAX77686_REG_PMIC_LDO11CTRL1, | |
78 | MAX77686_REG_PMIC_LDO12CTRL1, | |
79 | MAX77686_REG_PMIC_LDO13CTRL1, | |
80 | MAX77686_REG_PMIC_LDO14CTRL1, | |
81 | MAX77686_REG_PMIC_LDO15CTRL1, | |
82 | MAX77686_REG_PMIC_LDO16CTRL1, | |
83 | MAX77686_REG_PMIC_LDO17CTRL1, | |
84 | MAX77686_REG_PMIC_LDO18CTRL1, | |
85 | MAX77686_REG_PMIC_LDO19CTRL1, | |
86 | MAX77686_REG_PMIC_LDO20CTRL1, | |
87 | MAX77686_REG_PMIC_LDO21CTRL1, | |
88 | MAX77686_REG_PMIC_LDO22CTRL1, | |
89 | MAX77686_REG_PMIC_LDO23CTRL1, | |
90 | MAX77686_REG_PMIC_LDO24CTRL1, | |
91 | MAX77686_REG_PMIC_LDO25CTRL1, | |
92 | MAX77686_REG_PMIC_LDO26CTRL1, | |
93 | MAX77686_REG_PMIC_LDO1CTRL2, | |
94 | MAX77686_REG_PMIC_LDO2CTRL2, | |
95 | MAX77686_REG_PMIC_LDO3CTRL2, | |
96 | MAX77686_REG_PMIC_LDO4CTRL2, | |
97 | MAX77686_REG_PMIC_LDO5CTRL2, | |
98 | MAX77686_REG_PMIC_LDO6CTRL2, | |
99 | MAX77686_REG_PMIC_LDO7CTRL2, | |
100 | MAX77686_REG_PMIC_LDO8CTRL2, | |
101 | MAX77686_REG_PMIC_LDO9CTRL2, | |
102 | MAX77686_REG_PMIC_LDO10CTRL2, | |
103 | MAX77686_REG_PMIC_LDO11CTRL2, | |
104 | MAX77686_REG_PMIC_LDO12CTRL2, | |
105 | MAX77686_REG_PMIC_LDO13CTRL2, | |
106 | MAX77686_REG_PMIC_LDO14CTRL2, | |
107 | MAX77686_REG_PMIC_LDO15CTRL2, | |
108 | MAX77686_REG_PMIC_LDO16CTRL2, | |
109 | MAX77686_REG_PMIC_LDO17CTRL2, | |
110 | MAX77686_REG_PMIC_LDO18CTRL2, | |
111 | MAX77686_REG_PMIC_LDO19CTRL2, | |
112 | MAX77686_REG_PMIC_LDO20CTRL2, | |
113 | MAX77686_REG_PMIC_LDO21CTRL2, | |
114 | MAX77686_REG_PMIC_LDO22CTRL2, | |
115 | MAX77686_REG_PMIC_LDO23CTRL2, | |
116 | MAX77686_REG_PMIC_LDO24CTRL2, | |
117 | MAX77686_REG_PMIC_LDO25CTRL2, | |
118 | MAX77686_REG_PMIC_LDO26CTRL2, | |
119 | ||
120 | MAX77686_REG_PMIC_BBAT = 0x7e, | |
121 | MAX77686_REG_PMIC_32KHZ, | |
122 | ||
123 | PMIC_NUM_OF_REGS, | |
124 | }; | |
125 | ||
126 | /* I2C device address for pmic max77686 */ | |
127 | #define MAX77686_I2C_ADDR (0x12 >> 1) | |
128 | ||
129 | enum { | |
130 | REG_DISABLE = 0, | |
131 | REG_ENABLE | |
132 | }; | |
133 | ||
134 | enum { | |
135 | LDO_OFF = 0, | |
136 | LDO_ON, | |
137 | ||
138 | DIS_LDO = (0x00 << 6), | |
139 | EN_LDO = (0x3 << 6), | |
140 | }; | |
141 | ||
812d7576 PW |
142 | enum { |
143 | OPMODE_OFF = 0, | |
144 | OPMODE_STANDBY, | |
145 | OPMODE_LPM, | |
146 | OPMODE_ON, | |
147 | }; | |
148 | ||
149 | int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV); | |
150 | int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode); | |
151 | int max77686_set_buck_mode(struct pmic *p, int buck, char opmode); | |
152 | ||
153 | #define MAX77686_LDO_VOLT_MAX_HEX 0x3f | |
154 | #define MAX77686_LDO_VOLT_MASK 0x3f | |
155 | #define MAX77686_LDO_MODE_MASK 0xc0 | |
156 | #define MAX77686_LDO_MODE_OFF (0x00 << 0x06) | |
157 | #define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06) | |
158 | #define MAX77686_LDO_MODE_LPM (0x02 << 0x06) | |
159 | #define MAX77686_LDO_MODE_ON (0x03 << 0x06) | |
160 | #define MAX77686_BUCK_MODE_MASK 0x03 | |
161 | #define MAX77686_BUCK_MODE_SHIFT_1 0x00 | |
162 | #define MAX77686_BUCK_MODE_SHIFT_2 0x04 | |
163 | #define MAX77686_BUCK_MODE_OFF 0x00 | |
164 | #define MAX77686_BUCK_MODE_STANDBY 0x01 | |
165 | #define MAX77686_BUCK_MODE_LPM 0x02 | |
166 | #define MAX77686_BUCK_MODE_ON 0x03 | |
167 | ||
b278c409 RS |
168 | /* Buck1 1 volt value */ |
169 | #define MAX77686_BUCK1OUT_1V 0x5 | |
2955d600 BT |
170 | /* Buck1 1.05 volt value */ |
171 | #define MAX77686_BUCK1OUT_1_05V 0x6 | |
b278c409 RS |
172 | #define MAX77686_BUCK1CTRL_EN (3 << 0) |
173 | /* Buck2 1.3 volt value */ | |
174 | #define MAX77686_BUCK2DVS1_1_3V 0x38 | |
175 | #define MAX77686_BUCK2CTRL_ON (1 << 4) | |
176 | /* Buck3 1.0125 volt value */ | |
177 | #define MAX77686_BUCK3DVS1_1_0125V 0x21 | |
178 | #define MAX77686_BUCK3CTRL_ON (1 << 4) | |
179 | /* Buck4 1.2 volt value */ | |
180 | #define MAX77686_BUCK4DVS1_1_2V 0x30 | |
181 | #define MAX77686_BUCK4CTRL_ON (1 << 4) | |
182 | /* LDO2 1.5 volt value */ | |
183 | #define MAX77686_LD02CTRL1_1_5V 0x1c | |
184 | /* LDO3 1.8 volt value */ | |
185 | #define MAX77686_LD03CTRL1_1_8V 0x14 | |
186 | /* LDO5 1.8 volt value */ | |
187 | #define MAX77686_LD05CTRL1_1_8V 0x14 | |
188 | /* LDO10 1.8 volt value */ | |
189 | #define MAX77686_LD10CTRL1_1_8V 0x14 | |
190 | /* | |
191 | * MAX77686_REG_PMIC_32KHZ set to 32KH CP | |
192 | * output is activated | |
193 | */ | |
194 | #define MAX77686_32KHCP_EN (1 << 1) | |
195 | /* | |
196 | * MAX77686_REG_PMIC_BBAT set to | |
197 | * Back up batery charger on and | |
198 | * limit voltage setting to 3.5v | |
199 | */ | |
200 | #define MAX77686_BBCHOSTEN (1 << 0) | |
201 | #define MAX77686_BBCVS_3_5V (3 << 3) | |
58894524 | 202 | #endif /* __MAX77686_PMIC_H_ */ |