projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0442ed86 WD |
1 | /*----------------------------------------------------------------------------+ |
| 2 | | | |
| 3 | | This source code has been made available to you by IBM on an AS-IS | |
| 4 | | basis. Anyone receiving this source is licensed under IBM | |
| 5 | | copyrights to use it in any way he or she deems fit, including | |
| 6 | | copying it, modifying it, compiling it, and redistributing it either | |
| 7 | | with or without modifications. No license under IBM patents or | |
| 8 | | patent applications is to be implied by the copyright license. | |
| 9 | | | |
| 10 | | Any user of this software should understand that IBM cannot provide | |
| 11 | | technical support for this software and will not be responsible for | |
| 12 | | any consequences resulting from the use of this software. | |
| 13 | | | |
| 14 | | Any person who transfers this source code or any derivative work | |
| 15 | | must include the IBM copyright notice, this paragraph, and the | |
| 16 | | preceding two paragraphs in the transferred software. | |
| 17 | | | |
| 18 | | COPYRIGHT I B M CORPORATION 1999 | |
| 19 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
| 20 | +----------------------------------------------------------------------------*/ | |
| 21 | ||
| 22 | #ifndef __PPC405_H__ | |
| 23 | #define __PPC405_H__ | |
| 24 | ||
| 9b94ac61 SR |
25 | #ifndef CONFIG_IOP480 |
| 26 | #define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ | |
| 27 | #else | |
| 28 | #define CFG_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */ | |
| 29 | #endif | |
| 30 | ||
| 0442ed86 WD |
31 | /*--------------------------------------------------------------------- */ |
| 32 | /* Special Purpose Registers */ | |
| 33 | /*--------------------------------------------------------------------- */ | |
| 8bde7f77 WD |
34 | #define srr2 0x3de /* save/restore register 2 */ |
| 35 | #define srr3 0x3df /* save/restore register 3 */ | |
| efa35cf1 GB |
36 | |
| 37 | /* | |
| 38 | * 405 does not really have CSRR0/1 but SRR2/3 are used during critical | |
| 39 | * exception for the exact same purposes - let's alias them and have a | |
| 40 | * common handling in crit_return() and CRIT_EXCEPTION | |
| 41 | */ | |
| 42 | #define csrr0 srr2 | |
| 43 | #define csrr1 srr3 | |
| 44 | ||
| 0442ed86 WD |
45 | #define dbsr 0x3f0 /* debug status register */ |
| 46 | #define dbcr0 0x3f2 /* debug control register 0 */ | |
| 47 | #define dbcr1 0x3bd /* debug control register 1 */ | |
| 48 | #define iac1 0x3f4 /* instruction address comparator 1 */ | |
| 49 | #define iac2 0x3f5 /* instruction address comparator 2 */ | |
| 50 | #define iac3 0x3b4 /* instruction address comparator 3 */ | |
| 51 | #define iac4 0x3b5 /* instruction address comparator 4 */ | |
| 52 | #define dac1 0x3f6 /* data address comparator 1 */ | |
| 53 | #define dac2 0x3f7 /* data address comparator 2 */ | |
| 54 | #define dccr 0x3fa /* data cache control register */ | |
| 55 | #define iccr 0x3fb /* instruction cache control register */ | |
| 56 | #define esr 0x3d4 /* execption syndrome register */ | |
| 57 | #define dear 0x3d5 /* data exeption address register */ | |
| 58 | #define evpr 0x3d6 /* exeption vector prefix register */ | |
| 59 | #define tsr 0x3d8 /* timer status register */ | |
| 60 | #define tcr 0x3da /* timer control register */ | |
| 61 | #define pit 0x3db /* programmable interval timer */ | |
| 8bde7f77 WD |
62 | #define sgr 0x3b9 /* storage guarded reg */ |
| 63 | #define dcwr 0x3ba /* data cache write-thru reg*/ | |
| 64 | #define sler 0x3bb /* storage little-endian reg */ | |
| 0442ed86 WD |
65 | #define cdbcr 0x3d7 /* cache debug cntrl reg */ |
| 66 | #define icdbdr 0x3d3 /* instr cache dbug data reg*/ | |
| 67 | #define ccr0 0x3b3 /* core configuration register */ | |
| 68 | #define dvc1 0x3b6 /* data value compare register 1 */ | |
| 69 | #define dvc2 0x3b7 /* data value compare register 2 */ | |
| 70 | #define pid 0x3b1 /* process ID */ | |
| 71 | #define su0r 0x3bc /* storage user-defined register 0 */ | |
| 72 | #define zpr 0x3b0 /* zone protection regsiter */ | |
| 73 | ||
| 8bde7f77 WD |
74 | #define tbl 0x11c /* time base lower - privileged write */ |
| 75 | #define tbu 0x11d /* time base upper - privileged write */ | |
| 0442ed86 WD |
76 | |
| 77 | #define sprg4r 0x104 /* Special purpose general 4 - read only */ | |
| 78 | #define sprg5r 0x105 /* Special purpose general 5 - read only */ | |
| 79 | #define sprg6r 0x106 /* Special purpose general 6 - read only */ | |
| 80 | #define sprg7r 0x107 /* Special purpose general 7 - read only */ | |
| 81 | #define sprg4w 0x114 /* Special purpose general 4 - write only */ | |
| 82 | #define sprg5w 0x115 /* Special purpose general 5 - write only */ | |
| 83 | #define sprg6w 0x116 /* Special purpose general 6 - write only */ | |
| 84 | #define sprg7w 0x117 /* Special purpose general 7 - write only */ | |
| 85 | ||
| 86 | /****************************************************************************** | |
| 87 | * Special for PPC405GP | |
| 88 | ******************************************************************************/ | |
| 89 | ||
| 90 | /****************************************************************************** | |
| 91 | * DMA | |
| 92 | ******************************************************************************/ | |
| 93 | #define DMA_DCR_BASE 0x100 | |
| 94 | #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ | |
| 95 | #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ | |
| 96 | #define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ | |
| 97 | #define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ | |
| 98 | #define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ | |
| 99 | #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ | |
| 100 | #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ | |
| 101 | #define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ | |
| 102 | #define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ | |
| 103 | #define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ | |
| 104 | #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ | |
| 105 | #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ | |
| 106 | #define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ | |
| 107 | #define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ | |
| 108 | #define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ | |
| 109 | #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ | |
| 110 | #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ | |
| 111 | #define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ | |
| 112 | #define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ | |
| 113 | #define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ | |
| 114 | #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ | |
| 115 | #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ | |
| 116 | #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ | |
| 117 | ||
| 118 | /****************************************************************************** | |
| 119 | * Universal interrupt controller | |
| 120 | ******************************************************************************/ | |
| 6f2eb3f3 SR |
121 | #define UIC_SR 0x0 /* UIC status */ |
| 122 | #define UIC_ER 0x2 /* UIC enable */ | |
| 123 | #define UIC_CR 0x3 /* UIC critical */ | |
| 124 | #define UIC_PR 0x4 /* UIC polarity */ | |
| 125 | #define UIC_TR 0x5 /* UIC triggering */ | |
| 126 | #define UIC_MSR 0x6 /* UIC masked status */ | |
| 127 | #define UIC_VR 0x7 /* UIC vector */ | |
| 128 | #define UIC_VCR 0x8 /* UIC vector configuration */ | |
| 129 | ||
| 0442ed86 | 130 | #define UIC_DCR_BASE 0xc0 |
| 6f2eb3f3 | 131 | #define UIC0_DCR_BASE UIC_DCR_BASE |
| 0442ed86 WD |
132 | #define uicsr (UIC_DCR_BASE+0x0) /* UIC status */ |
| 133 | #define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */ | |
| 134 | #define uicer (UIC_DCR_BASE+0x2) /* UIC enable */ | |
| 135 | #define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */ | |
| 136 | #define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */ | |
| 137 | #define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */ | |
| 138 | #define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */ | |
| 139 | #define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ | |
| 140 | #define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ | |
| 141 | ||
| dbbd1257 SR |
142 | #if defined(CONFIG_405EX) |
| 143 | #define uic0sr uicsr /* UIC status */ | |
| 144 | #define uic0srs uicsrs /* UIC status set */ | |
| 145 | #define uic0er uicer /* UIC enable */ | |
| 146 | #define uic0cr uiccr /* UIC critical */ | |
| 147 | #define uic0pr uicpr /* UIC polarity */ | |
| 148 | #define uic0tr uictr /* UIC triggering */ | |
| 149 | #define uic0msr uicmsr /* UIC masked status */ | |
| 150 | #define uic0vr uicvr /* UIC vector */ | |
| 151 | #define uic0vcr uicvcr /* UIC vector configuration*/ | |
| 152 | ||
| 153 | #define UIC_DCR_BASE1 0xd0 | |
| 6f2eb3f3 | 154 | #define UIC1_DCR_BASE 0xd0 |
| dbbd1257 SR |
155 | #define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */ |
| 156 | #define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */ | |
| 157 | #define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */ | |
| 158 | #define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */ | |
| 159 | #define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */ | |
| 160 | #define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */ | |
| 161 | #define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */ | |
| 162 | #define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */ | |
| 163 | #define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/ | |
| 164 | ||
| 165 | #define UIC_DCR_BASE2 0xe0 | |
| 6f2eb3f3 | 166 | #define UIC2_DCR_BASE 0xe0 |
| dbbd1257 SR |
167 | #define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */ |
| 168 | #define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */ | |
| 169 | #define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */ | |
| 170 | #define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */ | |
| 171 | #define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */ | |
| 172 | #define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */ | |
| 173 | #define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */ | |
| 174 | #define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */ | |
| 175 | #define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/ | |
| 176 | #endif | |
| 177 | ||
| 0442ed86 WD |
178 | /*-----------------------------------------------------------------------------+ |
| 179 | | Universal interrupt controller interrupts | |
| 180 | +-----------------------------------------------------------------------------*/ | |
| e01bd218 SR |
181 | #if defined(CONFIG_405EZ) |
| 182 | #define UIC_DMA0 0x80000000 /* DMA chan. 0 */ | |
| 183 | #define UIC_DMA1 0x40000000 /* DMA chan. 1 */ | |
| 184 | #define UIC_DMA2 0x20000000 /* DMA chan. 2 */ | |
| 185 | #define UIC_DMA3 0x10000000 /* DMA chan. 3 */ | |
| 186 | #define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */ | |
| 187 | #define UIC_UART0 0x04000000 /* UART 0 */ | |
| 188 | #define UIC_UART1 0x02000000 /* UART 1 */ | |
| 189 | #define UIC_CAN0 0x01000000 /* CAN 0 */ | |
| 190 | #define UIC_CAN1 0x00800000 /* CAN 1 */ | |
| 191 | #define UIC_SPI 0x00400000 /* SPI */ | |
| 192 | #define UIC_IIC 0x00200000 /* IIC */ | |
| 193 | #define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */ | |
| 194 | #define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */ | |
| 195 | #define UIC_USBH1 0x00040000 /* USB Host 1 */ | |
| 196 | #define UIC_USBH2 0x00020000 /* USB Host 2 */ | |
| 197 | #define UIC_USBDEV 0x00010000 /* USB Device */ | |
| 1636d1c8 WD |
198 | #define UIC_ENET 0x00008000 /* Ethernet interrupt status */ |
| 199 | #define UIC_ENET1 0x00008000 /* dummy define */ | |
| e01bd218 SR |
200 | #define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */ |
| 201 | ||
| 202 | #define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */ | |
| 1636d1c8 | 203 | #define UIC_MAL_SERR 0x00002000 /* MAL SERR */ |
| e01bd218 SR |
204 | #define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */ |
| 205 | #define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */ | |
| 206 | ||
| 207 | #define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */ | |
| 208 | #define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */ | |
| 209 | #define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */ | |
| 210 | #define UIC_NAND 0x00000200 /* NAND Flash controller */ | |
| 211 | #define UIC_ADC 0x00000100 /* ADC */ | |
| 212 | #define UIC_DAC 0x00000080 /* DAC */ | |
| 213 | #define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */ | |
| 214 | #define UIC_RESERVED0 0x00000020 /* Reserved */ | |
| 215 | #define UIC_EXT0 0x00000010 /* External interrupt 0 */ | |
| 216 | #define UIC_EXT1 0x00000008 /* External interrupt 1 */ | |
| 217 | #define UIC_EXT2 0x00000004 /* External interrupt 2 */ | |
| 218 | #define UIC_EXT3 0x00000002 /* External interrupt 3 */ | |
| 219 | #define UIC_EXT4 0x00000001 /* External interrupt 4 */ | |
| 220 | ||
| dbbd1257 SR |
221 | #elif defined(CONFIG_405EX) |
| 222 | ||
| 223 | /* UIC 0 */ | |
| 224 | #define UIC_U0 0x80000000 /* */ | |
| 225 | #define UIC_U1 0x40000000 /* */ | |
| 226 | #define UIC_IIC0 0x20000000 /* */ | |
| 227 | #define UIC_PKA 0x10000000 /* */ | |
| 228 | #define UIC_TRNG 0x08000000 /* */ | |
| 229 | #define UIC_EBM 0x04000000 /* */ | |
| 230 | #define UIC_BGI 0x02000000 /* */ | |
| 231 | #define UIC_IIC1 0x01000000 /* */ | |
| 232 | #define UIC_SPI 0x00800000 /* */ | |
| 233 | #define UIC_EIRQ0 0x00400000 /**/ | |
| 234 | #define UIC_MTE 0x00200000 /*MAL Tx EOB */ | |
| 235 | #define UIC_MRE 0x00100000 /*MAL Rx EOB */ | |
| 236 | #define UIC_DMA0 0x00080000 /* */ | |
| 237 | #define UIC_DMA1 0x00040000 /* */ | |
| 238 | #define UIC_DMA2 0x00020000 /* */ | |
| 239 | #define UIC_DMA3 0x00010000 /* */ | |
| 240 | #define UIC_PCIE0AL 0x00008000 /* */ | |
| 241 | #define UIC_PCIE0VPD 0x00004000 /* */ | |
| 242 | #define UIC_RPCIE0HRST 0x00002000 /* */ | |
| 243 | #define UIC_FPCIE0HRST 0x00001000 /* */ | |
| 244 | #define UIC_PCIE0TCR 0x00000800 /* */ | |
| 245 | #define UIC_PCIEMSI0 0x00000400 /* */ | |
| 246 | #define UIC_PCIEMSI1 0x00000200 /* */ | |
| 247 | #define UIC_SECURITY 0x00000100 /* */ | |
| 248 | #define UIC_ENET 0x00000080 /* */ | |
| 249 | #define UIC_ENET1 0x00000040 /* */ | |
| 250 | #define UIC_PCIEMSI2 0x00000020 /* */ | |
| 251 | #define UIC_EIRQ4 0x00000010 /**/ | |
| 6f2eb3f3 SR |
252 | #define UICB0_UIC2NCI 0x00000008 /* */ |
| 253 | #define UICB0_UIC2CI 0x00000004 /* */ | |
| 254 | #define UICB0_UIC1NCI 0x00000002 /* */ | |
| 255 | #define UICB0_UIC1CI 0x00000001 /* */ | |
| 256 | ||
| 257 | #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ | |
| 258 | UICB0_UIC1CI | UICB0_UIC2NCI) | |
| dbbd1257 SR |
259 | |
| 260 | #define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */ | |
| 261 | #define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */ | |
| 262 | /* UIC 1 */ | |
| 263 | #define UIC_MS 0x80000000 /* MAL SERR */ | |
| 264 | #define UIC_MTDE 0x40000000 /* MAL TXDE */ | |
| 265 | #define UIC_MRDE 0x20000000 /* MAL RXDE */ | |
| 266 | #define UIC_PCIE0BMVC0 0x10000000 /* */ | |
| 267 | #define UIC_PCIE0DCRERR 0x08000000 /* */ | |
| 268 | #define UIC_EBC 0x04000000 /* */ | |
| 269 | #define UIC_NDFC 0x02000000 /* */ | |
| 270 | #define UIC_PCEI1DCRERR 0x01000000 /* */ | |
| 271 | #define UIC_GPTCMPT8 0x00800000 /* */ | |
| 272 | #define UIC_GPTCMPT9 0x00400000 /* */ | |
| 273 | #define UIC_PCIE1AL 0x00200000 /* */ | |
| 274 | #define UIC_PCIE1VPD 0x00100000 /* */ | |
| 275 | #define UIC_RPCE1HRST 0x00080000 /* */ | |
| 276 | #define UIC_FPCE1HRST 0x00040000 /* */ | |
| 277 | #define UIC_PCIE1TCR 0x00020000 /* */ | |
| 278 | #define UIC_PCIE1VC0 0x00010000 /* */ | |
| 279 | #define UIC_GPTCMPT3 0x00008000 /* */ | |
| 280 | #define UIC_GPTCMPT4 0x00004000 /* */ | |
| 281 | #define UIC_EIRQ7 0x00002000 /* */ | |
| 282 | #define UIC_EIRQ8 0x00001000 /* */ | |
| 283 | #define UIC_EIRQ9 0x00000800 /* */ | |
| 284 | #define UIC_GPTCMP5 0x00000400 /* */ | |
| 285 | #define UIC_GPTCMP6 0x00000200 /* */ | |
| 286 | #define UIC_GPTCMP7 0x00000100 /* */ | |
| 287 | #define UIC_SROM 0x00000080 /* SERIAL ROM*/ | |
| 288 | #define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/ | |
| 289 | #define UIC_EIRQ2 0x00000020 /* */ | |
| 290 | #define UIC_EIRQ5 0x00000010 /* */ | |
| 291 | #define UIC_EIRQ6 0x00000008 /* */ | |
| 292 | #define UIC_EMAC0WAKE 0x00000004 /* */ | |
| 293 | #define UIC_EIRQ1 0x00000002 /* */ | |
| 294 | #define UIC_EMAC1WAKE 0x00000001 /* */ | |
| 295 | #define UIC_MAL_SERR UIC_MS /* MAL SERR */ | |
| 296 | #define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */ | |
| 297 | #define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */ | |
| 298 | /* UIC 2 */ | |
| 299 | #define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/ | |
| 300 | #define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/ | |
| 301 | #define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/ | |
| 302 | #define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/ | |
| 303 | #define UIC_EIRQ3 0x08000000 /* External IRQ 3*/ | |
| 304 | #define UIC_DDRMCUE 0x04000000 /* */ | |
| 305 | #define UIC_DDRMCCE 0x02000000 /* */ | |
| 306 | #define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/ | |
| 307 | #define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/ | |
| 308 | #define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/ | |
| 309 | #define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/ | |
| 310 | #define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/ | |
| 311 | #define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/ | |
| 312 | #define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/ | |
| 313 | #define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/ | |
| 314 | #define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/ | |
| 315 | #define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/ | |
| 316 | #define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/ | |
| 317 | #define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/ | |
| 318 | #define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/ | |
| 319 | #define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/ | |
| 320 | #define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/ | |
| 321 | #define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/ | |
| 322 | #define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/ | |
| 323 | #define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/ | |
| 324 | #define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/ | |
| 325 | #define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/ | |
| 326 | #define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/ | |
| 327 | #define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/ | |
| 328 | #define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/ | |
| 329 | #define UIC_USBWAKE 0x00000002 /* USB wakup*/ | |
| 330 | #define UIC_USBOTG 0x00000001 /* USB OTG*/ | |
| 331 | #define UIC_ETH0 UIC_ENET | |
| 332 | #define UIC_ETH1 UIC_ENET1 | |
| 333 | ||
| e01bd218 SR |
334 | #else /* !defined(CONFIG_405EZ) */ |
| 335 | ||
| 0442ed86 WD |
336 | #define UIC_UART0 0x80000000 /* UART 0 */ |
| 337 | #define UIC_UART1 0x40000000 /* UART 1 */ | |
| 338 | #define UIC_IIC 0x20000000 /* IIC */ | |
| 339 | #define UIC_EXT_MAST 0x10000000 /* External Master */ | |
| 340 | #define UIC_PCI 0x08000000 /* PCI write to command reg */ | |
| 341 | #define UIC_DMA0 0x04000000 /* DMA chan. 0 */ | |
| 342 | #define UIC_DMA1 0x02000000 /* DMA chan. 1 */ | |
| 343 | #define UIC_DMA2 0x01000000 /* DMA chan. 2 */ | |
| 344 | #define UIC_DMA3 0x00800000 /* DMA chan. 3 */ | |
| 345 | #define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */ | |
| 346 | #define UIC_MAL_SERR 0x00200000 /* MAL SERR */ | |
| 347 | #define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */ | |
| 348 | #define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */ | |
| 349 | #define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */ | |
| 350 | #define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */ | |
| cea655a2 WD |
351 | #define UIC_ENET 0x00010000 /* Ethernet0 */ |
| 352 | #define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */ | |
| 353 | #define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */ | |
| 0442ed86 | 354 | #define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */ |
| 0442ed86 WD |
355 | #define UIC_PCI_PM 0x00002000 /* PCI Power Management */ |
| 356 | #define UIC_EXT0 0x00000040 /* External interrupt 0 */ | |
| 357 | #define UIC_EXT1 0x00000020 /* External interrupt 1 */ | |
| 358 | #define UIC_EXT2 0x00000010 /* External interrupt 2 */ | |
| 359 | #define UIC_EXT3 0x00000008 /* External interrupt 3 */ | |
| 360 | #define UIC_EXT4 0x00000004 /* External interrupt 4 */ | |
| 361 | #define UIC_EXT5 0x00000002 /* External interrupt 5 */ | |
| 362 | #define UIC_EXT6 0x00000001 /* External interrupt 6 */ | |
| e01bd218 | 363 | #endif /* defined(CONFIG_405EZ) */ |
| 0442ed86 WD |
364 | |
| 365 | /****************************************************************************** | |
| 366 | * SDRAM Controller | |
| 367 | ******************************************************************************/ | |
| 0442ed86 | 368 | /* values for memcfga register - indirect addressing of these regs */ |
| b867d705 | 369 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
370 | #define mem_besra 0x00 /* bus error syndrome reg a */ |
| 371 | #define mem_besrsa 0x04 /* bus error syndrome reg set a */ | |
| 372 | #define mem_besrb 0x08 /* bus error syndrome reg b */ | |
| 373 | #define mem_besrsb 0x0c /* bus error syndrome reg set b */ | |
| 374 | #define mem_bear 0x10 /* bus error address reg */ | |
| b867d705 | 375 | #endif |
| 0442ed86 | 376 | #define mem_mcopt1 0x20 /* memory controller options 1 */ |
| ca43ba18 | 377 | #define mem_status 0x24 /* memory status */ |
| 0442ed86 WD |
378 | #define mem_rtr 0x30 /* refresh timer reg */ |
| 379 | #define mem_pmit 0x34 /* power management idle timer */ | |
| 380 | #define mem_mb0cf 0x40 /* memory bank 0 configuration */ | |
| 381 | #define mem_mb1cf 0x44 /* memory bank 1 configuration */ | |
| e075fbe6 | 382 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
383 | #define mem_mb2cf 0x48 /* memory bank 2 configuration */ |
| 384 | #define mem_mb3cf 0x4c /* memory bank 3 configuration */ | |
| e075fbe6 | 385 | #endif |
| 0442ed86 | 386 | #define mem_sdtr1 0x80 /* timing reg 1 */ |
| b867d705 | 387 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
388 | #define mem_ecccf 0x94 /* ECC configuration */ |
| 389 | #define mem_eccerr 0x98 /* ECC error status */ | |
| b867d705 | 390 | #endif |
| 0442ed86 | 391 | |
| e075fbe6 | 392 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
393 | /****************************************************************************** |
| 394 | * Decompression Controller | |
| 395 | ******************************************************************************/ | |
| 396 | #define DECOMP_DCR_BASE 0x14 | |
| 397 | #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ | |
| 398 | #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ | |
| 399 | /* values for kiar register - indirect addressing of these regs */ | |
| 400 | #define kitor0 0x00 /* index table origin register 0 */ | |
| 401 | #define kitor1 0x01 /* index table origin register 1 */ | |
| 402 | #define kitor2 0x02 /* index table origin register 2 */ | |
| 403 | #define kitor3 0x03 /* index table origin register 3 */ | |
| 404 | #define kaddr0 0x04 /* address decode definition regsiter 0 */ | |
| 405 | #define kaddr1 0x05 /* address decode definition regsiter 1 */ | |
| 406 | #define kconf 0x40 /* decompression core config register */ | |
| 407 | #define kid 0x41 /* decompression core ID register */ | |
| 408 | #define kver 0x42 /* decompression core version # reg */ | |
| 409 | #define kpear 0x50 /* bus error addr reg (PLB addr) */ | |
| 410 | #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ | |
| 411 | #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ | |
| 412 | #define kesr0s 0x53 /* bus error status reg 0 (set) */ | |
| 413 | /* There are 0x400 of the following registers, from krom0 to krom3ff*/ | |
| 414 | /* Only the first one is given here. */ | |
| 415 | #define krom0 0x400 /* SRAM/ROM read/write */ | |
| e075fbe6 | 416 | #endif |
| 0442ed86 WD |
417 | |
| 418 | /****************************************************************************** | |
| 419 | * Power Management | |
| 420 | ******************************************************************************/ | |
| dbbd1257 SR |
421 | #ifdef CONFIG_405EX |
| 422 | #define POWERMAN_DCR_BASE 0xb0 | |
| 423 | #else | |
| 0442ed86 | 424 | #define POWERMAN_DCR_BASE 0xb8 |
| dbbd1257 | 425 | #endif |
| 0442ed86 WD |
426 | #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ |
| 427 | #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ | |
| 428 | #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ | |
| 429 | ||
| 430 | /****************************************************************************** | |
| 431 | * Extrnal Bus Controller | |
| 432 | ******************************************************************************/ | |
| 0442ed86 WD |
433 | /* values for ebccfga register - indirect addressing of these regs */ |
| 434 | #define pb0cr 0x00 /* periph bank 0 config reg */ | |
| 435 | #define pb1cr 0x01 /* periph bank 1 config reg */ | |
| 436 | #define pb2cr 0x02 /* periph bank 2 config reg */ | |
| 437 | #define pb3cr 0x03 /* periph bank 3 config reg */ | |
| 438 | #define pb4cr 0x04 /* periph bank 4 config reg */ | |
| e075fbe6 | 439 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
440 | #define pb5cr 0x05 /* periph bank 5 config reg */ |
| 441 | #define pb6cr 0x06 /* periph bank 6 config reg */ | |
| 442 | #define pb7cr 0x07 /* periph bank 7 config reg */ | |
| e075fbe6 | 443 | #endif |
| 0442ed86 WD |
444 | #define pb0ap 0x10 /* periph bank 0 access parameters */ |
| 445 | #define pb1ap 0x11 /* periph bank 1 access parameters */ | |
| 446 | #define pb2ap 0x12 /* periph bank 2 access parameters */ | |
| 447 | #define pb3ap 0x13 /* periph bank 3 access parameters */ | |
| 448 | #define pb4ap 0x14 /* periph bank 4 access parameters */ | |
| e075fbe6 | 449 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
450 | #define pb5ap 0x15 /* periph bank 5 access parameters */ |
| 451 | #define pb6ap 0x16 /* periph bank 6 access parameters */ | |
| 452 | #define pb7ap 0x17 /* periph bank 7 access parameters */ | |
| e075fbe6 | 453 | #endif |
| 0442ed86 WD |
454 | #define pbear 0x20 /* periph bus error addr reg */ |
| 455 | #define pbesr0 0x21 /* periph bus error status reg 0 */ | |
| 456 | #define pbesr1 0x22 /* periph bus error status reg 1 */ | |
| 457 | #define epcr 0x23 /* external periph control reg */ | |
| 4745acaa | 458 | #define EBC0_CFG 0x23 /* external bus configuration reg */ |
| 0442ed86 | 459 | |
| b867d705 SR |
460 | #ifdef CONFIG_405EP |
| 461 | /****************************************************************************** | |
| 462 | * Control | |
| 463 | ******************************************************************************/ | |
| 464 | #define CNTRL_DCR_BASE 0x0f0 | |
| 465 | #define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ | |
| 466 | #define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ | |
| 467 | #define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ | |
| 468 | #define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ | |
| 469 | #define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ | |
| 470 | #define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ | |
| 471 | ||
| 472 | #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ | |
| 473 | #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ | |
| 474 | #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ | |
| 475 | #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ | |
| 476 | #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ | |
| 477 | #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ | |
| 478 | #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ | |
| 479 | #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ | |
| 480 | #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ | |
| 481 | #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ | |
| 482 | ||
| 483 | /* Bit definitions */ | |
| 484 | #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ | |
| 485 | #define PLLMR0_CPU_DIV_BYPASS 0x00000000 | |
| 486 | #define PLLMR0_CPU_DIV_2 0x00100000 | |
| 487 | #define PLLMR0_CPU_DIV_3 0x00200000 | |
| 488 | #define PLLMR0_CPU_DIV_4 0x00300000 | |
| 489 | ||
| 490 | #define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ | |
| 491 | #define PLLMR0_CPU_PLB_DIV_1 0x00000000 | |
| 492 | #define PLLMR0_CPU_PLB_DIV_2 0x00010000 | |
| 493 | #define PLLMR0_CPU_PLB_DIV_3 0x00020000 | |
| 494 | #define PLLMR0_CPU_PLB_DIV_4 0x00030000 | |
| 495 | ||
| 496 | #define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ | |
| 497 | #define PLLMR0_OPB_PLB_DIV_1 0x00000000 | |
| 498 | #define PLLMR0_OPB_PLB_DIV_2 0x00001000 | |
| 499 | #define PLLMR0_OPB_PLB_DIV_3 0x00002000 | |
| 500 | #define PLLMR0_OPB_PLB_DIV_4 0x00003000 | |
| 501 | ||
| 502 | #define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ | |
| 503 | #define PLLMR0_EXB_PLB_DIV_2 0x00000000 | |
| 504 | #define PLLMR0_EXB_PLB_DIV_3 0x00000100 | |
| 505 | #define PLLMR0_EXB_PLB_DIV_4 0x00000200 | |
| 506 | #define PLLMR0_EXB_PLB_DIV_5 0x00000300 | |
| 507 | ||
| 508 | #define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ | |
| 509 | #define PLLMR0_MAL_PLB_DIV_1 0x00000000 | |
| 510 | #define PLLMR0_MAL_PLB_DIV_2 0x00000010 | |
| 511 | #define PLLMR0_MAL_PLB_DIV_3 0x00000020 | |
| 512 | #define PLLMR0_MAL_PLB_DIV_4 0x00000030 | |
| 513 | ||
| 514 | #define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ | |
| 515 | #define PLLMR0_PCI_PLB_DIV_1 0x00000000 | |
| 516 | #define PLLMR0_PCI_PLB_DIV_2 0x00000001 | |
| 517 | #define PLLMR0_PCI_PLB_DIV_3 0x00000002 | |
| 518 | #define PLLMR0_PCI_PLB_DIV_4 0x00000003 | |
| 519 | ||
| 520 | #define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ | |
| 521 | #define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ | |
| 522 | #define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ | |
| 523 | #define PLLMR1_FBMUL_DIV_16 0x00000000 | |
| 524 | #define PLLMR1_FBMUL_DIV_1 0x00100000 | |
| 525 | #define PLLMR1_FBMUL_DIV_2 0x00200000 | |
| 526 | #define PLLMR1_FBMUL_DIV_3 0x00300000 | |
| 527 | #define PLLMR1_FBMUL_DIV_4 0x00400000 | |
| 528 | #define PLLMR1_FBMUL_DIV_5 0x00500000 | |
| 529 | #define PLLMR1_FBMUL_DIV_6 0x00600000 | |
| 530 | #define PLLMR1_FBMUL_DIV_7 0x00700000 | |
| 531 | #define PLLMR1_FBMUL_DIV_8 0x00800000 | |
| 532 | #define PLLMR1_FBMUL_DIV_9 0x00900000 | |
| 533 | #define PLLMR1_FBMUL_DIV_10 0x00A00000 | |
| 534 | #define PLLMR1_FBMUL_DIV_11 0x00B00000 | |
| 535 | #define PLLMR1_FBMUL_DIV_12 0x00C00000 | |
| 536 | #define PLLMR1_FBMUL_DIV_13 0x00D00000 | |
| 537 | #define PLLMR1_FBMUL_DIV_14 0x00E00000 | |
| 538 | #define PLLMR1_FBMUL_DIV_15 0x00F00000 | |
| 539 | ||
| 540 | #define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ | |
| 541 | #define PLLMR1_FWDVA_DIV_8 0x00000000 | |
| 542 | #define PLLMR1_FWDVA_DIV_7 0x00010000 | |
| 543 | #define PLLMR1_FWDVA_DIV_6 0x00020000 | |
| 544 | #define PLLMR1_FWDVA_DIV_5 0x00030000 | |
| 545 | #define PLLMR1_FWDVA_DIV_4 0x00040000 | |
| 546 | #define PLLMR1_FWDVA_DIV_3 0x00050000 | |
| 547 | #define PLLMR1_FWDVA_DIV_2 0x00060000 | |
| 548 | #define PLLMR1_FWDVA_DIV_1 0x00070000 | |
| 549 | #define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ | |
| 550 | #define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ | |
| 551 | ||
| 552 | /* Defines for CPC0_EPRCSR register */ | |
| 553 | #define CPC0_EPRCSR_E0NFE 0x80000000 | |
| 554 | #define CPC0_EPRCSR_E1NFE 0x40000000 | |
| 555 | #define CPC0_EPRCSR_E1RPP 0x00000080 | |
| 556 | #define CPC0_EPRCSR_E0RPP 0x00000040 | |
| 557 | #define CPC0_EPRCSR_E1ERP 0x00000020 | |
| 558 | #define CPC0_EPRCSR_E0ERP 0x00000010 | |
| 559 | #define CPC0_EPRCSR_E1PCI 0x00000002 | |
| 560 | #define CPC0_EPRCSR_E0PCI 0x00000001 | |
| 561 | ||
| 562 | /* Defines for CPC0_PCI Register */ | |
| 563 | #define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ | |
| 564 | #define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ | |
| 565 | #define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ | |
| 566 | ||
| 567 | /* Defines for CPC0_BOOR Register */ | |
| 568 | #define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ | |
| 569 | ||
| 570 | /* Defines for CPC0_PLLMR1 Register fields */ | |
| 571 | #define PLL_ACTIVE 0x80000000 | |
| 572 | #define CPC0_PLLMR1_SSCS 0x80000000 | |
| 573 | #define PLL_RESET 0x40000000 | |
| 574 | #define CPC0_PLLMR1_PLLR 0x40000000 | |
| 575 | /* Feedback multiplier */ | |
| 576 | #define PLL_FBKDIV 0x00F00000 | |
| 577 | #define CPC0_PLLMR1_FBDV 0x00F00000 | |
| 578 | #define PLL_FBKDIV_16 0x00000000 | |
| 579 | #define PLL_FBKDIV_1 0x00100000 | |
| 580 | #define PLL_FBKDIV_2 0x00200000 | |
| 581 | #define PLL_FBKDIV_3 0x00300000 | |
| 582 | #define PLL_FBKDIV_4 0x00400000 | |
| 583 | #define PLL_FBKDIV_5 0x00500000 | |
| 584 | #define PLL_FBKDIV_6 0x00600000 | |
| 585 | #define PLL_FBKDIV_7 0x00700000 | |
| 586 | #define PLL_FBKDIV_8 0x00800000 | |
| 587 | #define PLL_FBKDIV_9 0x00900000 | |
| 588 | #define PLL_FBKDIV_10 0x00A00000 | |
| 589 | #define PLL_FBKDIV_11 0x00B00000 | |
| 590 | #define PLL_FBKDIV_12 0x00C00000 | |
| 591 | #define PLL_FBKDIV_13 0x00D00000 | |
| 592 | #define PLL_FBKDIV_14 0x00E00000 | |
| 593 | #define PLL_FBKDIV_15 0x00F00000 | |
| 594 | /* Forward A divisor */ | |
| 595 | #define PLL_FWDDIVA 0x00070000 | |
| 596 | #define CPC0_PLLMR1_FWDVA 0x00070000 | |
| 597 | #define PLL_FWDDIVA_8 0x00000000 | |
| 598 | #define PLL_FWDDIVA_7 0x00010000 | |
| 599 | #define PLL_FWDDIVA_6 0x00020000 | |
| 600 | #define PLL_FWDDIVA_5 0x00030000 | |
| 601 | #define PLL_FWDDIVA_4 0x00040000 | |
| 602 | #define PLL_FWDDIVA_3 0x00050000 | |
| 603 | #define PLL_FWDDIVA_2 0x00060000 | |
| 604 | #define PLL_FWDDIVA_1 0x00070000 | |
| 605 | /* Forward B divisor */ | |
| 606 | #define PLL_FWDDIVB 0x00007000 | |
| 607 | #define CPC0_PLLMR1_FWDVB 0x00007000 | |
| 608 | #define PLL_FWDDIVB_8 0x00000000 | |
| 609 | #define PLL_FWDDIVB_7 0x00001000 | |
| 610 | #define PLL_FWDDIVB_6 0x00002000 | |
| 611 | #define PLL_FWDDIVB_5 0x00003000 | |
| 612 | #define PLL_FWDDIVB_4 0x00004000 | |
| 613 | #define PLL_FWDDIVB_3 0x00005000 | |
| 614 | #define PLL_FWDDIVB_2 0x00006000 | |
| 615 | #define PLL_FWDDIVB_1 0x00007000 | |
| 616 | /* PLL tune bits */ | |
| 617 | #define PLL_TUNE_MASK 0x000003FF | |
| 618 | #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ | |
| 619 | #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ | |
| 620 | #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ | |
| 621 | #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ | |
| 622 | #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ | |
| 623 | #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ | |
| 624 | #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ | |
| 625 | ||
| 626 | /* Defines for CPC0_PLLMR0 Register fields */ | |
| 627 | /* CPU divisor */ | |
| 628 | #define PLL_CPUDIV 0x00300000 | |
| 629 | #define CPC0_PLLMR0_CCDV 0x00300000 | |
| 630 | #define PLL_CPUDIV_1 0x00000000 | |
| 631 | #define PLL_CPUDIV_2 0x00100000 | |
| 632 | #define PLL_CPUDIV_3 0x00200000 | |
| 633 | #define PLL_CPUDIV_4 0x00300000 | |
| 634 | /* PLB divisor */ | |
| 635 | #define PLL_PLBDIV 0x00030000 | |
| 636 | #define CPC0_PLLMR0_CBDV 0x00030000 | |
| 637 | #define PLL_PLBDIV_1 0x00000000 | |
| 638 | #define PLL_PLBDIV_2 0x00010000 | |
| 639 | #define PLL_PLBDIV_3 0x00020000 | |
| 640 | #define PLL_PLBDIV_4 0x00030000 | |
| 641 | /* OPB divisor */ | |
| 642 | #define PLL_OPBDIV 0x00003000 | |
| 643 | #define CPC0_PLLMR0_OPDV 0x00003000 | |
| 644 | #define PLL_OPBDIV_1 0x00000000 | |
| 645 | #define PLL_OPBDIV_2 0x00001000 | |
| 646 | #define PLL_OPBDIV_3 0x00002000 | |
| 647 | #define PLL_OPBDIV_4 0x00003000 | |
| 648 | /* EBC divisor */ | |
| 649 | #define PLL_EXTBUSDIV 0x00000300 | |
| 650 | #define CPC0_PLLMR0_EPDV 0x00000300 | |
| 651 | #define PLL_EXTBUSDIV_2 0x00000000 | |
| 652 | #define PLL_EXTBUSDIV_3 0x00000100 | |
| 653 | #define PLL_EXTBUSDIV_4 0x00000200 | |
| 654 | #define PLL_EXTBUSDIV_5 0x00000300 | |
| 655 | /* MAL divisor */ | |
| 656 | #define PLL_MALDIV 0x00000030 | |
| 657 | #define CPC0_PLLMR0_MPDV 0x00000030 | |
| 658 | #define PLL_MALDIV_1 0x00000000 | |
| 659 | #define PLL_MALDIV_2 0x00000010 | |
| 660 | #define PLL_MALDIV_3 0x00000020 | |
| 661 | #define PLL_MALDIV_4 0x00000030 | |
| 662 | /* PCI divisor */ | |
| 663 | #define PLL_PCIDIV 0x00000003 | |
| 664 | #define CPC0_PLLMR0_PPFD 0x00000003 | |
| 665 | #define PLL_PCIDIV_1 0x00000000 | |
| 666 | #define PLL_PCIDIV_2 0x00000001 | |
| 667 | #define PLL_PCIDIV_3 0x00000002 | |
| 668 | #define PLL_PCIDIV_4 0x00000003 | |
| 669 | ||
| 670 | /* | |
| 671 | *------------------------------------------------------------------------------- | |
| 672 | * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, | |
| 673 | * assuming a 33.3MHz input clock to the 405EP. | |
| 674 | *------------------------------------------------------------------------------- | |
| 675 | */ | |
| 676 | #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ | |
| 8bde7f77 WD |
677 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ |
| 678 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
| b867d705 | 679 | #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ |
| 8bde7f77 WD |
680 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ |
| 681 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| b867d705 SR |
682 | |
| 683 | #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ | |
| 8bde7f77 WD |
684 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ |
| 685 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
| b867d705 | 686 | #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ |
| 8bde7f77 WD |
687 | PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ |
| 688 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| b867d705 | 689 | #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
| 8bde7f77 WD |
690 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ |
| 691 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
| b867d705 | 692 | #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ |
| 8bde7f77 WD |
693 | PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ |
| 694 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| b867d705 | 695 | #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
| 8bde7f77 WD |
696 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ |
| 697 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
| b867d705 | 698 | #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ |
| 8bde7f77 WD |
699 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ |
| 700 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| 44acc8d3 | 701 | #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ |
| efe2a4d5 WD |
702 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ |
| 703 | PLL_MALDIV_1 | PLL_PCIDIV_2) | |
| 44acc8d3 | 704 | #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ |
| efe2a4d5 WD |
705 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ |
| 706 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| 779e9751 SR |
707 | #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ |
| 708 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ | |
| 709 | PLL_MALDIV_1 | PLL_PCIDIV_3) | |
| 710 | #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ | |
| 711 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ | |
| 712 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) | |
| 713 | #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ | |
| 714 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ | |
| 715 | PLL_MALDIV_1 | PLL_PCIDIV_1) | |
| 716 | #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ | |
| 717 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ | |
| 718 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) | |
| b867d705 SR |
719 | |
| 720 | /* | |
| 721 | * PLL Voltage Controlled Oscillator (VCO) definitions | |
| 722 | * Maximum and minimum values (in MHz) for correct PLL operation. | |
| 723 | */ | |
| 724 | #define VCO_MIN 500 | |
| 725 | #define VCO_MAX 1000 | |
| e01bd218 | 726 | #elif defined(CONFIG_405EZ) |
| e01bd218 SR |
727 | #define sdrnand0 0x4000 |
| 728 | #define sdrultra0 0x4040 | |
| 729 | #define sdrultra1 0x4050 | |
| 730 | #define sdricintstat 0x4510 | |
| 731 | ||
| 732 | #define SDR_NAND0_NDEN 0x80000000 | |
| c440bfe6 SR |
733 | #define SDR_NAND0_NDBTEN 0x40000000 |
| 734 | #define SDR_NAND0_NDBADR_MASK 0x30000000 | |
| 735 | #define SDR_NAND0_NDBPG_MASK 0x0f000000 | |
| 736 | #define SDR_NAND0_NDAREN 0x00800000 | |
| 737 | #define SDR_NAND0_NDRBEN 0x00400000 | |
| e01bd218 SR |
738 | |
| 739 | #define SDR_ULTRA0_NDGPIOBP 0x80000000 | |
| 740 | #define SDR_ULTRA0_CSN_MASK 0x78000000 | |
| 741 | #define SDR_ULTRA0_CSNSEL0 0x40000000 | |
| 742 | #define SDR_ULTRA0_CSNSEL1 0x20000000 | |
| 743 | #define SDR_ULTRA0_CSNSEL2 0x10000000 | |
| 744 | #define SDR_ULTRA0_CSNSEL3 0x08000000 | |
| c440bfe6 SR |
745 | #define SDR_ULTRA0_EBCRDYEN 0x04000000 |
| 746 | #define SDR_ULTRA0_SPISSINEN 0x02000000 | |
| 747 | #define SDR_ULTRA0_NFSRSTEN 0x01000000 | |
| e01bd218 SR |
748 | |
| 749 | #define SDR_ULTRA1_LEDNENABLE 0x40000000 | |
| 750 | ||
| 751 | #define SDR_ICRX_STAT 0x80000000 | |
| 752 | #define SDR_ICTX0_STAT 0x40000000 | |
| 753 | #define SDR_ICTX1_STAT 0x20000000 | |
| 754 | ||
| 90e6f41c SR |
755 | #define SDR_PINSTP 0x40 |
| 756 | ||
| e01bd218 SR |
757 | /****************************************************************************** |
| 758 | * Control | |
| 759 | ******************************************************************************/ | |
| e01bd218 SR |
760 | /* CPR Registers */ |
| 761 | #define cprclkupd 0x020 /* CPR_CLKUPD */ | |
| 762 | #define cprpllc 0x040 /* CPR_PLLC */ | |
| 763 | #define cprplld 0x060 /* CPR_PLLD */ | |
| 764 | #define cprprimad 0x080 /* CPR_PRIMAD */ | |
| 765 | #define cprperd0 0x0e0 /* CPR_PERD0 */ | |
| 766 | #define cprperd1 0x0e1 /* CPR_PERD1 */ | |
| 767 | #define cprperc0 0x180 /* CPR_PERC0 */ | |
| 768 | #define cprmisc0 0x181 /* CPR_MISC0 */ | |
| 769 | #define cprmisc1 0x182 /* CPR_MISC1 */ | |
| 770 | ||
| e01bd218 SR |
771 | #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ |
| 772 | #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ | |
| 773 | #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ | |
| 774 | ||
| 273db7e1 SR |
775 | #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ |
| 776 | ||
| e01bd218 SR |
777 | #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ |
| 778 | #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ | |
| 779 | #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ | |
| 780 | ||
| 781 | #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ | |
| 782 | #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ | |
| 783 | #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ | |
| 784 | #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ | |
| 785 | ||
| 786 | #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ | |
| 787 | #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ | |
| 788 | #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ | |
| 789 | #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ | |
| 790 | ||
| b867d705 | 791 | #else /* #ifdef CONFIG_405EP */ |
| 0442ed86 WD |
792 | /****************************************************************************** |
| 793 | * Control | |
| 794 | ******************************************************************************/ | |
| 795 | #define CNTRL_DCR_BASE 0x0b0 | |
| 796 | #define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ | |
| 797 | #define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ | |
| 798 | #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ | |
| 799 | #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ | |
| 1636d1c8 | 800 | #define strap (CNTRL_DCR_BASE+0x4) /* strap register */ |
| b867d705 | 801 | |
| 8cc10d06 NG |
802 | #define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ |
| 803 | #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ | |
| 804 | #define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ | |
| 805 | ||
| 806 | /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ | |
| 807 | #define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ | |
| 808 | #define CPC0_ECR (0xaa) /* edge conditioner register */ | |
| 809 | ||
| b867d705 | 810 | #define ecr (0xaa) /* edge conditioner register (405gpr) */ |
| 0442ed86 WD |
811 | |
| 812 | /* Bit definitions */ | |
| 813 | #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ | |
| 814 | #define PLLMR_FWD_DIV_BYPASS 0xE0000000 | |
| 815 | #define PLLMR_FWD_DIV_3 0xA0000000 | |
| 816 | #define PLLMR_FWD_DIV_4 0x80000000 | |
| 817 | #define PLLMR_FWD_DIV_6 0x40000000 | |
| 818 | ||
| 819 | #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ | |
| 820 | #define PLLMR_FB_DIV_1 0x02000000 | |
| 821 | #define PLLMR_FB_DIV_2 0x04000000 | |
| 822 | #define PLLMR_FB_DIV_3 0x06000000 | |
| 823 | #define PLLMR_FB_DIV_4 0x08000000 | |
| 824 | ||
| 825 | #define PLLMR_TUNING_MASK 0x01F80000 | |
| 826 | ||
| 827 | #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ | |
| 828 | #define PLLMR_CPU_PLB_DIV_1 0x00000000 | |
| 829 | #define PLLMR_CPU_PLB_DIV_2 0x00020000 | |
| 830 | #define PLLMR_CPU_PLB_DIV_3 0x00040000 | |
| 831 | #define PLLMR_CPU_PLB_DIV_4 0x00060000 | |
| 832 | ||
| 833 | #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ | |
| 834 | #define PLLMR_OPB_PLB_DIV_1 0x00000000 | |
| 835 | #define PLLMR_OPB_PLB_DIV_2 0x00008000 | |
| 836 | #define PLLMR_OPB_PLB_DIV_3 0x00010000 | |
| 837 | #define PLLMR_OPB_PLB_DIV_4 0x00018000 | |
| 838 | ||
| 839 | #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ | |
| 840 | #define PLLMR_PCI_PLB_DIV_1 0x00000000 | |
| 841 | #define PLLMR_PCI_PLB_DIV_2 0x00002000 | |
| 842 | #define PLLMR_PCI_PLB_DIV_3 0x00004000 | |
| 843 | #define PLLMR_PCI_PLB_DIV_4 0x00006000 | |
| 844 | ||
| 845 | #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ | |
| 846 | #define PLLMR_EXB_PLB_DIV_2 0x00000000 | |
| 847 | #define PLLMR_EXB_PLB_DIV_3 0x00000800 | |
| 848 | #define PLLMR_EXB_PLB_DIV_4 0x00001000 | |
| 849 | #define PLLMR_EXB_PLB_DIV_5 0x00001800 | |
| 850 | ||
| 851 | /* definitions for PPC405GPr (new mode strapping) */ | |
| 852 | #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ | |
| 853 | ||
| 854 | #define PSR_PLL_FWD_MASK 0xC0000000 | |
| 855 | #define PSR_PLL_FDBACK_MASK 0x30000000 | |
| 856 | #define PSR_PLL_TUNING_MASK 0x0E000000 | |
| 857 | #define PSR_PLB_CPU_MASK 0x01800000 | |
| 858 | #define PSR_OPB_PLB_MASK 0x00600000 | |
| 859 | #define PSR_PCI_PLB_MASK 0x00180000 | |
| 860 | #define PSR_EB_PLB_MASK 0x00060000 | |
| 861 | #define PSR_ROM_WIDTH_MASK 0x00018000 | |
| 862 | #define PSR_ROM_LOC 0x00004000 | |
| 863 | #define PSR_PCI_ASYNC_EN 0x00001000 | |
| 864 | #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ | |
| 865 | #define PSR_PCI_ARBIT_EN 0x00000400 | |
| 866 | #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ | |
| 867 | ||
| 44acc8d3 | 868 | #ifndef CONFIG_IOP480 |
| 0442ed86 WD |
869 | /* |
| 870 | * PLL Voltage Controlled Oscillator (VCO) definitions | |
| 871 | * Maximum and minimum values (in MHz) for correct PLL operation. | |
| 872 | */ | |
| 873 | #define VCO_MIN 400 | |
| 874 | #define VCO_MAX 800 | |
| 44acc8d3 | 875 | #endif /* #ifndef CONFIG_IOP480 */ |
| b867d705 | 876 | #endif /* #ifdef CONFIG_405EP */ |
| 0442ed86 WD |
877 | |
| 878 | /****************************************************************************** | |
| 879 | * Memory Access Layer | |
| 880 | ******************************************************************************/ | |
| e01bd218 SR |
881 | #if defined(CONFIG_405EZ) |
| 882 | #define MAL_DCR_BASE 0x380 | |
| 883 | #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ | |
| 884 | #define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ | |
| 885 | #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ | |
| 886 | #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ | |
| 887 | #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ | |
| 888 | #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ | |
| 889 | #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ | |
| 890 | #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ | |
| 891 | /* 0x08-0x0F Reserved */ | |
| 892 | #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ | |
| 893 | #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ | |
| 894 | #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ | |
| 895 | #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ | |
| 896 | /* 0x14-0x1F Reserved */ | |
| 897 | #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ | |
| 898 | #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ | |
| 899 | #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ | |
| 900 | #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ | |
| 901 | #define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ | |
| 902 | #define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ | |
| 903 | #define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ | |
| 904 | #define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ | |
| 905 | #define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ | |
| 906 | #define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ | |
| 907 | #define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ | |
| 908 | #define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ | |
| 909 | #define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ | |
| 910 | #define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ | |
| 911 | #define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ | |
| 912 | #define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ | |
| 913 | #define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ | |
| 914 | #define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ | |
| 915 | #define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ | |
| 916 | #define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ | |
| 917 | #define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ | |
| 918 | #define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ | |
| 919 | #define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ | |
| 920 | #define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ | |
| 921 | #define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ | |
| 922 | #define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ | |
| 923 | #define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ | |
| 924 | #define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ | |
| 925 | #define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ | |
| 926 | #define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ | |
| 927 | #define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ | |
| 928 | #define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ | |
| 929 | #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ | |
| 930 | #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ | |
| 931 | #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ | |
| 932 | #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ | |
| 933 | #define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ | |
| 934 | #define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ | |
| 935 | #define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ | |
| 936 | #define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ | |
| 937 | #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ | |
| 938 | #define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ | |
| 939 | #define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ | |
| 940 | #define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ | |
| 941 | #define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ | |
| 942 | #define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ | |
| 943 | #define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ | |
| 944 | #define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ | |
| 945 | #define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ | |
| 946 | #define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ | |
| 947 | #define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ | |
| 948 | #define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ | |
| 949 | #define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ | |
| 950 | #define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ | |
| 951 | #define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ | |
| 952 | #define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ | |
| 953 | #define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ | |
| 954 | #define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ | |
| 955 | #define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ | |
| 956 | #define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ | |
| 957 | #define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ | |
| 958 | #define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ | |
| 959 | #define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ | |
| 960 | #define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ | |
| 961 | #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ | |
| 962 | #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ | |
| 963 | #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ | |
| 964 | #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ | |
| 965 | #define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ | |
| 966 | #define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ | |
| 967 | #define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ | |
| 968 | #define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ | |
| 969 | #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ | |
| 970 | #define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ | |
| 971 | #define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ | |
| 972 | #define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ | |
| 973 | #define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ | |
| 974 | #define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ | |
| 975 | #define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ | |
| 976 | #define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ | |
| 977 | #define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ | |
| 978 | #define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ | |
| 979 | #define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ | |
| 980 | #define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ | |
| 981 | #define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ | |
| 982 | #define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ | |
| 983 | #define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ | |
| 984 | #define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ | |
| 985 | #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ | |
| 986 | #define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ | |
| 987 | #define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ | |
| 988 | #define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ | |
| 989 | #define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ | |
| 990 | #define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ | |
| 991 | #define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ | |
| 992 | #define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ | |
| 993 | ||
| 994 | #else /* !defined(CONFIG_405EZ) */ | |
| 995 | ||
| 0442ed86 WD |
996 | #define MAL_DCR_BASE 0x180 |
| 997 | #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ | |
| 998 | #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ | |
| 999 | #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ | |
| 1000 | #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ | |
| 1001 | #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ | |
| 1002 | #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ | |
| 1003 | #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ | |
| 1004 | #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ | |
| 1005 | #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ | |
| 1006 | #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ | |
| 1007 | #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ | |
| 1008 | #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ | |
| 1009 | #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ | |
| 1010 | #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ | |
| cea655a2 | 1011 | #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ |
| 0442ed86 | 1012 | #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ |
| cea655a2 | 1013 | #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ |
| 0442ed86 | 1014 | #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ |
| cea655a2 | 1015 | #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ |
| e01bd218 | 1016 | #endif /* defined(CONFIG_405EZ) */ |
| 0442ed86 WD |
1017 | |
| 1018 | /*----------------------------------------------------------------------------- | |
| 1019 | | IIC Register Offsets | |
| 1020 | '----------------------------------------------------------------------------*/ | |
| 1021 | #define IICMDBUF 0x00 | |
| 1022 | #define IICSDBUF 0x02 | |
| 1023 | #define IICLMADR 0x04 | |
| 1024 | #define IICHMADR 0x05 | |
| 1025 | #define IICCNTL 0x06 | |
| 1026 | #define IICMDCNTL 0x07 | |
| 1027 | #define IICSTS 0x08 | |
| 1028 | #define IICEXTSTS 0x09 | |
| 1029 | #define IICLSADR 0x0A | |
| 1030 | #define IICHSADR 0x0B | |
| 1031 | #define IICCLKDIV 0x0C | |
| 1032 | #define IICINTRMSK 0x0D | |
| 1033 | #define IICXFRCNT 0x0E | |
| 1034 | #define IICXTCNTLSS 0x0F | |
| 1035 | #define IICDIRECTCNTL 0x10 | |
| 1036 | ||
| 1037 | /*----------------------------------------------------------------------------- | |
| 1038 | | UART Register Offsets | |
| 1039 | '----------------------------------------------------------------------------*/ | |
| 1040 | #define DATA_REG 0x00 | |
| 1636d1c8 WD |
1041 | #define DL_LSB 0x00 |
| 1042 | #define DL_MSB 0x01 | |
| 0442ed86 WD |
1043 | #define INT_ENABLE 0x01 |
| 1044 | #define FIFO_CONTROL 0x02 | |
| 1045 | #define LINE_CONTROL 0x03 | |
| 1046 | #define MODEM_CONTROL 0x04 | |
| 1636d1c8 | 1047 | #define LINE_STATUS 0x05 |
| 0442ed86 WD |
1048 | #define MODEM_STATUS 0x06 |
| 1049 | #define SCRATCH 0x07 | |
| 1050 | ||
| 1051 | /****************************************************************************** | |
| 1052 | * On Chip Memory | |
| 1053 | ******************************************************************************/ | |
| e01bd218 SR |
1054 | #if defined(CONFIG_405EZ) |
| 1055 | #define OCM_DCR_BASE 0x020 | |
| 1056 | #define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ | |
| 1057 | #define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ | |
| 1058 | #define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ | |
| 1059 | #define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ | |
| 1060 | #define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ | |
| 1061 | #define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ | |
| 1062 | #define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ | |
| 1063 | #define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ | |
| 1064 | #define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ | |
| 1065 | #define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ | |
| 1066 | #define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ | |
| 1067 | #define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ | |
| 1068 | #define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ | |
| 1069 | #define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ | |
| 1070 | #define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ | |
| 1071 | #else | |
| 0442ed86 WD |
1072 | #define OCM_DCR_BASE 0x018 |
| 1073 | #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ | |
| 1074 | #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ | |
| 1075 | #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ | |
| 1076 | #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ | |
| e01bd218 | 1077 | #endif /* CONFIG_405EZ */ |
| 0442ed86 | 1078 | |
| b867d705 SR |
1079 | /****************************************************************************** |
| 1080 | * GPIO macro register defines | |
| 1081 | ******************************************************************************/ | |
| e01bd218 SR |
1082 | #if defined(CONFIG_405EZ) |
| 1083 | /* Only the 405EZ has 2 GPIOs */ | |
| 1084 | #define GPIO_BASE 0xEF600700 | |
| 1085 | #define GPIO0_OR (GPIO_BASE+0x0) | |
| 1086 | #define GPIO0_TCR (GPIO_BASE+0x4) | |
| 1087 | #define GPIO0_OSRL (GPIO_BASE+0x8) | |
| 1088 | #define GPIO0_OSRH (GPIO_BASE+0xC) | |
| 1089 | #define GPIO0_TSRL (GPIO_BASE+0x10) | |
| 1090 | #define GPIO0_TSRH (GPIO_BASE+0x14) | |
| 1091 | #define GPIO0_ODR (GPIO_BASE+0x18) | |
| 1092 | #define GPIO0_IR (GPIO_BASE+0x1C) | |
| 1093 | #define GPIO0_RR1 (GPIO_BASE+0x20) | |
| 1094 | #define GPIO0_RR2 (GPIO_BASE+0x24) | |
| 1095 | #define GPIO0_RR3 (GPIO_BASE+0x28) | |
| 1096 | #define GPIO0_ISR1L (GPIO_BASE+0x30) | |
| 1097 | #define GPIO0_ISR1H (GPIO_BASE+0x34) | |
| 1098 | #define GPIO0_ISR2L (GPIO_BASE+0x38) | |
| 1099 | #define GPIO0_ISR2H (GPIO_BASE+0x3C) | |
| 1100 | #define GPIO0_ISR3L (GPIO_BASE+0x40) | |
| 1101 | #define GPIO0_ISR3H (GPIO_BASE+0x44) | |
| 1102 | ||
| 1103 | #define GPIO1_BASE 0xEF600800 | |
| 1104 | #define GPIO1_OR (GPIO1_BASE+0x0) | |
| 1105 | #define GPIO1_TCR (GPIO1_BASE+0x4) | |
| 1106 | #define GPIO1_OSRL (GPIO1_BASE+0x8) | |
| 1107 | #define GPIO1_OSRH (GPIO1_BASE+0xC) | |
| 1108 | #define GPIO1_TSRL (GPIO1_BASE+0x10) | |
| 1109 | #define GPIO1_TSRH (GPIO1_BASE+0x14) | |
| 1110 | #define GPIO1_ODR (GPIO1_BASE+0x18) | |
| 1111 | #define GPIO1_IR (GPIO1_BASE+0x1C) | |
| 1112 | #define GPIO1_RR1 (GPIO1_BASE+0x20) | |
| 1113 | #define GPIO1_RR2 (GPIO1_BASE+0x24) | |
| 1114 | #define GPIO1_RR3 (GPIO1_BASE+0x28) | |
| 1115 | #define GPIO1_ISR1L (GPIO1_BASE+0x30) | |
| 1116 | #define GPIO1_ISR1H (GPIO1_BASE+0x34) | |
| 1117 | #define GPIO1_ISR2L (GPIO1_BASE+0x38) | |
| 1118 | #define GPIO1_ISR2H (GPIO1_BASE+0x3C) | |
| 1119 | #define GPIO1_ISR3L (GPIO1_BASE+0x40) | |
| 1120 | #define GPIO1_ISR3H (GPIO1_BASE+0x44) | |
| 1121 | ||
| dbbd1257 SR |
1122 | #elif defined(CONFIG_405EX) |
| 1123 | #define GPIO_BASE 0xEF600800 | |
| 1124 | #define GPIO0_OR (GPIO_BASE+0x0) | |
| 1125 | #define GPIO0_TCR (GPIO_BASE+0x4) | |
| 1126 | #define GPIO0_OSRL (GPIO_BASE+0x8) | |
| 1127 | #define GPIO0_OSRH (GPIO_BASE+0xC) | |
| 1128 | #define GPIO0_TSRL (GPIO_BASE+0x10) | |
| 1129 | #define GPIO0_TSRH (GPIO_BASE+0x14) | |
| 1130 | #define GPIO0_ODR (GPIO_BASE+0x18) | |
| 1131 | #define GPIO0_IR (GPIO_BASE+0x1C) | |
| 1132 | #define GPIO0_RR1 (GPIO_BASE+0x20) | |
| 1133 | #define GPIO0_RR2 (GPIO_BASE+0x24) | |
| 1134 | #define GPIO0_ISR1L (GPIO_BASE+0x30) | |
| 1135 | #define GPIO0_ISR1H (GPIO_BASE+0x34) | |
| 1136 | #define GPIO0_ISR2L (GPIO_BASE+0x38) | |
| 1137 | #define GPIO0_ISR2H (GPIO_BASE+0x3C) | |
| 1138 | #define GPIO0_ISR3L (GPIO_BASE+0x40) | |
| 1139 | #define GPIO0_ISR3H (GPIO_BASE+0x44) | |
| 1140 | ||
| e01bd218 SR |
1141 | #else /* !405EZ */ |
| 1142 | ||
| b867d705 SR |
1143 | #define GPIO_BASE 0xEF600700 |
| 1144 | #define GPIO0_OR (GPIO_BASE+0x0) | |
| 1145 | #define GPIO0_TCR (GPIO_BASE+0x4) | |
| 1146 | #define GPIO0_OSRH (GPIO_BASE+0x8) | |
| 1147 | #define GPIO0_OSRL (GPIO_BASE+0xC) | |
| 1148 | #define GPIO0_TSRH (GPIO_BASE+0x10) | |
| 1149 | #define GPIO0_TSRL (GPIO_BASE+0x14) | |
| 1150 | #define GPIO0_ODR (GPIO_BASE+0x18) | |
| 1151 | #define GPIO0_IR (GPIO_BASE+0x1C) | |
| 1152 | #define GPIO0_RR1 (GPIO_BASE+0x20) | |
| 1153 | #define GPIO0_RR2 (GPIO_BASE+0x24) | |
| 1154 | #define GPIO0_ISR1H (GPIO_BASE+0x30) | |
| 1155 | #define GPIO0_ISR1L (GPIO_BASE+0x34) | |
| 1156 | #define GPIO0_ISR2H (GPIO_BASE+0x38) | |
| 1157 | #define GPIO0_ISR2L (GPIO_BASE+0x3C) | |
| 1158 | ||
| e01bd218 | 1159 | #endif /* CONFIG_405EZ */ |
| 0442ed86 | 1160 | |
| aee747f1 SR |
1161 | #define GPIO0_BASE GPIO_BASE |
| 1162 | ||
| dbbd1257 SR |
1163 | #if defined(CONFIG_405EX) |
| 1164 | #define SDR0_SRST 0x0200 | |
| 1165 | ||
| 1166 | #define SDRAM_BESR0 0x00 | |
| 1167 | #define SDRAM_BEARL 0x02 | |
| 1168 | #define SDRAM_BEARU 0x03 | |
| 1169 | #define SDRAM_WMIRQ 0x06 /**/ | |
| 1170 | #define SDRAM_PLBOPT 0x08 /**/ | |
| 1171 | #define SDRAM_PUABA 0x09 /**/ | |
| 1172 | #define SDRAM_MCSTAT 0x1F /* memory controller status */ | |
| 1173 | #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ | |
| 1174 | #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ | |
| 1175 | #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ | |
| 1176 | #define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ | |
| 1177 | #define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ | |
| 1178 | #define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ | |
| 1179 | #define SDRAM_CODT 0x26 /* on die termination for controller */ | |
| 1180 | #define SDRAM_VVPR 0x27 /* variable VRef programmming */ | |
| 1181 | #define SDRAM_OPARS 0x28 /* on chip driver control setup */ | |
| 1182 | #define SDRAM_OPART 0x29 /* on chip driver control trigger */ | |
| 1183 | #define SDRAM_RTR 0x30 /* refresh timer */ | |
| 1184 | #define SDRAM_PMIT 0x34 /* power management idle timer */ | |
| 1185 | #define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ | |
| 1186 | #define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ | |
| 1187 | #define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */ | |
| 1188 | #define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */ | |
| 1189 | #define SDRAM_INITPLR0 0x50 /* manual initialization control */ | |
| 1190 | #define SDRAM_INITPLR1 0x51 /* manual initialization control */ | |
| 1191 | #define SDRAM_INITPLR2 0x52 /* manual initialization control */ | |
| 1192 | #define SDRAM_INITPLR3 0x53 /* manual initialization control */ | |
| 1193 | #define SDRAM_INITPLR4 0x54 /* manual initialization control */ | |
| 1194 | #define SDRAM_INITPLR5 0x55 /* manual initialization control */ | |
| 1195 | #define SDRAM_INITPLR6 0x56 /* manual initialization control */ | |
| 1196 | #define SDRAM_INITPLR7 0x57 /* manual initialization control */ | |
| 1197 | #define SDRAM_INITPLR8 0x58 /* manual initialization control */ | |
| 1198 | #define SDRAM_INITPLR9 0x59 /* manual initialization control */ | |
| 1199 | #define SDRAM_INITPLR10 0x5a /* manual initialization control */ | |
| 1200 | #define SDRAM_INITPLR11 0x5b /* manual initialization control */ | |
| 1201 | #define SDRAM_INITPLR12 0x5c /* manual initialization control */ | |
| 1202 | #define SDRAM_INITPLR13 0x5d /* manual initialization control */ | |
| 1203 | #define SDRAM_INITPLR14 0x5e /* manual initialization control */ | |
| 1204 | #define SDRAM_INITPLR15 0x5f /* manual initialization control */ | |
| 1205 | #define SDRAM_RQDC 0x70 /* read DQS delay control */ | |
| 1206 | #define SDRAM_RFDC 0x74 /* read feedback delay control */ | |
| 1207 | #define SDRAM_RDCC 0x78 /* read data capture control */ | |
| 1208 | #define SDRAM_DLCR 0x7A /* delay line calibration */ | |
| 1209 | #define SDRAM_CLKTR 0x80 /* DDR clock timing */ | |
| 1210 | #define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ | |
| 1211 | #define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ | |
| 1212 | #define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ | |
| 1213 | #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ | |
| 1214 | #define SDRAM_MMODE 0x88 /* memory mode */ | |
| 1215 | #define SDRAM_MEMODE 0x89 /* memory extended mode */ | |
| 1216 | #define SDRAM_ECCCR 0x98 /* ECC error status */ | |
| 1217 | #define SDRAM_RID 0xF8 /* revision ID */ | |
| 1218 | ||
| 1219 | /*-----------------------------------------------------------------------------+ | |
| 1220 | | Memory Bank 0-7 configuration | |
| 1221 | +-----------------------------------------------------------------------------*/ | |
| 1222 | #define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */ | |
| 1223 | #define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */ | |
| 1224 | #define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */ | |
| 1225 | #define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */ | |
| 1226 | #define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */ | |
| 1227 | #define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */ | |
| 1228 | #define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */ | |
| 1229 | #define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */ | |
| 1230 | #define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */ | |
| 1231 | #define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */ | |
| 1232 | #define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */ | |
| 1233 | #define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */ | |
| 1234 | ||
| 1235 | /*-----------------------------------------------------------------------------+ | |
| 1236 | | Memory Controller Status | |
| 1237 | +-----------------------------------------------------------------------------*/ | |
| 1238 | #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ | |
| 1239 | #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ | |
| 1240 | #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ | |
| 1241 | #define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ | |
| 1242 | #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ | |
| 1243 | #define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ | |
| 1244 | ||
| 1245 | /*-----------------------------------------------------------------------------+ | |
| 1246 | | Memory Controller Options 1 | |
| 1247 | +-----------------------------------------------------------------------------*/ | |
| 1248 | #define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */ | |
| 1249 | #define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ | |
| 1250 | #define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ | |
| 1251 | #define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ | |
| 1252 | #define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ | |
| 1253 | #define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) | |
| 1254 | #define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ | |
| 1255 | #define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ | |
| 1256 | #define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ | |
| 1257 | #define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ | |
| 1258 | #define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ | |
| 1259 | #define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ | |
| 1260 | #define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ | |
| 1261 | #define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ | |
| 1262 | #define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ | |
| 1263 | #define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ | |
| 1264 | #define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ | |
| 1265 | #define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ | |
| 1266 | #define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ | |
| 1267 | #define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ | |
| 1268 | #define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ | |
| 1269 | #define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ | |
| 1270 | #define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ | |
| 1271 | #define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ | |
| 1272 | #define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ | |
| 1273 | #define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ | |
| 1274 | #define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ | |
| 1275 | #define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ | |
| 1276 | #define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ | |
| 1277 | #define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ | |
| 1278 | #define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ | |
| 1279 | #define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ | |
| 1280 | #define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ | |
| 1281 | #define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ | |
| 1282 | #define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ | |
| 1283 | ||
| 1284 | /*-----------------------------------------------------------------------------+ | |
| 1285 | | Memory Controller Options 2 | |
| 1286 | +-----------------------------------------------------------------------------*/ | |
| 1287 | #define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ | |
| 1288 | #define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ | |
| 1289 | #define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ | |
| 1290 | #define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ | |
| 1291 | #define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ | |
| 1292 | #define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ | |
| 1293 | #define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ | |
| 1294 | #define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ | |
| 1295 | #define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ | |
| 1296 | #define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ | |
| 1297 | #define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ | |
| 1298 | #define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ | |
| 1299 | #define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ | |
| 1300 | #define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ | |
| 1301 | #define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ | |
| 1302 | #define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ | |
| 1303 | #define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ | |
| 1304 | #define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ | |
| 1305 | ||
| 1306 | /*-----------------------------------------------------------------------------+ | |
| 1307 | | SDRAM Refresh Timer Register | |
| 1308 | +-----------------------------------------------------------------------------*/ | |
| 1309 | #define SDRAM_RTR_RINT_MASK 0xFFF80000 | |
| 1310 | #define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) | |
| 1311 | #define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) | |
| 1312 | ||
| 1313 | /*-----------------------------------------------------------------------------+ | |
| 1314 | | SDRAM Read DQS Delay Control Register | |
| 1315 | +-----------------------------------------------------------------------------*/ | |
| 1316 | #define SDRAM_RQDC_RQDE_MASK 0x80000000 | |
| 1317 | #define SDRAM_RQDC_RQDE_DISABLE 0x00000000 | |
| 1318 | #define SDRAM_RQDC_RQDE_ENABLE 0x80000000 | |
| 1319 | #define SDRAM_RQDC_RQFD_MASK 0x000001FF | |
| 1320 | #define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) | |
| 1321 | ||
| 1322 | #define SDRAM_RQDC_RQFD_MAX 0xFF | |
| 1323 | ||
| 1324 | /*-----------------------------------------------------------------------------+ | |
| 1325 | | SDRAM Read Data Capture Control Register | |
| 1326 | +-----------------------------------------------------------------------------*/ | |
| 1327 | #define SDRAM_RDCC_RDSS_MASK 0xC0000000 | |
| 1328 | #define SDRAM_RDCC_RDSS_T1 0x00000000 | |
| 1329 | #define SDRAM_RDCC_RDSS_T2 0x40000000 | |
| 1330 | #define SDRAM_RDCC_RDSS_T3 0x80000000 | |
| 1331 | #define SDRAM_RDCC_RDSS_T4 0xC0000000 | |
| 1332 | #define SDRAM_RDCC_RSAE_MASK 0x00000001 | |
| 1333 | #define SDRAM_RDCC_RSAE_DISABLE 0x00000001 | |
| 1334 | #define SDRAM_RDCC_RSAE_ENABLE 0x00000000 | |
| 1335 | ||
| 1336 | /*-----------------------------------------------------------------------------+ | |
| 1337 | | SDRAM Read Feedback Delay Control Register | |
| 1338 | +-----------------------------------------------------------------------------*/ | |
| 1339 | #define SDRAM_RFDC_ARSE_MASK 0x80000000 | |
| 1340 | #define SDRAM_RFDC_ARSE_DISABLE 0x80000000 | |
| 1341 | #define SDRAM_RFDC_ARSE_ENABLE 0x00000000 | |
| 1342 | #define SDRAM_RFDC_RFOS_MASK 0x007F0000 | |
| 1343 | #define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) | |
| 1344 | #define SDRAM_RFDC_RFFD_MASK 0x000003FF | |
| 1345 | #define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) | |
| 1346 | ||
| 1347 | #define SDRAM_RFDC_RFFD_MAX 0x4FF | |
| 1348 | ||
| 1349 | /*-----------------------------------------------------------------------------+ | |
| 1350 | | SDRAM Delay Line Calibration Register | |
| 1351 | +-----------------------------------------------------------------------------*/ | |
| 1352 | #define SDRAM_DLCR_DCLM_MASK 0x80000000 | |
| 1353 | #define SDRAM_DLCR_DCLM_MANUEL 0x80000000 | |
| 1354 | #define SDRAM_DLCR_DCLM_AUTO 0x00000000 | |
| 1355 | #define SDRAM_DLCR_DLCR_MASK 0x08000000 | |
| 1356 | #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 | |
| 1357 | #define SDRAM_DLCR_DLCR_IDLE 0x00000000 | |
| 1358 | #define SDRAM_DLCR_DLCS_MASK 0x07000000 | |
| 1359 | #define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 | |
| 1360 | #define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 | |
| 1361 | #define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 | |
| 1362 | #define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 | |
| 1363 | #define SDRAM_DLCR_DLCS_ERROR 0x04000000 | |
| 1364 | #define SDRAM_DLCR_DLCV_MASK 0x000001FF | |
| 1365 | #define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) | |
| 1366 | #define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) | |
| 1367 | ||
| 1368 | /*-----------------------------------------------------------------------------+ | |
| 1369 | | SDRAM Controller On Die Termination Register | |
| 1370 | +-----------------------------------------------------------------------------*/ | |
| 1371 | #define SDRAM_CODT_ODT_ON 0x80000000 | |
| 1372 | #define SDRAM_CODT_ODT_OFF 0x00000000 | |
| 1373 | #define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 | |
| 1374 | #define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 | |
| 1375 | #define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 | |
| 1376 | #define SDRAM_CODT_DQS_MASK 0x00000010 | |
| 1377 | #define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 | |
| 1378 | #define SDRAM_CODT_DQS_SINGLE_END 0x00000010 | |
| 1379 | #define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 | |
| 1380 | #define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 | |
| 1381 | #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 | |
| 1382 | #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 | |
| 1383 | #define SDRAM_CODT_IO_HIZ 0x00000000 | |
| 1384 | #define SDRAM_CODT_IO_NMODE 0x00000001 | |
| 1385 | ||
| 1386 | /*-----------------------------------------------------------------------------+ | |
| 1387 | | SDRAM Mode Register | |
| 1388 | +-----------------------------------------------------------------------------*/ | |
| 1389 | #define SDRAM_MMODE_WR_MASK 0x00000E00 | |
| 1390 | #define SDRAM_MMODE_WR_DDR1 0x00000000 | |
| 1391 | #define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 | |
| 1392 | #define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 | |
| 1393 | #define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 | |
| 1394 | #define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 | |
| 1395 | #define SDRAM_MMODE_DCL_MASK 0x00000070 | |
| 1396 | #define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 | |
| 1397 | #define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 | |
| 1398 | #define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 | |
| 1399 | #define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 | |
| 1400 | #define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 | |
| 1401 | #define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 | |
| 1402 | #define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 | |
| 1403 | #define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 | |
| 1404 | #define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 | |
| 1405 | ||
| 1406 | /*-----------------------------------------------------------------------------+ | |
| 1407 | | SDRAM Extended Mode Register | |
| 1408 | +-----------------------------------------------------------------------------*/ | |
| 1409 | #define SDRAM_MEMODE_DIC_MASK 0x00000002 | |
| 1410 | #define SDRAM_MEMODE_DIC_NORMAL 0x00000000 | |
| 1411 | #define SDRAM_MEMODE_DIC_WEAK 0x00000002 | |
| 1412 | #define SDRAM_MEMODE_DLL_MASK 0x00000001 | |
| 1413 | #define SDRAM_MEMODE_DLL_DISABLE 0x00000001 | |
| 1414 | #define SDRAM_MEMODE_DLL_ENABLE 0x00000000 | |
| 1415 | #define SDRAM_MEMODE_RTT_MASK 0x00000044 | |
| 1416 | #define SDRAM_MEMODE_RTT_DISABLED 0x00000000 | |
| 1417 | #define SDRAM_MEMODE_RTT_75OHM 0x00000004 | |
| 1418 | #define SDRAM_MEMODE_RTT_150OHM 0x00000040 | |
| 1419 | #define SDRAM_MEMODE_DQS_MASK 0x00000400 | |
| 1420 | #define SDRAM_MEMODE_DQS_DISABLE 0x00000400 | |
| 1421 | #define SDRAM_MEMODE_DQS_ENABLE 0x00000000 | |
| 1422 | ||
| 1423 | /*-----------------------------------------------------------------------------+ | |
| 1424 | | SDRAM Clock Timing Register | |
| 1425 | +-----------------------------------------------------------------------------*/ | |
| 1426 | #define SDRAM_CLKTR_CLKP_MASK 0xC0000000 | |
| 1427 | #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 | |
| 1428 | #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 | |
| 1429 | ||
| 1430 | /*-----------------------------------------------------------------------------+ | |
| 1431 | | SDRAM Write Timing Register | |
| 1432 | +-----------------------------------------------------------------------------*/ | |
| 1433 | #define SDRAM_WRDTR_WDTP_1_CYC 0x80000000 | |
| 1434 | #define SDRAM_WRDTR_LLWP_MASK 0x10000000 | |
| 1435 | #define SDRAM_WRDTR_LLWP_DIS 0x10000000 | |
| 1436 | #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 | |
| 1437 | #define SDRAM_WRDTR_WTR_MASK 0x0E000000 | |
| 1438 | #define SDRAM_WRDTR_WTR_0_DEG 0x06000000 | |
| 1439 | #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 | |
| 1440 | #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 | |
| 1441 | ||
| 1442 | /*-----------------------------------------------------------------------------+ | |
| 1443 | | SDRAM SDTR1 Options | |
| 1444 | +-----------------------------------------------------------------------------*/ | |
| 1445 | #define SDRAM_SDTR1_LDOF_MASK 0x80000000 | |
| 1446 | #define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 | |
| 1447 | #define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 | |
| 1448 | #define SDRAM_SDTR1_RTW_MASK 0x00F00000 | |
| 1449 | #define SDRAM_SDTR1_RTW_2_CLK 0x00200000 | |
| 1450 | #define SDRAM_SDTR1_RTW_3_CLK 0x00300000 | |
| 1451 | #define SDRAM_SDTR1_WTWO_MASK 0x000F0000 | |
| 1452 | #define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 | |
| 1453 | #define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 | |
| 1454 | #define SDRAM_SDTR1_RTRO_MASK 0x0000F000 | |
| 1455 | #define SDRAM_SDTR1_RTRO_1_CLK 0x00000000 | |
| 1456 | #define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 | |
| 1457 | ||
| 1458 | /*-----------------------------------------------------------------------------+ | |
| 1459 | | SDRAM SDTR2 Options | |
| 1460 | +-----------------------------------------------------------------------------*/ | |
| 1461 | #define SDRAM_SDTR2_RCD_MASK 0xF0000000 | |
| 1462 | #define SDRAM_SDTR2_RCD_1_CLK 0x10000000 | |
| 1463 | #define SDRAM_SDTR2_RCD_2_CLK 0x20000000 | |
| 1464 | #define SDRAM_SDTR2_RCD_3_CLK 0x30000000 | |
| 1465 | #define SDRAM_SDTR2_RCD_4_CLK 0x40000000 | |
| 1466 | #define SDRAM_SDTR2_RCD_5_CLK 0x50000000 | |
| 1467 | #define SDRAM_SDTR2_WTR_MASK 0x0F000000 | |
| 1468 | #define SDRAM_SDTR2_WTR_1_CLK 0x01000000 | |
| 1469 | #define SDRAM_SDTR2_WTR_2_CLK 0x02000000 | |
| 1470 | #define SDRAM_SDTR2_WTR_3_CLK 0x03000000 | |
| 1471 | #define SDRAM_SDTR2_WTR_4_CLK 0x04000000 | |
| 1472 | #define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) | |
| 1473 | #define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 | |
| 1474 | #define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 | |
| 1475 | #define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 | |
| 1476 | #define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 | |
| 1477 | #define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 | |
| 1478 | #define SDRAM_SDTR2_WPC_MASK 0x0000F000 | |
| 1479 | #define SDRAM_SDTR2_WPC_2_CLK 0x00002000 | |
| 1480 | #define SDRAM_SDTR2_WPC_3_CLK 0x00003000 | |
| 1481 | #define SDRAM_SDTR2_WPC_4_CLK 0x00004000 | |
| 1482 | #define SDRAM_SDTR2_WPC_5_CLK 0x00005000 | |
| 1483 | #define SDRAM_SDTR2_WPC_6_CLK 0x00006000 | |
| 1484 | #define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) | |
| 1485 | #define SDRAM_SDTR2_RPC_MASK 0x00000F00 | |
| 1486 | #define SDRAM_SDTR2_RPC_2_CLK 0x00000200 | |
| 1487 | #define SDRAM_SDTR2_RPC_3_CLK 0x00000300 | |
| 1488 | #define SDRAM_SDTR2_RPC_4_CLK 0x00000400 | |
| 1489 | #define SDRAM_SDTR2_RP_MASK 0x000000F0 | |
| 1490 | #define SDRAM_SDTR2_RP_3_CLK 0x00000030 | |
| 1491 | #define SDRAM_SDTR2_RP_4_CLK 0x00000040 | |
| 1492 | #define SDRAM_SDTR2_RP_5_CLK 0x00000050 | |
| 1493 | #define SDRAM_SDTR2_RP_6_CLK 0x00000060 | |
| 1494 | #define SDRAM_SDTR2_RP_7_CLK 0x00000070 | |
| 1495 | #define SDRAM_SDTR2_RRD_MASK 0x0000000F | |
| 1496 | #define SDRAM_SDTR2_RRD_2_CLK 0x00000002 | |
| 1497 | #define SDRAM_SDTR2_RRD_3_CLK 0x00000003 | |
| 1498 | ||
| 1499 | /*-----------------------------------------------------------------------------+ | |
| 1500 | | SDRAM SDTR3 Options | |
| 1501 | +-----------------------------------------------------------------------------*/ | |
| 1502 | #define SDRAM_SDTR3_RAS_MASK 0x1F000000 | |
| 1503 | #define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) | |
| 1504 | #define SDRAM_SDTR3_RC_MASK 0x001F0000 | |
| 1505 | #define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) | |
| 1506 | #define SDRAM_SDTR3_XCS_MASK 0x00001F00 | |
| 1507 | #define SDRAM_SDTR3_XCS 0x00000D00 | |
| 1508 | #define SDRAM_SDTR3_RFC_MASK 0x0000003F | |
| 1509 | #define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) | |
| 1510 | ||
| 1511 | /*-----------------------------------------------------------------------------+ | |
| 1512 | | Memory Bank 0-1 configuration | |
| 1513 | +-----------------------------------------------------------------------------*/ | |
| 1514 | #define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ | |
| 1515 | #define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ | |
| 1516 | #define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ | |
| 1517 | #define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ | |
| 1518 | #define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ | |
| 1519 | #define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ | |
| 1520 | #define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ | |
| 1521 | #define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ | |
| 1522 | #define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ | |
| 1523 | #define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ | |
| 1524 | #define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ | |
| 1525 | #define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ | |
| 1526 | #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ | |
| 1527 | #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ | |
| 1528 | ||
| 1529 | #define sdr_uart0 0x0120 /* UART0 Config */ | |
| 1530 | #define sdr_uart1 0x0121 /* UART1 Config */ | |
| 1531 | #define sdr_mfr 0x4300 /* SDR0_MFR reg */ | |
| 1532 | ||
| 1533 | /* Defines for CPC0_EPRCSR register */ | |
| 1534 | #define CPC0_EPRCSR_E0NFE 0x80000000 | |
| 1535 | #define CPC0_EPRCSR_E1NFE 0x40000000 | |
| 1536 | #define CPC0_EPRCSR_E1RPP 0x00000080 | |
| 1537 | #define CPC0_EPRCSR_E0RPP 0x00000040 | |
| 1538 | #define CPC0_EPRCSR_E1ERP 0x00000020 | |
| 1539 | #define CPC0_EPRCSR_E0ERP 0x00000010 | |
| 1540 | #define CPC0_EPRCSR_E1PCI 0x00000002 | |
| 1541 | #define CPC0_EPRCSR_E0PCI 0x00000001 | |
| 1542 | ||
| 1543 | #define cpr0_clkupd 0x020 | |
| 1544 | #define cpr0_pllc 0x040 | |
| 1545 | #define cpr0_plld 0x060 | |
| 1546 | #define cpr0_cpud 0x080 | |
| 1547 | #define cpr0_plbd 0x0a0 | |
| 1548 | #define cpr0_opbd 0x0c0 | |
| 1549 | #define cpr0_perd 0x0e0 | |
| 1550 | #define cpr0_ahbd 0x100 | |
| 1551 | #define cpr0_icfg 0x140 | |
| 1552 | ||
| 1553 | #define SDR_PINSTP 0x0040 | |
| 1554 | #define sdr_sdcs 0x0060 | |
| 1555 | ||
| 1556 | #define SDR0_SDCS_SDD (0x80000000 >> 31) | |
| 1557 | ||
| 1558 | /* CUST0 Customer Configuration Register0 */ | |
| 1559 | #define SDR0_CUST0 0x4000 | |
| 1560 | #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ | |
| 1561 | #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ | |
| 1562 | #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ | |
| 1563 | #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ | |
| 1564 | ||
| 1565 | #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ | |
| 1566 | #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ | |
| 1567 | #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ | |
| 1568 | ||
| 1569 | #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ | |
| 1570 | #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ | |
| 1571 | #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ | |
| 1572 | ||
| 1573 | #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ | |
| 1574 | #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) | |
| 1575 | #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) | |
| 1576 | ||
| 1577 | #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ | |
| 1578 | #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) | |
| 1579 | #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) | |
| 1580 | ||
| 1581 | #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ | |
| 1582 | #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ | |
| 1583 | #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ | |
| 1584 | ||
| 1585 | #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ | |
| 1586 | #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ | |
| 1587 | #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ | |
| 1588 | ||
| 1589 | #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ | |
| 1590 | #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) | |
| 1591 | #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) | |
| 1592 | ||
| 1593 | #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ | |
| 1594 | #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ | |
| 1595 | #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ | |
| 1596 | #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ | |
| 1597 | #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ | |
| 1598 | #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ | |
| 1599 | #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ | |
| 7cfc12a7 SR |
1600 | |
| 1601 | #define SDR0_PFC0 0x4100 | |
| 1602 | #define SDR0_PFC1 0x4101 | |
| 1603 | #define SDR0_PFC1_U1ME 0x02000000 | |
| 1604 | #define SDR0_PFC1_U0ME 0x00080000 | |
| 1605 | #define SDR0_PFC1_U0IM 0x00040000 | |
| 1606 | #define SDR0_PFC1_SIS 0x00020000 | |
| 1607 | #define SDR0_PFC1_DMAAEN 0x00010000 | |
| 1608 | #define SDR0_PFC1_DMADEN 0x00008000 | |
| 1609 | #define SDR0_PFC1_USBEN 0x00004000 | |
| 1610 | #define SDR0_PFC1_AHBSWAP 0x00000020 | |
| 1611 | #define SDR0_PFC1_USBBIGEN 0x00000010 | |
| 1612 | #define SDR0_PFC1_GPT_FREQ 0x0000000f | |
| dbbd1257 SR |
1613 | #endif |
| 1614 | ||
| 0442ed86 | 1615 | #endif /* __PPC405_H__ */ |