projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0442ed86 WD |
1 | /*----------------------------------------------------------------------------+ |
| 2 | | | |
| 3 | | This source code has been made available to you by IBM on an AS-IS | |
| 4 | | basis. Anyone receiving this source is licensed under IBM | |
| 5 | | copyrights to use it in any way he or she deems fit, including | |
| 6 | | copying it, modifying it, compiling it, and redistributing it either | |
| 7 | | with or without modifications. No license under IBM patents or | |
| 8 | | patent applications is to be implied by the copyright license. | |
| 9 | | | |
| 10 | | Any user of this software should understand that IBM cannot provide | |
| 11 | | technical support for this software and will not be responsible for | |
| 12 | | any consequences resulting from the use of this software. | |
| 13 | | | |
| 14 | | Any person who transfers this source code or any derivative work | |
| 15 | | must include the IBM copyright notice, this paragraph, and the | |
| 16 | | preceding two paragraphs in the transferred software. | |
| 17 | | | |
| 18 | | COPYRIGHT I B M CORPORATION 1999 | |
| 19 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
| 20 | +----------------------------------------------------------------------------*/ | |
| 21 | ||
| 22 | #ifndef __PPC405_H__ | |
| 23 | #define __PPC405_H__ | |
| 24 | ||
| 25 | /*--------------------------------------------------------------------- */ | |
| 26 | /* Special Purpose Registers */ | |
| 27 | /*--------------------------------------------------------------------- */ | |
| 8bde7f77 WD |
28 | #define srr2 0x3de /* save/restore register 2 */ |
| 29 | #define srr3 0x3df /* save/restore register 3 */ | |
| 0442ed86 WD |
30 | #define dbsr 0x3f0 /* debug status register */ |
| 31 | #define dbcr0 0x3f2 /* debug control register 0 */ | |
| 32 | #define dbcr1 0x3bd /* debug control register 1 */ | |
| 33 | #define iac1 0x3f4 /* instruction address comparator 1 */ | |
| 34 | #define iac2 0x3f5 /* instruction address comparator 2 */ | |
| 35 | #define iac3 0x3b4 /* instruction address comparator 3 */ | |
| 36 | #define iac4 0x3b5 /* instruction address comparator 4 */ | |
| 37 | #define dac1 0x3f6 /* data address comparator 1 */ | |
| 38 | #define dac2 0x3f7 /* data address comparator 2 */ | |
| 39 | #define dccr 0x3fa /* data cache control register */ | |
| 40 | #define iccr 0x3fb /* instruction cache control register */ | |
| 41 | #define esr 0x3d4 /* execption syndrome register */ | |
| 42 | #define dear 0x3d5 /* data exeption address register */ | |
| 43 | #define evpr 0x3d6 /* exeption vector prefix register */ | |
| 44 | #define tsr 0x3d8 /* timer status register */ | |
| 45 | #define tcr 0x3da /* timer control register */ | |
| 46 | #define pit 0x3db /* programmable interval timer */ | |
| 8bde7f77 WD |
47 | #define sgr 0x3b9 /* storage guarded reg */ |
| 48 | #define dcwr 0x3ba /* data cache write-thru reg*/ | |
| 49 | #define sler 0x3bb /* storage little-endian reg */ | |
| 0442ed86 WD |
50 | #define cdbcr 0x3d7 /* cache debug cntrl reg */ |
| 51 | #define icdbdr 0x3d3 /* instr cache dbug data reg*/ | |
| 52 | #define ccr0 0x3b3 /* core configuration register */ | |
| 53 | #define dvc1 0x3b6 /* data value compare register 1 */ | |
| 54 | #define dvc2 0x3b7 /* data value compare register 2 */ | |
| 55 | #define pid 0x3b1 /* process ID */ | |
| 56 | #define su0r 0x3bc /* storage user-defined register 0 */ | |
| 57 | #define zpr 0x3b0 /* zone protection regsiter */ | |
| 58 | ||
| 8bde7f77 WD |
59 | #define tbl 0x11c /* time base lower - privileged write */ |
| 60 | #define tbu 0x11d /* time base upper - privileged write */ | |
| 0442ed86 WD |
61 | |
| 62 | #define sprg4r 0x104 /* Special purpose general 4 - read only */ | |
| 63 | #define sprg5r 0x105 /* Special purpose general 5 - read only */ | |
| 64 | #define sprg6r 0x106 /* Special purpose general 6 - read only */ | |
| 65 | #define sprg7r 0x107 /* Special purpose general 7 - read only */ | |
| 66 | #define sprg4w 0x114 /* Special purpose general 4 - write only */ | |
| 67 | #define sprg5w 0x115 /* Special purpose general 5 - write only */ | |
| 68 | #define sprg6w 0x116 /* Special purpose general 6 - write only */ | |
| 69 | #define sprg7w 0x117 /* Special purpose general 7 - write only */ | |
| 70 | ||
| 71 | /****************************************************************************** | |
| 72 | * Special for PPC405GP | |
| 73 | ******************************************************************************/ | |
| 74 | ||
| 75 | /****************************************************************************** | |
| 76 | * DMA | |
| 77 | ******************************************************************************/ | |
| 78 | #define DMA_DCR_BASE 0x100 | |
| 79 | #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ | |
| 80 | #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ | |
| 81 | #define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ | |
| 82 | #define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ | |
| 83 | #define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ | |
| 84 | #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ | |
| 85 | #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ | |
| 86 | #define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ | |
| 87 | #define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ | |
| 88 | #define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ | |
| 89 | #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ | |
| 90 | #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ | |
| 91 | #define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ | |
| 92 | #define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ | |
| 93 | #define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ | |
| 94 | #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ | |
| 95 | #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ | |
| 96 | #define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ | |
| 97 | #define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ | |
| 98 | #define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ | |
| 99 | #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ | |
| 100 | #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ | |
| 101 | #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ | |
| 102 | ||
| 103 | /****************************************************************************** | |
| 104 | * Universal interrupt controller | |
| 105 | ******************************************************************************/ | |
| 106 | #define UIC_DCR_BASE 0xc0 | |
| 107 | #define uicsr (UIC_DCR_BASE+0x0) /* UIC status */ | |
| 108 | #define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */ | |
| 109 | #define uicer (UIC_DCR_BASE+0x2) /* UIC enable */ | |
| 110 | #define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */ | |
| 111 | #define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */ | |
| 112 | #define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */ | |
| 113 | #define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */ | |
| 114 | #define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ | |
| 115 | #define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ | |
| 116 | ||
| 117 | /*-----------------------------------------------------------------------------+ | |
| 118 | | Universal interrupt controller interrupts | |
| 119 | +-----------------------------------------------------------------------------*/ | |
| 120 | #define UIC_UART0 0x80000000 /* UART 0 */ | |
| 121 | #define UIC_UART1 0x40000000 /* UART 1 */ | |
| 122 | #define UIC_IIC 0x20000000 /* IIC */ | |
| 123 | #define UIC_EXT_MAST 0x10000000 /* External Master */ | |
| 124 | #define UIC_PCI 0x08000000 /* PCI write to command reg */ | |
| 125 | #define UIC_DMA0 0x04000000 /* DMA chan. 0 */ | |
| 126 | #define UIC_DMA1 0x02000000 /* DMA chan. 1 */ | |
| 127 | #define UIC_DMA2 0x01000000 /* DMA chan. 2 */ | |
| 128 | #define UIC_DMA3 0x00800000 /* DMA chan. 3 */ | |
| 129 | #define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */ | |
| 130 | #define UIC_MAL_SERR 0x00200000 /* MAL SERR */ | |
| 131 | #define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */ | |
| 132 | #define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */ | |
| 133 | #define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */ | |
| 134 | #define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */ | |
| cea655a2 WD |
135 | #define UIC_ENET 0x00010000 /* Ethernet0 */ |
| 136 | #define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */ | |
| 137 | #define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */ | |
| 0442ed86 | 138 | #define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */ |
| 0442ed86 WD |
139 | #define UIC_PCI_PM 0x00002000 /* PCI Power Management */ |
| 140 | #define UIC_EXT0 0x00000040 /* External interrupt 0 */ | |
| 141 | #define UIC_EXT1 0x00000020 /* External interrupt 1 */ | |
| 142 | #define UIC_EXT2 0x00000010 /* External interrupt 2 */ | |
| 143 | #define UIC_EXT3 0x00000008 /* External interrupt 3 */ | |
| 144 | #define UIC_EXT4 0x00000004 /* External interrupt 4 */ | |
| 145 | #define UIC_EXT5 0x00000002 /* External interrupt 5 */ | |
| 146 | #define UIC_EXT6 0x00000001 /* External interrupt 6 */ | |
| 147 | ||
| 148 | /****************************************************************************** | |
| 149 | * SDRAM Controller | |
| 150 | ******************************************************************************/ | |
| 151 | #define SDRAM_DCR_BASE 0x10 | |
| 152 | #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ | |
| 153 | #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ | |
| 154 | /* values for memcfga register - indirect addressing of these regs */ | |
| b867d705 | 155 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
156 | #define mem_besra 0x00 /* bus error syndrome reg a */ |
| 157 | #define mem_besrsa 0x04 /* bus error syndrome reg set a */ | |
| 158 | #define mem_besrb 0x08 /* bus error syndrome reg b */ | |
| 159 | #define mem_besrsb 0x0c /* bus error syndrome reg set b */ | |
| 160 | #define mem_bear 0x10 /* bus error address reg */ | |
| b867d705 | 161 | #endif |
| 0442ed86 | 162 | #define mem_mcopt1 0x20 /* memory controller options 1 */ |
| ca43ba18 | 163 | #define mem_status 0x24 /* memory status */ |
| 0442ed86 WD |
164 | #define mem_rtr 0x30 /* refresh timer reg */ |
| 165 | #define mem_pmit 0x34 /* power management idle timer */ | |
| 166 | #define mem_mb0cf 0x40 /* memory bank 0 configuration */ | |
| 167 | #define mem_mb1cf 0x44 /* memory bank 1 configuration */ | |
| e075fbe6 | 168 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
169 | #define mem_mb2cf 0x48 /* memory bank 2 configuration */ |
| 170 | #define mem_mb3cf 0x4c /* memory bank 3 configuration */ | |
| e075fbe6 | 171 | #endif |
| 0442ed86 | 172 | #define mem_sdtr1 0x80 /* timing reg 1 */ |
| b867d705 | 173 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
174 | #define mem_ecccf 0x94 /* ECC configuration */ |
| 175 | #define mem_eccerr 0x98 /* ECC error status */ | |
| b867d705 | 176 | #endif |
| 0442ed86 | 177 | |
| e075fbe6 | 178 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
179 | /****************************************************************************** |
| 180 | * Decompression Controller | |
| 181 | ******************************************************************************/ | |
| 182 | #define DECOMP_DCR_BASE 0x14 | |
| 183 | #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ | |
| 184 | #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ | |
| 185 | /* values for kiar register - indirect addressing of these regs */ | |
| 186 | #define kitor0 0x00 /* index table origin register 0 */ | |
| 187 | #define kitor1 0x01 /* index table origin register 1 */ | |
| 188 | #define kitor2 0x02 /* index table origin register 2 */ | |
| 189 | #define kitor3 0x03 /* index table origin register 3 */ | |
| 190 | #define kaddr0 0x04 /* address decode definition regsiter 0 */ | |
| 191 | #define kaddr1 0x05 /* address decode definition regsiter 1 */ | |
| 192 | #define kconf 0x40 /* decompression core config register */ | |
| 193 | #define kid 0x41 /* decompression core ID register */ | |
| 194 | #define kver 0x42 /* decompression core version # reg */ | |
| 195 | #define kpear 0x50 /* bus error addr reg (PLB addr) */ | |
| 196 | #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ | |
| 197 | #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ | |
| 198 | #define kesr0s 0x53 /* bus error status reg 0 (set) */ | |
| 199 | /* There are 0x400 of the following registers, from krom0 to krom3ff*/ | |
| 200 | /* Only the first one is given here. */ | |
| 201 | #define krom0 0x400 /* SRAM/ROM read/write */ | |
| e075fbe6 | 202 | #endif |
| 0442ed86 WD |
203 | |
| 204 | /****************************************************************************** | |
| 205 | * Power Management | |
| 206 | ******************************************************************************/ | |
| 207 | #define POWERMAN_DCR_BASE 0xb8 | |
| 208 | #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ | |
| 209 | #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ | |
| 210 | #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ | |
| 211 | ||
| 212 | /****************************************************************************** | |
| 213 | * Extrnal Bus Controller | |
| 214 | ******************************************************************************/ | |
| 215 | #define EBC_DCR_BASE 0x12 | |
| 216 | #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ | |
| 217 | #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ | |
| 218 | /* values for ebccfga register - indirect addressing of these regs */ | |
| 219 | #define pb0cr 0x00 /* periph bank 0 config reg */ | |
| 220 | #define pb1cr 0x01 /* periph bank 1 config reg */ | |
| 221 | #define pb2cr 0x02 /* periph bank 2 config reg */ | |
| 222 | #define pb3cr 0x03 /* periph bank 3 config reg */ | |
| 223 | #define pb4cr 0x04 /* periph bank 4 config reg */ | |
| e075fbe6 | 224 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
225 | #define pb5cr 0x05 /* periph bank 5 config reg */ |
| 226 | #define pb6cr 0x06 /* periph bank 6 config reg */ | |
| 227 | #define pb7cr 0x07 /* periph bank 7 config reg */ | |
| e075fbe6 | 228 | #endif |
| 0442ed86 WD |
229 | #define pb0ap 0x10 /* periph bank 0 access parameters */ |
| 230 | #define pb1ap 0x11 /* periph bank 1 access parameters */ | |
| 231 | #define pb2ap 0x12 /* periph bank 2 access parameters */ | |
| 232 | #define pb3ap 0x13 /* periph bank 3 access parameters */ | |
| 233 | #define pb4ap 0x14 /* periph bank 4 access parameters */ | |
| e075fbe6 | 234 | #ifndef CONFIG_405EP |
| 0442ed86 WD |
235 | #define pb5ap 0x15 /* periph bank 5 access parameters */ |
| 236 | #define pb6ap 0x16 /* periph bank 6 access parameters */ | |
| 237 | #define pb7ap 0x17 /* periph bank 7 access parameters */ | |
| e075fbe6 | 238 | #endif |
| 0442ed86 WD |
239 | #define pbear 0x20 /* periph bus error addr reg */ |
| 240 | #define pbesr0 0x21 /* periph bus error status reg 0 */ | |
| 241 | #define pbesr1 0x22 /* periph bus error status reg 1 */ | |
| 242 | #define epcr 0x23 /* external periph control reg */ | |
| 4745acaa | 243 | #define EBC0_CFG 0x23 /* external bus configuration reg */ |
| 0442ed86 | 244 | |
| b867d705 SR |
245 | #ifdef CONFIG_405EP |
| 246 | /****************************************************************************** | |
| 247 | * Control | |
| 248 | ******************************************************************************/ | |
| 249 | #define CNTRL_DCR_BASE 0x0f0 | |
| 250 | #define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ | |
| 251 | #define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ | |
| 252 | #define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ | |
| 253 | #define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ | |
| 254 | #define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ | |
| 255 | #define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ | |
| 256 | ||
| 257 | #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ | |
| 258 | #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ | |
| 259 | #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ | |
| 260 | #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ | |
| 261 | #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ | |
| 262 | #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ | |
| 263 | #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ | |
| 264 | #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ | |
| 265 | #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ | |
| 266 | #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ | |
| 267 | ||
| 268 | /* Bit definitions */ | |
| 269 | #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ | |
| 270 | #define PLLMR0_CPU_DIV_BYPASS 0x00000000 | |
| 271 | #define PLLMR0_CPU_DIV_2 0x00100000 | |
| 272 | #define PLLMR0_CPU_DIV_3 0x00200000 | |
| 273 | #define PLLMR0_CPU_DIV_4 0x00300000 | |
| 274 | ||
| 275 | #define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ | |
| 276 | #define PLLMR0_CPU_PLB_DIV_1 0x00000000 | |
| 277 | #define PLLMR0_CPU_PLB_DIV_2 0x00010000 | |
| 278 | #define PLLMR0_CPU_PLB_DIV_3 0x00020000 | |
| 279 | #define PLLMR0_CPU_PLB_DIV_4 0x00030000 | |
| 280 | ||
| 281 | #define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ | |
| 282 | #define PLLMR0_OPB_PLB_DIV_1 0x00000000 | |
| 283 | #define PLLMR0_OPB_PLB_DIV_2 0x00001000 | |
| 284 | #define PLLMR0_OPB_PLB_DIV_3 0x00002000 | |
| 285 | #define PLLMR0_OPB_PLB_DIV_4 0x00003000 | |
| 286 | ||
| 287 | #define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ | |
| 288 | #define PLLMR0_EXB_PLB_DIV_2 0x00000000 | |
| 289 | #define PLLMR0_EXB_PLB_DIV_3 0x00000100 | |
| 290 | #define PLLMR0_EXB_PLB_DIV_4 0x00000200 | |
| 291 | #define PLLMR0_EXB_PLB_DIV_5 0x00000300 | |
| 292 | ||
| 293 | #define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ | |
| 294 | #define PLLMR0_MAL_PLB_DIV_1 0x00000000 | |
| 295 | #define PLLMR0_MAL_PLB_DIV_2 0x00000010 | |
| 296 | #define PLLMR0_MAL_PLB_DIV_3 0x00000020 | |
| 297 | #define PLLMR0_MAL_PLB_DIV_4 0x00000030 | |
| 298 | ||
| 299 | #define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ | |
| 300 | #define PLLMR0_PCI_PLB_DIV_1 0x00000000 | |
| 301 | #define PLLMR0_PCI_PLB_DIV_2 0x00000001 | |
| 302 | #define PLLMR0_PCI_PLB_DIV_3 0x00000002 | |
| 303 | #define PLLMR0_PCI_PLB_DIV_4 0x00000003 | |
| 304 | ||
| 305 | #define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ | |
| 306 | #define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ | |
| 307 | #define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ | |
| 308 | #define PLLMR1_FBMUL_DIV_16 0x00000000 | |
| 309 | #define PLLMR1_FBMUL_DIV_1 0x00100000 | |
| 310 | #define PLLMR1_FBMUL_DIV_2 0x00200000 | |
| 311 | #define PLLMR1_FBMUL_DIV_3 0x00300000 | |
| 312 | #define PLLMR1_FBMUL_DIV_4 0x00400000 | |
| 313 | #define PLLMR1_FBMUL_DIV_5 0x00500000 | |
| 314 | #define PLLMR1_FBMUL_DIV_6 0x00600000 | |
| 315 | #define PLLMR1_FBMUL_DIV_7 0x00700000 | |
| 316 | #define PLLMR1_FBMUL_DIV_8 0x00800000 | |
| 317 | #define PLLMR1_FBMUL_DIV_9 0x00900000 | |
| 318 | #define PLLMR1_FBMUL_DIV_10 0x00A00000 | |
| 319 | #define PLLMR1_FBMUL_DIV_11 0x00B00000 | |
| 320 | #define PLLMR1_FBMUL_DIV_12 0x00C00000 | |
| 321 | #define PLLMR1_FBMUL_DIV_13 0x00D00000 | |
| 322 | #define PLLMR1_FBMUL_DIV_14 0x00E00000 | |
| 323 | #define PLLMR1_FBMUL_DIV_15 0x00F00000 | |
| 324 | ||
| 325 | #define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ | |
| 326 | #define PLLMR1_FWDVA_DIV_8 0x00000000 | |
| 327 | #define PLLMR1_FWDVA_DIV_7 0x00010000 | |
| 328 | #define PLLMR1_FWDVA_DIV_6 0x00020000 | |
| 329 | #define PLLMR1_FWDVA_DIV_5 0x00030000 | |
| 330 | #define PLLMR1_FWDVA_DIV_4 0x00040000 | |
| 331 | #define PLLMR1_FWDVA_DIV_3 0x00050000 | |
| 332 | #define PLLMR1_FWDVA_DIV_2 0x00060000 | |
| 333 | #define PLLMR1_FWDVA_DIV_1 0x00070000 | |
| 334 | #define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ | |
| 335 | #define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ | |
| 336 | ||
| 337 | /* Defines for CPC0_EPRCSR register */ | |
| 338 | #define CPC0_EPRCSR_E0NFE 0x80000000 | |
| 339 | #define CPC0_EPRCSR_E1NFE 0x40000000 | |
| 340 | #define CPC0_EPRCSR_E1RPP 0x00000080 | |
| 341 | #define CPC0_EPRCSR_E0RPP 0x00000040 | |
| 342 | #define CPC0_EPRCSR_E1ERP 0x00000020 | |
| 343 | #define CPC0_EPRCSR_E0ERP 0x00000010 | |
| 344 | #define CPC0_EPRCSR_E1PCI 0x00000002 | |
| 345 | #define CPC0_EPRCSR_E0PCI 0x00000001 | |
| 346 | ||
| 347 | /* Defines for CPC0_PCI Register */ | |
| 348 | #define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ | |
| 349 | #define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ | |
| 350 | #define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ | |
| 351 | ||
| 352 | /* Defines for CPC0_BOOR Register */ | |
| 353 | #define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ | |
| 354 | ||
| 355 | /* Defines for CPC0_PLLMR1 Register fields */ | |
| 356 | #define PLL_ACTIVE 0x80000000 | |
| 357 | #define CPC0_PLLMR1_SSCS 0x80000000 | |
| 358 | #define PLL_RESET 0x40000000 | |
| 359 | #define CPC0_PLLMR1_PLLR 0x40000000 | |
| 360 | /* Feedback multiplier */ | |
| 361 | #define PLL_FBKDIV 0x00F00000 | |
| 362 | #define CPC0_PLLMR1_FBDV 0x00F00000 | |
| 363 | #define PLL_FBKDIV_16 0x00000000 | |
| 364 | #define PLL_FBKDIV_1 0x00100000 | |
| 365 | #define PLL_FBKDIV_2 0x00200000 | |
| 366 | #define PLL_FBKDIV_3 0x00300000 | |
| 367 | #define PLL_FBKDIV_4 0x00400000 | |
| 368 | #define PLL_FBKDIV_5 0x00500000 | |
| 369 | #define PLL_FBKDIV_6 0x00600000 | |
| 370 | #define PLL_FBKDIV_7 0x00700000 | |
| 371 | #define PLL_FBKDIV_8 0x00800000 | |
| 372 | #define PLL_FBKDIV_9 0x00900000 | |
| 373 | #define PLL_FBKDIV_10 0x00A00000 | |
| 374 | #define PLL_FBKDIV_11 0x00B00000 | |
| 375 | #define PLL_FBKDIV_12 0x00C00000 | |
| 376 | #define PLL_FBKDIV_13 0x00D00000 | |
| 377 | #define PLL_FBKDIV_14 0x00E00000 | |
| 378 | #define PLL_FBKDIV_15 0x00F00000 | |
| 379 | /* Forward A divisor */ | |
| 380 | #define PLL_FWDDIVA 0x00070000 | |
| 381 | #define CPC0_PLLMR1_FWDVA 0x00070000 | |
| 382 | #define PLL_FWDDIVA_8 0x00000000 | |
| 383 | #define PLL_FWDDIVA_7 0x00010000 | |
| 384 | #define PLL_FWDDIVA_6 0x00020000 | |
| 385 | #define PLL_FWDDIVA_5 0x00030000 | |
| 386 | #define PLL_FWDDIVA_4 0x00040000 | |
| 387 | #define PLL_FWDDIVA_3 0x00050000 | |
| 388 | #define PLL_FWDDIVA_2 0x00060000 | |
| 389 | #define PLL_FWDDIVA_1 0x00070000 | |
| 390 | /* Forward B divisor */ | |
| 391 | #define PLL_FWDDIVB 0x00007000 | |
| 392 | #define CPC0_PLLMR1_FWDVB 0x00007000 | |
| 393 | #define PLL_FWDDIVB_8 0x00000000 | |
| 394 | #define PLL_FWDDIVB_7 0x00001000 | |
| 395 | #define PLL_FWDDIVB_6 0x00002000 | |
| 396 | #define PLL_FWDDIVB_5 0x00003000 | |
| 397 | #define PLL_FWDDIVB_4 0x00004000 | |
| 398 | #define PLL_FWDDIVB_3 0x00005000 | |
| 399 | #define PLL_FWDDIVB_2 0x00006000 | |
| 400 | #define PLL_FWDDIVB_1 0x00007000 | |
| 401 | /* PLL tune bits */ | |
| 402 | #define PLL_TUNE_MASK 0x000003FF | |
| 403 | #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ | |
| 404 | #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ | |
| 405 | #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ | |
| 406 | #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ | |
| 407 | #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ | |
| 408 | #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ | |
| 409 | #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ | |
| 410 | ||
| 411 | /* Defines for CPC0_PLLMR0 Register fields */ | |
| 412 | /* CPU divisor */ | |
| 413 | #define PLL_CPUDIV 0x00300000 | |
| 414 | #define CPC0_PLLMR0_CCDV 0x00300000 | |
| 415 | #define PLL_CPUDIV_1 0x00000000 | |
| 416 | #define PLL_CPUDIV_2 0x00100000 | |
| 417 | #define PLL_CPUDIV_3 0x00200000 | |
| 418 | #define PLL_CPUDIV_4 0x00300000 | |
| 419 | /* PLB divisor */ | |
| 420 | #define PLL_PLBDIV 0x00030000 | |
| 421 | #define CPC0_PLLMR0_CBDV 0x00030000 | |
| 422 | #define PLL_PLBDIV_1 0x00000000 | |
| 423 | #define PLL_PLBDIV_2 0x00010000 | |
| 424 | #define PLL_PLBDIV_3 0x00020000 | |
| 425 | #define PLL_PLBDIV_4 0x00030000 | |
| 426 | /* OPB divisor */ | |
| 427 | #define PLL_OPBDIV 0x00003000 | |
| 428 | #define CPC0_PLLMR0_OPDV 0x00003000 | |
| 429 | #define PLL_OPBDIV_1 0x00000000 | |
| 430 | #define PLL_OPBDIV_2 0x00001000 | |
| 431 | #define PLL_OPBDIV_3 0x00002000 | |
| 432 | #define PLL_OPBDIV_4 0x00003000 | |
| 433 | /* EBC divisor */ | |
| 434 | #define PLL_EXTBUSDIV 0x00000300 | |
| 435 | #define CPC0_PLLMR0_EPDV 0x00000300 | |
| 436 | #define PLL_EXTBUSDIV_2 0x00000000 | |
| 437 | #define PLL_EXTBUSDIV_3 0x00000100 | |
| 438 | #define PLL_EXTBUSDIV_4 0x00000200 | |
| 439 | #define PLL_EXTBUSDIV_5 0x00000300 | |
| 440 | /* MAL divisor */ | |
| 441 | #define PLL_MALDIV 0x00000030 | |
| 442 | #define CPC0_PLLMR0_MPDV 0x00000030 | |
| 443 | #define PLL_MALDIV_1 0x00000000 | |
| 444 | #define PLL_MALDIV_2 0x00000010 | |
| 445 | #define PLL_MALDIV_3 0x00000020 | |
| 446 | #define PLL_MALDIV_4 0x00000030 | |
| 447 | /* PCI divisor */ | |
| 448 | #define PLL_PCIDIV 0x00000003 | |
| 449 | #define CPC0_PLLMR0_PPFD 0x00000003 | |
| 450 | #define PLL_PCIDIV_1 0x00000000 | |
| 451 | #define PLL_PCIDIV_2 0x00000001 | |
| 452 | #define PLL_PCIDIV_3 0x00000002 | |
| 453 | #define PLL_PCIDIV_4 0x00000003 | |
| 454 | ||
| 455 | /* | |
| 456 | *------------------------------------------------------------------------------- | |
| 457 | * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, | |
| 458 | * assuming a 33.3MHz input clock to the 405EP. | |
| 459 | *------------------------------------------------------------------------------- | |
| 460 | */ | |
| 461 | #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ | |
| 8bde7f77 WD |
462 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ |
| 463 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
| b867d705 | 464 | #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ |
| 8bde7f77 WD |
465 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ |
| 466 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| b867d705 SR |
467 | |
| 468 | #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ | |
| 8bde7f77 WD |
469 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ |
| 470 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
| b867d705 | 471 | #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ |
| 8bde7f77 WD |
472 | PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ |
| 473 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| b867d705 | 474 | #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
| 8bde7f77 WD |
475 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ |
| 476 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
| b867d705 | 477 | #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ |
| 8bde7f77 WD |
478 | PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ |
| 479 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| b867d705 | 480 | #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
| 8bde7f77 WD |
481 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ |
| 482 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
| b867d705 | 483 | #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ |
| 8bde7f77 WD |
484 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ |
| 485 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| 44acc8d3 | 486 | #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ |
| efe2a4d5 WD |
487 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ |
| 488 | PLL_MALDIV_1 | PLL_PCIDIV_2) | |
| 44acc8d3 | 489 | #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ |
| efe2a4d5 WD |
490 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ |
| 491 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
| b867d705 SR |
492 | |
| 493 | /* | |
| 494 | * PLL Voltage Controlled Oscillator (VCO) definitions | |
| 495 | * Maximum and minimum values (in MHz) for correct PLL operation. | |
| 496 | */ | |
| 497 | #define VCO_MIN 500 | |
| 498 | #define VCO_MAX 1000 | |
| 499 | #else /* #ifdef CONFIG_405EP */ | |
| 0442ed86 WD |
500 | /****************************************************************************** |
| 501 | * Control | |
| 502 | ******************************************************************************/ | |
| 503 | #define CNTRL_DCR_BASE 0x0b0 | |
| 504 | #define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ | |
| 505 | #define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ | |
| 506 | #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ | |
| 507 | #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ | |
| 508 | #define strap (CNTRL_DCR_BASE+0x4) /* strap register */ | |
| b867d705 SR |
509 | |
| 510 | #define ecr (0xaa) /* edge conditioner register (405gpr) */ | |
| 0442ed86 WD |
511 | |
| 512 | /* Bit definitions */ | |
| 513 | #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ | |
| 514 | #define PLLMR_FWD_DIV_BYPASS 0xE0000000 | |
| 515 | #define PLLMR_FWD_DIV_3 0xA0000000 | |
| 516 | #define PLLMR_FWD_DIV_4 0x80000000 | |
| 517 | #define PLLMR_FWD_DIV_6 0x40000000 | |
| 518 | ||
| 519 | #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ | |
| 520 | #define PLLMR_FB_DIV_1 0x02000000 | |
| 521 | #define PLLMR_FB_DIV_2 0x04000000 | |
| 522 | #define PLLMR_FB_DIV_3 0x06000000 | |
| 523 | #define PLLMR_FB_DIV_4 0x08000000 | |
| 524 | ||
| 525 | #define PLLMR_TUNING_MASK 0x01F80000 | |
| 526 | ||
| 527 | #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ | |
| 528 | #define PLLMR_CPU_PLB_DIV_1 0x00000000 | |
| 529 | #define PLLMR_CPU_PLB_DIV_2 0x00020000 | |
| 530 | #define PLLMR_CPU_PLB_DIV_3 0x00040000 | |
| 531 | #define PLLMR_CPU_PLB_DIV_4 0x00060000 | |
| 532 | ||
| 533 | #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ | |
| 534 | #define PLLMR_OPB_PLB_DIV_1 0x00000000 | |
| 535 | #define PLLMR_OPB_PLB_DIV_2 0x00008000 | |
| 536 | #define PLLMR_OPB_PLB_DIV_3 0x00010000 | |
| 537 | #define PLLMR_OPB_PLB_DIV_4 0x00018000 | |
| 538 | ||
| 539 | #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ | |
| 540 | #define PLLMR_PCI_PLB_DIV_1 0x00000000 | |
| 541 | #define PLLMR_PCI_PLB_DIV_2 0x00002000 | |
| 542 | #define PLLMR_PCI_PLB_DIV_3 0x00004000 | |
| 543 | #define PLLMR_PCI_PLB_DIV_4 0x00006000 | |
| 544 | ||
| 545 | #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ | |
| 546 | #define PLLMR_EXB_PLB_DIV_2 0x00000000 | |
| 547 | #define PLLMR_EXB_PLB_DIV_3 0x00000800 | |
| 548 | #define PLLMR_EXB_PLB_DIV_4 0x00001000 | |
| 549 | #define PLLMR_EXB_PLB_DIV_5 0x00001800 | |
| 550 | ||
| 551 | /* definitions for PPC405GPr (new mode strapping) */ | |
| 552 | #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ | |
| 553 | ||
| 554 | #define PSR_PLL_FWD_MASK 0xC0000000 | |
| 555 | #define PSR_PLL_FDBACK_MASK 0x30000000 | |
| 556 | #define PSR_PLL_TUNING_MASK 0x0E000000 | |
| 557 | #define PSR_PLB_CPU_MASK 0x01800000 | |
| 558 | #define PSR_OPB_PLB_MASK 0x00600000 | |
| 559 | #define PSR_PCI_PLB_MASK 0x00180000 | |
| 560 | #define PSR_EB_PLB_MASK 0x00060000 | |
| 561 | #define PSR_ROM_WIDTH_MASK 0x00018000 | |
| 562 | #define PSR_ROM_LOC 0x00004000 | |
| 563 | #define PSR_PCI_ASYNC_EN 0x00001000 | |
| 564 | #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ | |
| 565 | #define PSR_PCI_ARBIT_EN 0x00000400 | |
| 566 | #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ | |
| 567 | ||
| 44acc8d3 | 568 | #ifndef CONFIG_IOP480 |
| 0442ed86 WD |
569 | /* |
| 570 | * PLL Voltage Controlled Oscillator (VCO) definitions | |
| 571 | * Maximum and minimum values (in MHz) for correct PLL operation. | |
| 572 | */ | |
| 573 | #define VCO_MIN 400 | |
| 574 | #define VCO_MAX 800 | |
| 44acc8d3 | 575 | #endif /* #ifndef CONFIG_IOP480 */ |
| b867d705 | 576 | #endif /* #ifdef CONFIG_405EP */ |
| 0442ed86 WD |
577 | |
| 578 | /****************************************************************************** | |
| 579 | * Memory Access Layer | |
| 580 | ******************************************************************************/ | |
| 581 | #define MAL_DCR_BASE 0x180 | |
| 582 | #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ | |
| 583 | #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ | |
| 584 | #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ | |
| 585 | #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ | |
| 586 | #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ | |
| 587 | #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ | |
| 588 | #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ | |
| 589 | #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ | |
| 590 | #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ | |
| 591 | #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ | |
| 592 | #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ | |
| 593 | #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ | |
| 594 | #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ | |
| 595 | #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ | |
| cea655a2 | 596 | #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ |
| 0442ed86 | 597 | #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ |
| cea655a2 | 598 | #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ |
| 0442ed86 | 599 | #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ |
| cea655a2 | 600 | #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ |
| 0442ed86 WD |
601 | |
| 602 | /*----------------------------------------------------------------------------- | |
| 603 | | IIC Register Offsets | |
| 604 | '----------------------------------------------------------------------------*/ | |
| 605 | #define IICMDBUF 0x00 | |
| 606 | #define IICSDBUF 0x02 | |
| 607 | #define IICLMADR 0x04 | |
| 608 | #define IICHMADR 0x05 | |
| 609 | #define IICCNTL 0x06 | |
| 610 | #define IICMDCNTL 0x07 | |
| 611 | #define IICSTS 0x08 | |
| 612 | #define IICEXTSTS 0x09 | |
| 613 | #define IICLSADR 0x0A | |
| 614 | #define IICHSADR 0x0B | |
| 615 | #define IICCLKDIV 0x0C | |
| 616 | #define IICINTRMSK 0x0D | |
| 617 | #define IICXFRCNT 0x0E | |
| 618 | #define IICXTCNTLSS 0x0F | |
| 619 | #define IICDIRECTCNTL 0x10 | |
| 620 | ||
| 621 | /*----------------------------------------------------------------------------- | |
| 622 | | UART Register Offsets | |
| 623 | '----------------------------------------------------------------------------*/ | |
| 624 | #define DATA_REG 0x00 | |
| 625 | #define DL_LSB 0x00 | |
| 626 | #define DL_MSB 0x01 | |
| 627 | #define INT_ENABLE 0x01 | |
| 628 | #define FIFO_CONTROL 0x02 | |
| 629 | #define LINE_CONTROL 0x03 | |
| 630 | #define MODEM_CONTROL 0x04 | |
| 631 | #define LINE_STATUS 0x05 | |
| 632 | #define MODEM_STATUS 0x06 | |
| 633 | #define SCRATCH 0x07 | |
| 634 | ||
| 635 | /****************************************************************************** | |
| 636 | * On Chip Memory | |
| 637 | ******************************************************************************/ | |
| 638 | #define OCM_DCR_BASE 0x018 | |
| 639 | #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ | |
| 640 | #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ | |
| 641 | #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ | |
| 642 | #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ | |
| 643 | ||
| b867d705 SR |
644 | /****************************************************************************** |
| 645 | * GPIO macro register defines | |
| 646 | ******************************************************************************/ | |
| 647 | #define GPIO_BASE 0xEF600700 | |
| 648 | #define GPIO0_OR (GPIO_BASE+0x0) | |
| 649 | #define GPIO0_TCR (GPIO_BASE+0x4) | |
| 650 | #define GPIO0_OSRH (GPIO_BASE+0x8) | |
| 651 | #define GPIO0_OSRL (GPIO_BASE+0xC) | |
| 652 | #define GPIO0_TSRH (GPIO_BASE+0x10) | |
| 653 | #define GPIO0_TSRL (GPIO_BASE+0x14) | |
| 654 | #define GPIO0_ODR (GPIO_BASE+0x18) | |
| 655 | #define GPIO0_IR (GPIO_BASE+0x1C) | |
| 656 | #define GPIO0_RR1 (GPIO_BASE+0x20) | |
| 657 | #define GPIO0_RR2 (GPIO_BASE+0x24) | |
| 658 | #define GPIO0_ISR1H (GPIO_BASE+0x30) | |
| 659 | #define GPIO0_ISR1L (GPIO_BASE+0x34) | |
| 660 | #define GPIO0_ISR2H (GPIO_BASE+0x38) | |
| 661 | #define GPIO0_ISR2L (GPIO_BASE+0x3C) | |
| 662 | ||
| 0442ed86 WD |
663 | |
| 664 | /* | |
| 665 | * Macro for accessing the indirect EBC register | |
| 666 | */ | |
| 667 | #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) | |
| 668 | #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) | |
| 669 | ||
| 670 | ||
| 671 | #ifndef __ASSEMBLY__ | |
| 672 | ||
| 673 | typedef struct | |
| 674 | { | |
| 675 | unsigned long pllFwdDiv; | |
| 676 | unsigned long pllFwdDivB; | |
| 677 | unsigned long pllFbkDiv; | |
| 678 | unsigned long pllPlbDiv; | |
| 679 | unsigned long pllPciDiv; | |
| 680 | unsigned long pllExtBusDiv; | |
| 681 | unsigned long pllOpbDiv; | |
| 682 | unsigned long freqVCOMhz; /* in MHz */ | |
| 683 | unsigned long freqProcessor; | |
| 684 | unsigned long freqPLB; | |
| 685 | unsigned long freqPCI; | |
| 686 | unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ | |
| 687 | unsigned long pciClkSync; /* PCI clock is synchronous */ | |
| 44acc8d3 | 688 | unsigned long freqVCOHz; |
| 0442ed86 WD |
689 | } PPC405_SYS_INFO; |
| 690 | ||
| 691 | #endif /* _ASMLANGUAGE */ | |
| 692 | ||
| 693 | #define RESET_VECTOR 0xfffffffc | |
| 694 | #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache | |
| 695 | line aligned data. */ | |
| 696 | ||
| 697 | #endif /* __PPC405_H__ */ |