[people/ms/u-boot.git] / include / ppc4xx.h

/*----------------------------------------------------------------------------+
|
|       This source code has been made available to you by IBM on an AS-IS
|       basis.  Anyone receiving this source is licensed under IBM
|       copyrights to use it in any way he or she deems fit, including
|       copying it, modifying it, compiling it, and redistributing it either
|       with or without modifications.  No license under IBM patents or
|       patent applications is to be implied by the copyright license.
|
|       Any user of this software should understand that IBM cannot provide
|       technical support for this software and will not be responsible for
|       any consequences resulting from the use of this software.
|
|       Any person who transfers this source code or any derivative work
|       must include the IBM copyright notice, this paragraph, and the
|       preceding two paragraphs in the transferred software.
|
|       COPYRIGHT   I B M   CORPORATION 1999
|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+----------------------------------------------------------------------------*/

#ifndef	__PPC4XX_H__
#define __PPC4XX_H__

#if defined(CONFIG_440)
#include <ppc440.h>
#else
#include <ppc405.h>
#endif

/*
 * Common stuff for 4xx (405 and 440)
 */

#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
#define _START_OFFSET		(EXC_OFF_SYS_RESET + 0x2000)

#define RESET_VECTOR	0xfffffffc
#define CACHELINE_MASK	(CFG_CACHELINE_SIZE - 1) /* Address mask for cache
						     line aligned data. */

#define CPR0_DCR_BASE	0x0C
#define cprcfga		(CPR0_DCR_BASE+0x0)
#define cprcfgd		(CPR0_DCR_BASE+0x1)

#define SDR_DCR_BASE	0x0E
#define sdrcfga		(SDR_DCR_BASE+0x0)
#define sdrcfgd		(SDR_DCR_BASE+0x1)

#define SDRAM_DCR_BASE	0x10
#define memcfga		(SDRAM_DCR_BASE+0x0)
#define memcfgd		(SDRAM_DCR_BASE+0x1)

#define EBC_DCR_BASE	0x12
#define ebccfga		(EBC_DCR_BASE+0x0)
#define ebccfgd		(EBC_DCR_BASE+0x1)

/*
 * Macros for indirect DCR access
 */
#define mtcpr(reg, d)	do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
#define mfcpr(reg, d)	do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)

#define mtebc(reg, d)	do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
#define mfebc(reg, d)	do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)

#define mtsdram(reg, d)	do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
#define mfsdram(reg, d)	do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)

#define mtsdr(reg, d)	do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
#define mfsdr(reg, d)	do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)

#ifndef __ASSEMBLY__

typedef struct
{
	unsigned long freqDDR;
	unsigned long freqEBC;
	unsigned long freqOPB;
	unsigned long freqPCI;
	unsigned long freqPLB;
	unsigned long freqTmrClk;
	unsigned long freqUART;
	unsigned long freqProcessor;
	unsigned long freqVCOHz;
	unsigned long freqVCOMhz;	/* in MHz                          */
	unsigned long pciClkSync;	/* PCI clock is synchronous        */
	unsigned long pciIntArbEn;	/* Internal PCI arbiter is enabled */
	unsigned long pllExtBusDiv;
	unsigned long pllFbkDiv;
	unsigned long pllFwdDiv;
	unsigned long pllFwdDivA;
	unsigned long pllFwdDivB;
	unsigned long pllOpbDiv;
	unsigned long pllPciDiv;
	unsigned long pllPlbDiv;
} PPC4xx_SYS_INFO;

#endif	/* __ASSEMBLY__ */

#endif	/* __PPC4XX_H__ */
Commit	Line	Data
935ecca1 WD	1	/*----------------------------------------------------------------------------+
	2	\|
	3	\| This source code has been made available to you by IBM on an AS-IS
	4	\| basis. Anyone receiving this source is licensed under IBM
	5	\| copyrights to use it in any way he or she deems fit, including
	6	\| copying it, modifying it, compiling it, and redistributing it either
	7	\| with or without modifications. No license under IBM patents or
	8	\| patent applications is to be implied by the copyright license.
	9	\|
	10	\| Any user of this software should understand that IBM cannot provide
	11	\| technical support for this software and will not be responsible for
	12	\| any consequences resulting from the use of this software.
	13	\|
	14	\| Any person who transfers this source code or any derivative work
	15	\| must include the IBM copyright notice, this paragraph, and the
	16	\| preceding two paragraphs in the transferred software.
	17	\|
	18	\| COPYRIGHT I B M CORPORATION 1999
	19	\| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
	20	+----------------------------------------------------------------------------*/
	21
	22	#ifndef __PPC4XX_H__
	23	#define __PPC4XX_H__
	24
935ecca1 WD	25	#if defined(CONFIG_440)
	26	#include <ppc440.h>
	27	#else
	28	#include <ppc405.h>
	29	#endif
	30
087dfdb7 SR	31	/*
	32	* Common stuff for 4xx (405 and 440)
	33	*/
	34
	35	#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
	36	#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
	37
	38	#define RESET_VECTOR 0xfffffffc
	39	#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
	40	line aligned data. */
	41
	42	#define CPR0_DCR_BASE 0x0C
	43	#define cprcfga (CPR0_DCR_BASE+0x0)
	44	#define cprcfgd (CPR0_DCR_BASE+0x1)
	45
	46	#define SDR_DCR_BASE 0x0E
	47	#define sdrcfga (SDR_DCR_BASE+0x0)
	48	#define sdrcfgd (SDR_DCR_BASE+0x1)
	49
	50	#define SDRAM_DCR_BASE 0x10
	51	#define memcfga (SDRAM_DCR_BASE+0x0)
	52	#define memcfgd (SDRAM_DCR_BASE+0x1)
	53
	54	#define EBC_DCR_BASE 0x12
	55	#define ebccfga (EBC_DCR_BASE+0x0)
	56	#define ebccfgd (EBC_DCR_BASE+0x1)
	57
	58	/*
	59	* Macros for indirect DCR access
	60	*/
	61	#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
	62	#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
	63
	64	#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
	65	#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
	66
	67	#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
	68	#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
	69
	70	#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
	71	#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
	72
	73	#ifndef __ASSEMBLY__
	74
	75	typedef struct
	76	{
	77	unsigned long freqDDR;
	78	unsigned long freqEBC;
	79	unsigned long freqOPB;
	80	unsigned long freqPCI;
	81	unsigned long freqPLB;
	82	unsigned long freqTmrClk;
	83	unsigned long freqUART;
	84	unsigned long freqProcessor;
	85	unsigned long freqVCOHz;
	86	unsigned long freqVCOMhz; /* in MHz */
	87	unsigned long pciClkSync; /* PCI clock is synchronous */
	88	unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
	89	unsigned long pllExtBusDiv;
	90	unsigned long pllFbkDiv;
	91	unsigned long pllFwdDiv;
	92	unsigned long pllFwdDivA;
	93	unsigned long pllFwdDivB;
	94	unsigned long pllOpbDiv;
95	unsigned long pllPciDiv;
96	unsigned long pllPlbDiv;
97	} PPC4xx_SYS_INFO;
98
99	#endif /* __ASSEMBLY__ */
100
935ecca1	101	#endif /* __PPC4XX_H__ */