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ba56f625 WD |
1 | /*----------------------------------------------------------------------------+ |
2 | | | |
3 | | This source code has been made available to you by IBM on an AS-IS | |
4 | | basis. Anyone receiving this source is licensed under IBM | |
5 | | copyrights to use it in any way he or she deems fit, including | |
6 | | copying it, modifying it, compiling it, and redistributing it either | |
7 | | with or without modifications. No license under IBM patents or | |
8 | | patent applications is to be implied by the copyright license. | |
9 | | | |
10 | | Any user of this software should understand that IBM cannot provide | |
11 | | technical support for this software and will not be responsible for | |
12 | | any consequences resulting from the use of this software. | |
13 | | | |
14 | | Any person who transfers this source code or any derivative work | |
15 | | must include the IBM copyright notice, this paragraph, and the | |
16 | | preceding two paragraphs in the transferred software. | |
17 | | | |
18 | | COPYRIGHT I B M CORPORATION 1999 | |
19 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
20 | +----------------------------------------------------------------------------*/ | |
21 | /*----------------------------------------------------------------------------+ | |
22 | | | |
23 | | File Name: enetemac.h | |
24 | | | |
25 | | Function: Header file for the EMAC3 macro on the 405GP. | |
26 | | | |
27 | | Author: Mark Wisner | |
28 | | | |
29 | | Change Activity- | |
30 | | | |
31 | | Date Description of Change BY | |
32 | | --------- --------------------- --- | |
33 | | 29-Apr-99 Created MKW | |
34 | | | |
35 | +----------------------------------------------------------------------------*/ | |
36 | /*----------------------------------------------------------------------------+ | |
37 | | 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com | |
38 | | ported to handle 440GP and 440GX multiple EMACs | |
39 | +----------------------------------------------------------------------------*/ | |
40 | ||
d6c61aab SR |
41 | #ifndef _PPC4XX_ENET_H_ |
42 | #define _PPC4XX_ENET_H_ | |
ba56f625 | 43 | |
ba56f625 WD |
44 | #include <net.h> |
45 | #include "405_mal.h" | |
46 | ||
47 | ||
48 | /*-----------------------------------------------------------------------------+ | |
49 | | General enternet defines. 802 frames are not supported. | |
50 | +-----------------------------------------------------------------------------*/ | |
51 | #define ENET_ADDR_LENGTH 6 | |
52 | #define ENET_ARPTYPE 0x806 | |
53 | #define ARP_REQUEST 1 | |
54 | #define ARP_REPLY 2 | |
55 | #define ENET_IPTYPE 0x800 | |
56 | #define ARP_CACHE_SIZE 5 | |
57 | ||
58 | #define NUM_TX_BUFF 1 | |
59 | #define NUM_RX_BUFF PKTBUFSRX | |
60 | ||
61 | struct enet_frame { | |
62 | unsigned char dest_addr[ENET_ADDR_LENGTH]; | |
63 | unsigned char source_addr[ENET_ADDR_LENGTH]; | |
64 | unsigned short type; | |
65 | unsigned char enet_data[1]; | |
66 | }; | |
67 | ||
68 | struct arp_entry { | |
69 | unsigned long inet_address; | |
70 | unsigned char mac_address[ENET_ADDR_LENGTH]; | |
71 | unsigned long valid; | |
72 | unsigned long sec; | |
73 | unsigned long nsec; | |
74 | }; | |
75 | ||
76 | ||
77 | /* Statistic Areas */ | |
78 | #define MAX_ERR_LOG 10 | |
79 | ||
80 | typedef struct emac_stats_st{ /* Statistic Block */ | |
81 | int data_len_err; | |
82 | int rx_frames; | |
83 | int rx; | |
84 | int rx_prot_err; | |
85 | int int_err; | |
d6c61aab SR |
86 | int pkts_tx; |
87 | int pkts_rx; | |
88 | int pkts_handled; | |
ba56f625 WD |
89 | short tx_err_log[MAX_ERR_LOG]; |
90 | short rx_err_log[MAX_ERR_LOG]; | |
91 | } EMAC_STATS_ST, *EMAC_STATS_PST; | |
92 | ||
d6c61aab SR |
93 | /* Structure containing variables used by the shared code (4xx_enet.c) */ |
94 | typedef struct emac_4xx_hw_st { | |
ba56f625 WD |
95 | uint32_t hw_addr; /* EMAC offset */ |
96 | uint32_t tah_addr; /* TAH offset */ | |
97 | uint32_t phy_id; | |
98 | uint32_t phy_addr; | |
99 | uint32_t original_fc; | |
100 | uint32_t txcw; | |
101 | uint32_t autoneg_failed; | |
102 | uint32_t emac_ier; | |
103 | volatile mal_desc_t *tx; | |
104 | volatile mal_desc_t *rx; | |
105 | bd_t *bis; /* for eth_init upon mal error */ | |
106 | mal_desc_t *alloc_tx_buf; | |
107 | mal_desc_t *alloc_rx_buf; | |
108 | char *txbuf_ptr; | |
109 | uint16_t devnum; | |
110 | int get_link_status; | |
111 | int tbi_compatibility_en; | |
112 | int tbi_compatibility_on; | |
113 | int fc_send_xon; | |
114 | int report_tx_early; | |
115 | int first_init; | |
116 | int tx_err_index; | |
117 | int rx_err_index; | |
118 | int rx_slot; /* MAL Receive Slot */ | |
119 | int rx_i_index; /* Receive Interrupt Queue Index */ | |
120 | int rx_u_index; /* Receive User Queue Index */ | |
121 | int tx_slot; /* MAL Transmit Slot */ | |
122 | int tx_i_index; /* Transmit Interrupt Queue Index */ | |
123 | int tx_u_index; /* Transmit User Queue Index */ | |
124 | int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */ | |
125 | int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */ | |
126 | int is_receiving; /* sync with eth interrupt */ | |
127 | int print_speed; /* print speed message upon start */ | |
128 | EMAC_STATS_ST stats; | |
d6c61aab | 129 | } EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST; |
ba56f625 WD |
130 | |
131 | ||
846b0dd2 | 132 | #if defined(CONFIG_440GX) |
ba56f625 | 133 | #define EMAC_NUM_DEV 4 |
6e7fb6ea SR |
134 | #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \ |
135 | defined(CONFIG_NET_MULTI) && \ | |
6c5879f3 | 136 | !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) |
ba56f625 WD |
137 | #define EMAC_NUM_DEV 2 |
138 | #else | |
d6c61aab | 139 | #define EMAC_NUM_DEV 1 |
ba56f625 WD |
140 | #endif |
141 | ||
6c5879f3 MB |
142 | #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ |
143 | #define EMAC_STACR_OC_MASK (0x00008000) | |
144 | #else | |
145 | #define EMAC_STACR_OC_MASK (0x00000000) | |
146 | #endif | |
147 | ||
887e2ec9 SR |
148 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
149 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
6c5879f3 MB |
150 | #define SDR0_PFC1_EM_1000 (0x00200000) |
151 | #endif | |
ba56f625 WD |
152 | |
153 | /*ZMII Bridge Register addresses */ | |
887e2ec9 SR |
154 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
155 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
c157d8e2 SR |
156 | #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) |
157 | #else | |
ba56f625 | 158 | #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) |
c157d8e2 | 159 | #endif |
ba56f625 WD |
160 | #define ZMII_FER (ZMII_BASE) |
161 | #define ZMII_SSR (ZMII_BASE + 4) | |
162 | #define ZMII_SMIISR (ZMII_BASE + 8) | |
163 | ||
164 | #define ZMII_RMII 0x22000000 | |
165 | #define ZMII_MDI0 0x80000000 | |
166 | ||
167 | /* ZMII FER Register Bit Definitions */ | |
887e2ec9 | 168 | #define ZMII_FER_DIS (0x0) |
ba56f625 WD |
169 | #define ZMII_FER_MDI (0x8) |
170 | #define ZMII_FER_SMII (0x4) | |
171 | #define ZMII_FER_RMII (0x2) | |
172 | #define ZMII_FER_MII (0x1) | |
173 | ||
174 | #define ZMII_FER_RSVD11 (0x00200000) | |
175 | #define ZMII_FER_RSVD10 (0x00100000) | |
176 | #define ZMII_FER_RSVD14_31 (0x0003FFFF) | |
177 | ||
178 | #define ZMII_FER_V(__x) (((3 - __x) * 4) + 16) | |
179 | ||
180 | ||
181 | /* ZMII Speed Selection Register Bit Definitions */ | |
182 | #define ZMII_SSR_SCI (0x4) | |
183 | #define ZMII_SSR_FSS (0x2) | |
184 | #define ZMII_SSR_SP (0x1) | |
185 | #define ZMII_SSR_RSVD16_31 (0x0000FFFF) | |
186 | ||
187 | #define ZMII_SSR_V(__x) (((3 - __x) * 4) + 16) | |
188 | ||
189 | ||
190 | /* ZMII SMII Status Register Bit Definitions */ | |
191 | #define ZMII_SMIISR_E1 (0x80) | |
192 | #define ZMII_SMIISR_EC (0x40) | |
193 | #define ZMII_SMIISR_EN (0x20) | |
194 | #define ZMII_SMIISR_EJ (0x10) | |
195 | #define ZMII_SMIISR_EL (0x08) | |
196 | #define ZMII_SMIISR_ED (0x04) | |
197 | #define ZMII_SMIISR_ES (0x02) | |
198 | #define ZMII_SMIISR_EF (0x01) | |
199 | ||
200 | #define ZMII_SMIISR_V(__x) ((3 - __x) * 8) | |
201 | ||
202 | /* RGMII Register Addresses */ | |
887e2ec9 SR |
203 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
204 | #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000) | |
205 | #else | |
ba56f625 | 206 | #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790) |
887e2ec9 | 207 | #endif |
ba56f625 WD |
208 | #define RGMII_FER (RGMII_BASE + 0x00) |
209 | #define RGMII_SSR (RGMII_BASE + 0x04) | |
210 | ||
211 | /* RGMII Function Enable (FER) Register Bit Definitions */ | |
212 | /* Note: for EMAC 2 and 3 only, 440GX only */ | |
213 | #define RGMII_FER_DIS (0x00) | |
214 | #define RGMII_FER_RTBI (0x04) | |
215 | #define RGMII_FER_RGMII (0x05) | |
216 | #define RGMII_FER_TBI (0x06) | |
217 | #define RGMII_FER_GMII (0x07) | |
218 | ||
219 | #define RGMII_FER_V(__x) ((__x - 2) * 4) | |
220 | ||
221 | /* RGMII Speed Selection Register Bit Definitions */ | |
222 | #define RGMII_SSR_SP_10MBPS (0x00) | |
223 | #define RGMII_SSR_SP_100MBPS (0x02) | |
224 | #define RGMII_SSR_SP_1000MBPS (0x04) | |
225 | ||
887e2ec9 SR |
226 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
227 | #define RGMII_SSR_V(__x) ((__x) * 8) | |
228 | #else | |
ba56f625 | 229 | #define RGMII_SSR_V(__x) ((__x -2) * 8) |
887e2ec9 | 230 | #endif |
ba56f625 WD |
231 | |
232 | ||
233 | /*---------------------------------------------------------------------------+ | |
234 | | TCP/IP Acceleration Hardware (TAH) 440GX Only | |
235 | +---------------------------------------------------------------------------*/ | |
846b0dd2 | 236 | #if defined(CONFIG_440GX) |
ba56f625 WD |
237 | #define TAH_BASE (CFG_PERIPHERAL_BASE + 0x0B50) |
238 | #define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/ | |
239 | #define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */ | |
240 | #define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */ | |
241 | #define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */ | |
242 | #define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */ | |
243 | #define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */ | |
244 | #define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */ | |
245 | #define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */ | |
246 | #define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */ | |
247 | ||
ba56f625 WD |
248 | /* TAH Revision */ |
249 | #define TAH_REV_RN_M (0x000FFF00) /* Revision Number */ | |
250 | #define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */ | |
251 | ||
252 | #define TAH_REV_RN_V (8) | |
253 | #define TAH_REV_BN_V (0) | |
254 | ||
255 | /* TAH Mode Register */ | |
256 | #define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */ | |
257 | #define TAH_MR_SR (0x40000000) /* Software reset */ | |
258 | #define TAH_MR_ST (0x3F000000) /* Send Threshold */ | |
259 | #define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */ | |
260 | #define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */ | |
261 | #define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */ | |
262 | #define TAH_MR_RSVD (0x0007FFFF) /* Reserved */ | |
263 | ||
264 | #define TAH_MR_ST_V (20) | |
265 | #define TAH_MR_TFS_V (17) | |
266 | ||
267 | #define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */ | |
268 | #define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */ | |
269 | #define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */ | |
270 | #define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */ | |
271 | #define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/ | |
272 | ||
273 | ||
274 | /* TAH Segment Size Registers 0:5 */ | |
275 | #define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */ | |
276 | #define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */ | |
277 | #define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */ | |
278 | ||
279 | /* TAH Transmit Status Register */ | |
280 | #define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */ | |
281 | #define TAH_TSR_UH (0x40000000) /* Unrecognized header */ | |
282 | #define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */ | |
283 | #define TAH_TSR_IPOP (0x10000000) /* IP option present */ | |
284 | #define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */ | |
285 | #define TAH_TSR_ILTS (0x04000000) /* IP length too short */ | |
286 | #define TAH_TSR_IPFP (0x02000000) /* IP fragment present */ | |
287 | #define TAH_TSR_UP (0x01000000) /* Unsupported protocol */ | |
288 | #define TAH_TSR_TFP (0x00800000) /* TCP flags present */ | |
289 | #define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */ | |
290 | #define TAH_TSR_DLM (0x00200000) /* Data length mismatch */ | |
291 | #define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */ | |
292 | #define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */ | |
293 | #define TAH_TSR_SSTS (0x00040000) /* Segment size too small */ | |
294 | #define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */ | |
846b0dd2 | 295 | #endif /* CONFIG_440GX */ |
ba56f625 WD |
296 | |
297 | ||
298 | /* Ethernet MAC Regsiter Addresses */ | |
d6c61aab | 299 | #if defined(CONFIG_440) |
887e2ec9 SR |
300 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
301 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
c157d8e2 SR |
302 | #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) |
303 | #else | |
ba56f625 | 304 | #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) |
c157d8e2 | 305 | #endif |
d6c61aab SR |
306 | #else |
307 | #define EMAC_BASE 0xEF600800 | |
308 | #endif | |
ba56f625 WD |
309 | |
310 | #define EMAC_M0 (EMAC_BASE) | |
311 | #define EMAC_M1 (EMAC_BASE + 4) | |
312 | #define EMAC_TXM0 (EMAC_BASE + 8) | |
313 | #define EMAC_TXM1 (EMAC_BASE + 12) | |
314 | #define EMAC_RXM (EMAC_BASE + 16) | |
315 | #define EMAC_ISR (EMAC_BASE + 20) | |
316 | #define EMAC_IER (EMAC_BASE + 24) | |
317 | #define EMAC_IAH (EMAC_BASE + 28) | |
318 | #define EMAC_IAL (EMAC_BASE + 32) | |
319 | #define EMAC_VLAN_TPID_REG (EMAC_BASE + 36) | |
320 | #define EMAC_VLAN_TCI_REG (EMAC_BASE + 40) | |
321 | #define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44) | |
322 | #define EMAC_IND_HASH_1 (EMAC_BASE + 48) | |
323 | #define EMAC_IND_HASH_2 (EMAC_BASE + 52) | |
324 | #define EMAC_IND_HASH_3 (EMAC_BASE + 56) | |
325 | #define EMAC_IND_HASH_4 (EMAC_BASE + 60) | |
326 | #define EMAC_GRP_HASH_1 (EMAC_BASE + 64) | |
327 | #define EMAC_GRP_HASH_2 (EMAC_BASE + 68) | |
328 | #define EMAC_GRP_HASH_3 (EMAC_BASE + 72) | |
329 | #define EMAC_GRP_HASH_4 (EMAC_BASE + 76) | |
330 | #define EMAC_LST_SRC_LOW (EMAC_BASE + 80) | |
331 | #define EMAC_LST_SRC_HI (EMAC_BASE + 84) | |
332 | #define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88) | |
333 | #define EMAC_STACR (EMAC_BASE + 92) | |
334 | #define EMAC_TRTR (EMAC_BASE + 96) | |
335 | #define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100) | |
336 | ||
337 | /* bit definitions */ | |
338 | /* MODE REG 0 */ | |
339 | #define EMAC_M0_RXI (0x80000000) | |
340 | #define EMAC_M0_TXI (0x40000000) | |
341 | #define EMAC_M0_SRST (0x20000000) | |
342 | #define EMAC_M0_TXE (0x10000000) | |
343 | #define EMAC_M0_RXE (0x08000000) | |
344 | #define EMAC_M0_WKE (0x04000000) | |
345 | ||
17f50f22 | 346 | /* on 440GX EMAC_MR1 has a different layout! */ |
887e2ec9 SR |
347 | #if defined(CONFIG_440GX) || \ |
348 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
349 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
ba56f625 WD |
350 | /* MODE Reg 1 */ |
351 | #define EMAC_M1_FDE (0x80000000) | |
352 | #define EMAC_M1_ILE (0x40000000) | |
353 | #define EMAC_M1_VLE (0x20000000) | |
354 | #define EMAC_M1_EIFC (0x10000000) | |
355 | #define EMAC_M1_APP (0x08000000) | |
356 | #define EMAC_M1_RSVD (0x06000000) | |
357 | #define EMAC_M1_IST (0x01000000) | |
358 | #define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ | |
359 | #define EMAC_M1_MF_100MBPS (0x00400000) | |
360 | #define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ | |
361 | #define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ | |
362 | #define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ | |
363 | #define EMAC_M1_RFS_2K (0x00100000) | |
364 | #define EMAC_M1_RFS_1K (0x00080000) | |
365 | #define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ | |
366 | #define EMAC_M1_TX_FIFO_8K (0x00040000) | |
367 | #define EMAC_M1_TX_FIFO_4K (0x00030000) | |
368 | #define EMAC_M1_TX_FIFO_2K (0x00020000) | |
369 | #define EMAC_M1_TX_FIFO_1K (0x00010000) | |
370 | #define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */ | |
371 | #define EMAC_M1_MWSW (0x00007000) | |
372 | #define EMAC_M1_JUMBO_ENABLE (0x00000800) | |
373 | #define EMAC_M1_IPPA (0x000007c0) | |
374 | #define EMAC_M1_OBCI_GT100 (0x00000020) | |
375 | #define EMAC_M1_OBCI_100 (0x00000018) | |
376 | #define EMAC_M1_OBCI_83 (0x00000010) | |
377 | #define EMAC_M1_OBCI_66 (0x00000008) | |
378 | #define EMAC_M1_RSVD1 (0x00000007) | |
846b0dd2 | 379 | #else /* defined(CONFIG_440GX) */ |
17f50f22 SR |
380 | /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */ |
381 | #define EMAC_M1_FDE 0x80000000 | |
382 | #define EMAC_M1_ILE 0x40000000 | |
383 | #define EMAC_M1_VLE 0x20000000 | |
384 | #define EMAC_M1_EIFC 0x10000000 | |
385 | #define EMAC_M1_APP 0x08000000 | |
386 | #define EMAC_M1_AEMI 0x02000000 | |
387 | #define EMAC_M1_IST 0x01000000 | |
388 | #define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ | |
389 | #define EMAC_M1_MF_100MBPS 0x00400000 | |
390 | #define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ | |
391 | #define EMAC_M1_RFS_2K 0x00200000 | |
392 | #define EMAC_M1_RFS_1K 0x00100000 | |
393 | #define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ | |
394 | #define EMAC_M1_TX_FIFO_1K 0x00040000 | |
395 | #define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ | |
396 | #define EMAC_M1_TR0_MULTI 0x00008000 | |
397 | #define EMAC_M1_TR1_DEPEND 0x00004000 | |
398 | #define EMAC_M1_TR1_MULTI 0x00002000 | |
846b0dd2 | 399 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
17f50f22 | 400 | #define EMAC_M1_JUMBO_ENABLE 0x00001000 |
846b0dd2 SR |
401 | #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ |
402 | #endif /* defined(CONFIG_440GX) */ | |
17f50f22 | 403 | |
ba56f625 WD |
404 | /* Transmit Mode Register 0 */ |
405 | #define EMAC_TXM0_GNP0 (0x80000000) | |
406 | #define EMAC_TXM0_GNP1 (0x40000000) | |
407 | #define EMAC_TXM0_GNPD (0x20000000) | |
408 | #define EMAC_TXM0_FC (0x10000000) | |
409 | ||
410 | /* Receive Mode Register */ | |
411 | #define EMAC_RMR_SP (0x80000000) | |
412 | #define EMAC_RMR_SFCS (0x40000000) | |
413 | #define EMAC_RMR_ARRP (0x20000000) | |
414 | #define EMAC_RMR_ARP (0x10000000) | |
415 | #define EMAC_RMR_AROP (0x08000000) | |
416 | #define EMAC_RMR_ARPI (0x04000000) | |
417 | #define EMAC_RMR_PPP (0x02000000) | |
418 | #define EMAC_RMR_PME (0x01000000) | |
419 | #define EMAC_RMR_PMME (0x00800000) | |
420 | #define EMAC_RMR_IAE (0x00400000) | |
421 | #define EMAC_RMR_MIAE (0x00200000) | |
422 | #define EMAC_RMR_BAE (0x00100000) | |
423 | #define EMAC_RMR_MAE (0x00080000) | |
424 | ||
425 | /* Interrupt Status & enable Regs */ | |
426 | #define EMAC_ISR_OVR (0x02000000) | |
427 | #define EMAC_ISR_PP (0x01000000) | |
428 | #define EMAC_ISR_BP (0x00800000) | |
429 | #define EMAC_ISR_RP (0x00400000) | |
430 | #define EMAC_ISR_SE (0x00200000) | |
431 | #define EMAC_ISR_SYE (0x00100000) | |
432 | #define EMAC_ISR_BFCS (0x00080000) | |
433 | #define EMAC_ISR_PTLE (0x00040000) | |
434 | #define EMAC_ISR_ORE (0x00020000) | |
435 | #define EMAC_ISR_IRE (0x00010000) | |
436 | #define EMAC_ISR_DBDM (0x00000200) | |
437 | #define EMAC_ISR_DB0 (0x00000100) | |
438 | #define EMAC_ISR_SE0 (0x00000080) | |
439 | #define EMAC_ISR_TE0 (0x00000040) | |
440 | #define EMAC_ISR_DB1 (0x00000020) | |
441 | #define EMAC_ISR_SE1 (0x00000010) | |
442 | #define EMAC_ISR_TE1 (0x00000008) | |
443 | #define EMAC_ISR_MOS (0x00000002) | |
444 | #define EMAC_ISR_MOF (0x00000001) | |
445 | ||
446 | ||
447 | /* STA CONTROL REG */ | |
448 | #define EMAC_STACR_OC (0x00008000) | |
449 | #define EMAC_STACR_PHYE (0x00004000) | |
6c5879f3 MB |
450 | |
451 | #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ | |
452 | #define EMAC_STACR_INDIRECT_MODE (0x00002000) | |
453 | #define EMAC_STACR_WRITE (0x00000800) /* $BUC */ | |
454 | #define EMAC_STACR_READ (0x00001000) /* $BUC */ | |
455 | #define EMAC_STACR_OP_MASK (0x00001800) | |
456 | #define EMAC_STACR_MDIO_ADDR (0x00000000) | |
457 | #define EMAC_STACR_MDIO_WRITE (0x00000800) | |
458 | #define EMAC_STACR_MDIO_READ (0x00001800) | |
459 | #define EMAC_STACR_MDIO_READ_INC (0x00001000) | |
460 | #else | |
ba56f625 WD |
461 | #define EMAC_STACR_WRITE (0x00002000) |
462 | #define EMAC_STACR_READ (0x00001000) | |
6c5879f3 MB |
463 | #endif |
464 | ||
ba56f625 WD |
465 | #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */ |
466 | #define EMAC_STACR_CLK_66MHZ (0x00000400) | |
467 | #define EMAC_STACR_CLK_100MHZ (0x00000C00) | |
468 | ||
469 | /* Transmit Request Threshold Register */ | |
470 | #define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */ | |
471 | #define EMAC_TRTR_192 (0x10000000) | |
472 | #define EMAC_TRTR_128 (0x01000000) | |
473 | ||
474 | /* the follwing defines are for the MadMAL status and control registers. */ | |
475 | /* For bits 0..5 look at the mal.h file */ | |
476 | #define EMAC_TX_CTRL_GFCS (0x0200) | |
477 | #define EMAC_TX_CTRL_GP (0x0100) | |
478 | #define EMAC_TX_CTRL_ISA (0x0080) | |
479 | #define EMAC_TX_CTRL_RSA (0x0040) | |
480 | #define EMAC_TX_CTRL_IVT (0x0020) | |
481 | #define EMAC_TX_CTRL_RVT (0x0010) | |
482 | ||
483 | #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP) | |
484 | ||
485 | #define EMAC_TX_ST_BFCS (0x0200) | |
486 | #define EMAC_TX_ST_BPP (0x0100) | |
487 | #define EMAC_TX_ST_LCS (0x0080) | |
488 | #define EMAC_TX_ST_ED (0x0040) | |
489 | #define EMAC_TX_ST_EC (0x0020) | |
490 | #define EMAC_TX_ST_LC (0x0010) | |
491 | #define EMAC_TX_ST_MC (0x0008) | |
492 | #define EMAC_TX_ST_SC (0x0004) | |
493 | #define EMAC_TX_ST_UR (0x0002) | |
494 | #define EMAC_TX_ST_SQE (0x0001) | |
495 | ||
496 | #define EMAC_TX_ST_DEFAULT (0x03F3) | |
497 | ||
498 | ||
499 | /* madmal receive status / Control bits */ | |
500 | ||
501 | #define EMAC_RX_ST_OE (0x0200) | |
502 | #define EMAC_RX_ST_PP (0x0100) | |
503 | #define EMAC_RX_ST_BP (0x0080) | |
504 | #define EMAC_RX_ST_RP (0x0040) | |
505 | #define EMAC_RX_ST_SE (0x0020) | |
506 | #define EMAC_RX_ST_AE (0x0010) | |
507 | #define EMAC_RX_ST_BFCS (0x0008) | |
508 | #define EMAC_RX_ST_PTL (0x0004) | |
509 | #define EMAC_RX_ST_ORE (0x0002) | |
510 | #define EMAC_RX_ST_IRE (0x0001) | |
511 | /* all the errors we care about */ | |
512 | #define EMAC_RX_ERRORS (0x03FF) | |
513 | ||
d6c61aab | 514 | #endif /* _PPC4XX_ENET_H_ */ |