[thirdparty/u-boot.git] / include / sandbox-clk.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2019
 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
 */

#ifndef __SANDBOX_CLK_H__
#define __SANDBOX_CLK_H__

#include <linux/clk-provider.h>

enum {
	SANDBOX_CLK_PLL2 = 1,
	SANDBOX_CLK_PLL3,
	SANDBOX_CLK_PLL3_60M,
	SANDBOX_CLK_PLL3_80M,
	SANDBOX_CLK_ECSPI_ROOT,
	SANDBOX_CLK_ECSPI0,
	SANDBOX_CLK_ECSPI1,
	SANDBOX_CLK_USDHC1_SEL,
	SANDBOX_CLK_USDHC2_SEL,
	SANDBOX_CLK_I2C,
	SANDBOX_CLK_I2C_ROOT,
};

enum sandbox_pllv3_type {
	SANDBOX_PLLV3_GENERIC,
	SANDBOX_PLLV3_USB,
};

struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
			      const char *parent_name, void __iomem *base,
			      u32 div_mask);

static inline struct clk *sandbox_clk_fixed_factor(const char *name,
						   const char *parent,
						   unsigned int mult,
						   unsigned int div)
{
	return clk_register_fixed_factor(NULL, name, parent,
			CLK_SET_RATE_PARENT, mult, div);
}

static inline struct clk *sandbox_clk_divider(const char *name,
					      const char *parent,
					      void __iomem *reg, u8 shift,
					      u8 width)
{
	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
			reg, shift, width, 0);
}

static inline struct clk *sandbox_clk_gate(const char *name, const char *parent,
					   void __iomem *reg, u8 bit_idx,
					   u8 clk_gate_flags)
{
	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT,
				 reg, bit_idx, clk_gate_flags, NULL);
}

struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
				       const char *parent_name,
				       unsigned long flags,
				       void __iomem *reg, u8 bit_idx,
				       u8 cgr_val, u8 clk_gate_flags);

static inline struct clk *sandbox_clk_gate2(const char *name,
					    const char *parent,
					    void __iomem *reg, u8 shift)
{
	return sandbox_clk_register_gate2(NULL, name, parent,
					  CLK_SET_RATE_PARENT, reg, shift,
					  0x3, 0);
}

static inline struct clk *sandbox_clk_mux(const char *name, void __iomem *reg,
					  u8 shift, u8 width,
					  const char * const *parents,
					  int num_parents)
{
	return clk_register_mux(NULL, name, parents, num_parents,
				CLK_SET_RATE_NO_REPARENT, reg, shift,
				width, 0);
}

int sandbox_clk_enable_count(struct clk *clk);

#endif /* __SANDBOX_CLK_H__ */
Commit	Line	Data
87e460c3 LM	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright (C) 2019
	4	* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
	5	*/
	6
	7	#ifndef __SANDBOX_CLK_H__
	8	#define __SANDBOX_CLK_H__
	9
	10	#include <linux/clk-provider.h>
	11
	12	enum {
	13	SANDBOX_CLK_PLL2 = 1,
	14	SANDBOX_CLK_PLL3,
	15	SANDBOX_CLK_PLL3_60M,
	16	SANDBOX_CLK_PLL3_80M,
	17	SANDBOX_CLK_ECSPI_ROOT,
	18	SANDBOX_CLK_ECSPI0,
	19	SANDBOX_CLK_ECSPI1,
	20	SANDBOX_CLK_USDHC1_SEL,
	21	SANDBOX_CLK_USDHC2_SEL,
8f611dc7	22	SANDBOX_CLK_I2C,
c66f4f5e	23	SANDBOX_CLK_I2C_ROOT,
87e460c3 LM	24	};
	25
	26	enum sandbox_pllv3_type {
	27	SANDBOX_PLLV3_GENERIC,
	28	SANDBOX_PLLV3_USB,
	29	};
	30
	31	struct clk sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char name,
	32	const char parent_name, void __iomem base,
	33	u32 div_mask);
	34
	35	static inline struct clk sandbox_clk_fixed_factor(const char name,
	36	const char *parent,
	37	unsigned int mult,
	38	unsigned int div)
	39	{
	40	return clk_register_fixed_factor(NULL, name, parent,
	41	CLK_SET_RATE_PARENT, mult, div);
	42	}
	43
	44	static inline struct clk sandbox_clk_divider(const char name,
	45	const char *parent,
	46	void __iomem *reg, u8 shift,
	47	u8 width)
	48	{
	49	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
	50	reg, shift, width, 0);
	51	}
	52
cd16c57b DB	53	static inline struct clk sandbox_clk_gate(const char name, const char *parent,
	54	void __iomem *reg, u8 bit_idx,
	55	u8 clk_gate_flags)
	56	{
	57	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT,
	58	reg, bit_idx, clk_gate_flags, NULL);
	59	}
	60
87e460c3 LM	61	struct clk sandbox_clk_register_gate2(struct device dev, const char *name,
	62	const char *parent_name,
	63	unsigned long flags,
	64	void __iomem *reg, u8 bit_idx,
	65	u8 cgr_val, u8 clk_gate_flags);
	66
	67	static inline struct clk sandbox_clk_gate2(const char name,
	68	const char *parent,
	69	void __iomem *reg, u8 shift)
	70	{
	71	return sandbox_clk_register_gate2(NULL, name, parent,
	72	CLK_SET_RATE_PARENT, reg, shift,
	73	0x3, 0);
	74	}
	75
	76	static inline struct clk sandbox_clk_mux(const char name, void __iomem *reg,
	77	u8 shift, u8 width,
	78	const char * const *parents,
	79	int num_parents)
	80	{
	81	return clk_register_mux(NULL, name, parents, num_parents,
	82	CLK_SET_RATE_NO_REPARENT, reg, shift,
	83	width, 0);
	84	}
	85
c66f4f5e PF	86	int sandbox_clk_enable_count(struct clk *clk);
c66f4f5e PF	87
87e460c3	88	#endif /* __SANDBOX_CLK_H__ */